multigate review lecture.pdf

446 IETE TECHNICAL REVIEW | VOL 27 | ISSUE 6 | NOV-DEC 2010

Multiple Gate Field-Effect Transistors for Future CMOS Technologies

Vaidyanathan SubramanianCompact Modeling and Enablement Croup, IBM SRDC (India), Bangalore, India

Abstract

This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolu-tion of FinFET technologies; the main flavors (variants) of multigate FETs; and their advantages/disadvan-tages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspec-tive on the future of the FinFET technology is presented. This paper is a judicious mix of the author’s original work on FinFETs and other contemporary know-how available in the literature on this topic.

KeywordsCMOS scaling, Double gate MOSFET, FinFET, Multiple gate FET, Multigate FET.

1. Motivation Behind Multigate Field-Effect Transistors

The phenomenon of short channel effects (SCEs) in metal–oxide–semiconductor field-effect transistors (MOSFETs) has been known since the late 1970s. As gate lengths are reduced, threshold voltages are seen to decrease and OFF-state currents are seen to increase. This is a consequence of the fact that as gate lengths are decreased, the depletion regions associated with the source-to-body and drain-to-body regions become closer to each other and start to interact with each other. Since depletion regions are regions of high electric fields, they facilitate carrier transport directly between the source and drain regions, which gives rise to the observed phe-nomena of higher OFF-state currents, reduced threshold voltages, and reduced control of the gate over transistor characteristics in MOSFETs. Classical scaling approaches have dealt with this problem by requiring an increase in body doping, thereby decreasing the depletion widths associated with the source-to-body and drain-to-body regions, so that these two junctions are kept separated to the extent possible. However, increasing the body doping is accompanied by severe drawbacks such as degraded mobilities, increased capacitances, and increased statisti-cal fluctuations, all of which pose serious challenges to scaling. Innovative solutions such as dynamic threshold voltage MOSFETs (DTMOS) have been successfully used to reduce the leakage power consumption of analog and digital circuits [1-3].

An alternate way to increase the gate control over the channel would be to have an extra gate. This additional

gate would help strengthen the immunity of the channel from penetration effects of the drain electric field. In this approach, the main lever for controlling the channel is not with the body doping, but the separation between the two gates. In fact the body doping is deliberately kept at a very low value, at near-intrinsic levels. This helps avoid the problems of mobility degradation, higher junc-tion capacitances, and stochastic fluctuations. Undoped double gate MOSFETs (DG MOSFETs) are thus a better option from the point of view of long-term scalability and extendability to future CMOS technologies.

2. Evolution of Multigate FETs

The seriousness of the problem of short channel effects in single gate MOSFET transistors, and the potential dif-ficulties associated with their scaling by increasing body doping became evident way back in the early 1990s, and many true DG MOSFET architectures were proposed. A very good overview of these architectures is given in [4-9]. Based on their orientation, Wong [5,6] grouped the double gate architectures into planar (or Type I), verti-cal pillar (or Type II), and vertical (or Type III). These are illustrated in Figure 1. As explained in [6], Type I DG MOSFETs have horizontal planarity and horizontal current flow, and feature gates on the top and bottom sides of the silicon body. The advantage of this topology is that the quality and thickness of the silicon film can be accurately controlled by the epitaxial process. On the other hand, they suffer from the need to accurately align the top and bottom gates. Any misalignment results in the degradation of device properties. This is quite chal-lenging; nevertheless, this topology has been realized

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447IETE TECHNICAL REVIEW | VOL 27 | ISSUE 6 | NOV-DEC 2010

in practice [5,10]. Type II DG MOSFETs, at the other extreme, have vertical orientation and vertical current flow. The achievable packing density of these transistors is the highest; however, they suffer from considerable difficulties when it comes to the formation of the source and drain regions and very large scale integration schemes. For this reason, Type II DG MOSFETs did not gain in popularity. Type III MOSFETs, on the other hand, feature current flow along fin sidewalls but in the horizontal direction. They are thus more area efficient compared to Type I DG MOSFETs, and at the same time less complicated than Type II DG MOSFETs.

In 1990, Hisamoto proposed a Type III DG MOSFET topology with the name fully depleted lean-channel transistor (DELTA) [11]. The fabrication sequence of the DELTA is described in [11], and is briefly summarized here as follows. Starting with a bulk Si wafer, pad oxide and nitride hardmask are formed over active areas, and the remaining areas are subjected to reactive ion etch-ing (RIE) which results in the removal of silicon, leaving behind islands of silicon. This is followed by gate oxide growth, after which a protective nitride layer is deposited on top of the gate oxide. The substrate is now oxidized at 1100°C, resulting in the conversion of the silicon to silicon dioxide. The insulating oxide is thus formed thermally, and serves to isolate the transistors from one another. The resulting device looks a lot like the modern day FinFET, and is shown in Figure 2. The DELTA topology did not gain momentum at that time since the classical planar MOSFET topology was meeting the transistor specifications satisfactorily.

In the subsequent years, as scaling challenges became more severe, the DG MOSFET architecture was revisited, and the DELTA topology made a comeback a decade later, this time under the name 'FinFET' [12]. This time, it captured the attention and fascination of the scientific community, and the subsequent few years saw an explo-sion in research and development efforts into FinFETs [13-20]. There are two minor variants of the FinFET, namely, the omega-gate FinFET and the pi-gate FinFET, which are named following the shape of the overlapping gate over the fin. In the case of the omega-gate FinFET, the gate undercuts and partially covers the bottom sur-face of the fin as well, whereas in the case of the pi-gate FinFET, the gate extends to a depth below the bottom of the silicon fin. The objective of these structures is to achieve an additional gate control over the channel and prevent fringing fields from penetrating into the silicon body. Figure 3 shows these two variants of the FinFET.

And then we have the gate wrap-around FET, or gate all-around (GAA) FET, or surround-gate FET, where the silicon is surrounded on all sides by the gate. Such a transistor is also known as a nanowire FET, and rep-

resents the ultimately scaled MOSFET device, i.e., the device with the maximum possible gate control over the channel. This device is shown in Figure 4. Such a device was proposed as early as 1990 [22].

Subramanian V: Multiple Gate Field-Effect Transistors for Future CMOS Technologies

Figure 1: Double gate MOSFET topologies: Planar (Type I), vertical (Type II) and vertical (Type III) (after [6]). The FinFET belongs to the Type III category

Figure 2: The Fully Depleted Lean Channel Transistor (DELTA) topology, introduced in 1989 by Hisamoto et al. (from [11]). The DELTA is the predecessor to the FinFET.

Figure 3: Pi- and Omega-gate FinFETs. The name is derived from the shape of the gate as seen in the cross-sectional view. From Colinge [21].




3. Fabrication Technology

We will now look at technology aspects of FinFETs, which can be defined as undoped Type III double gate silicon-on-insulator (SOI) MOSFETs with current flow in the horizontal (i.e., left to right) direction along the top and sides of a thin slice of silicon, i.e., the “fin.” The start-ing substrate is a SOI wafer with a buried oxide (BOX) thickness around 150 nm. The thickness of the silicon is ≈70 nm, and the silicon is of lightly doped p-type with the dopant concentration ≈1 × 1015cm−3, which ensures fully depleted device operation. The main modules in a FinFET process are those related to fin formation, gate stack formation, and source/drain extension forma-tion. The FinFET process can either follow a “gate-first” route, or a “gate-last” route [23]. In the former route, fin formation is followed by gate stack formation followed by extension formation, whereas in the latter route, fin formation is followed by extension formation followed by gate stack formation. Both routes have been used for fabricating well-functioning FinFETs down to 20 nm gate

lengths. FinFETs are fabricated with fin widths that are typically less than one-half of the minimum gate lengths. Such dimensions are typically sublithographic, and not possible to define directly in a single-step process. Tech-niques such as e-beam lithography can be used to pattern the fins directly; however, this route is not preferred for production due to high equipment cost and low manufacturing throughput. Hence fin patterning needs to make use of creative techniques in order to pattern such sublithographic dimensions. Two of the mainstream techniques for fin definition are resist-defined fin (RDF) patterning and spacer-defined fin (SDF) patterning. A schematic flow of the RDF process is shown in Figure 5.

In this process, a thick (≈100 nm) hardmask is deposited on the silicon. This is followed by a deposition of a positive photoresist and exposure using 193-nm DUV lithography in order to define the active areas. Unexposed areas of the photoresist are removed, exposing the hardmask beneath, which is then etched using an anisotropic etch process. After the hardmask is removed from the exposed areas using a HF-based isotropic (wet) etch, trimming of the resist/hardmask stack is performed in order to reduce the thickness down to the desired sublithographic dimen-sion. Once the hardmask thickness has been brought to the desired value, once again an aggressive, directional etch is carried out, this time etching into the silicon film, while the resist/hardmask combination serves to protect those areas that will eventually form the fins. This etch is continued till all the unprotected silicon has been etched away, and then the hardmask on top of the silicon is also removed to reveal the fin areas.

A schematic of the SDF process is illustrated in Figure 6. In this approach, a sacrificial SiGe film is blan-ket deposited on top of the silicon film and patterned in such a way that the width of this sacrificial SiGe defines the final fin-to-fin spacing. This is followed by


Figure 4: Gate wrap-around or Gate all-around or surround-gate FET, introduced by Colinge et al (from [22]). This is a predecessor to the ultimately scaled device, i.e., the nano-wire FET.

Figure 5: Process flow for Resist Defined Fin (RDF) technology.

Figure 6: Process flow for Spacer Defined Fin (SDF) technology.




the formation of a thin nitride spacer along the sidewalls of the SiGe. Next the SiGe is removed, leaving behind the nitride spacers, which serve as a hardmask during the subsequent etch of the silicon film. The thickness of the spacer translates into the resulting width of the fins. This is the SDF formation process. Depending on the process control and the desired fin widths, this process of sidewall spacer formation and etching can even be carried out one more time to result in even smaller fin widths. High fin patterning densities can be obtained using the SDF process; however, in this instance the fin width is fixed by the technology, and it is not possible to use it as a design variable, since arbitrary fin widths are not supported in this technology. More information on the SDF patterning approach can be found in [16,24-26].

Fin width definition is followed by a hydrogen anneal-ing step in order to relax the stresses and defects at the surface which may have resulted due to aggressive etch chemistries employed for fin definition. This hydrogen annealing step also smoothens the sharp edges of the FinFET’s cross section, resulting in a rounded profile, which reduces the problems of electric field crowding and corner effects. Figure 7 is a top view of a FinFET before and after hydrogen anneal, showing the effect of corner rounding.

The next important module is that of gate stack forma-tion. As indicated earlier, there are two options: the “gate-first” approach and the “gate-last” approach. In the gate-first approach [13,27-29], the gate dielectric is formed, followed by a deposition of the gate electrode on top. The resist is deposited on top of this, and the stack comprising the gate dielectric, gate electrode, and the resist is patterned and subsequently trimmed in order to achieve the desired gate length. The resist is removed. The source and drain extension region, also known as the lightly doped drain (LDD) region is formed. Halo (pocket) implants are typically absent in FinFET pro-cesses, and so are threshold adjust implants. The next step is that of spacer formation. This is followed by an optional selective epitaxial growth (SEG) process, where the source and drain regions are thickened by conformal deposition of silicon (or SiGe). This is done in order to ease the difficulties of current crowding in the extension regions and reduce the contact and spreading resistances, thereby reducing the overall series resistance. This is followed by heavily doped drain (HDD) region forma-tion, silicidation, premetal dielectric (PMD) deposition, contact formation, and back-end-of-line (BEOL) steps completing the fabrication sequence. The above fabrica-tion sequence is shown schematically in Figure 8.

In the gate-last process [12,30,31], the source/drain is formed immediately after fin patterning. Doped poly-silicon or polycrystalline SiGe is deposited on the fin,

followed by a patterning which defines the source/drain extension regions. Spacer is grown on the insides of this region, and is followed by gate stack deposition and patterning. A picture of the FinFET at the end of its fabrication sequence is shown in Figure 9.

4. Device Performance

There are many device parameters and figures of merit based on which one can assess the overall device per-formance. To assess the DC and low-frequency analog performance, we look at device parameters such as the parasitic resistance, mobility, saturation velocity, and corresponding figures of merit such as the drive current (ION), leakage current (IOFF), transconductance (Gm), out-put conductance (Gds), and voltage gain (Gm/Gds). These are obtained from I–V and low-frequency C–V measure-ments. To assess the high-frequency (RF) performance, we perform two-port S-parameter measurements from which we obtain the high-frequency transconductance, output conductance, parasitic resistance, and capaci-

(a) Before corner rounding

(b) After corner rounding

Figure 7: Top view of a FinFET before and after corner round-ing step.

Figure 8: Main modules in the FinFET fabrication sequence.

Figure 9: The FinFET at the end of the Front-End-Of-Line (FEOL) steps.





tance, and corresponding RF figures of merit such as the unity gain current frequency (or cutoff frequency), fT, and the unity power gain frequency (or oscillation frequency), fmax. There are also important considerations such as low-frequency noise, high-frequency noise and current mismatch, and the overall device performance is thus a complex function of all of these. The FinFET’s performance also depends strongly on the width of the patterned fins, known as the fin width. In this paper, we will show trends in some of the key device parameters and figures of merit for FinFETs, and compare them with those of planar bulk MOSFETs.

4.1 DC and Low-Frequency Analog Performance

4.1.1 Source/Drain Resistance

Shown in Figure 10 is a plot of the total resistance in the linear region (RTOTAL) versus the mask length (Lmask) for a FinFET and a planar MOSFET. The extrapolation of this curve yields the value of the source/drain resis-tance, RS. Using this procedure we obtain the RS of the FinFET to be equal to 200 Ω.μm, while that of the planar MOSFET is obtained to be 50 Ω.μm. The source/drain series resistance of FinFETs is thus found to be higher than that of the planar MOSFET. This aspect of a higher series resistance in FinFETs has been investigated in detail in [32], and it has been concluded that this is due to the high contact resistance that develops as the current flow changes from a vertical plane in the channel to a horizontal plane in the source and drain regions. As this component is present only in FinFETs and not in planar MOSFETs, the series resistance of FinFETs is higher. This is an important difference between FinFETs and planar MOSFETs, and also one of the challenges of the FinFET

technology [33]. Techniques such as selective epitaxial growth and conformal doping have been partially suc-cessful in reducing this difference and bringing the FinFET’s source/drain resistance to acceptable levels.

4.1.2 Mobility and Saturation Velocity

We now compare the mobility and saturation veloc-ity of FinFET and planar bulk MOSFET technologies. Figure 11 compares the mobility of FinFETs with that of planar bulk MOSFETs. It is seen that the FinFET has a higher peak mobility at lower electric fields compared to the planar bulk MOSFET, which has a lower peak mobil-ity and also higher electric fields. This can be explained on the basis of lower doping concentrations in FinFETs, whereas the doping levels are much higher in the case of planar bulk MOSFETs. Lower doping levels result in lower electric fields as well as reduced scattering (hence higher mobilities), whereas higher doping levels result in higher electric fields and higher scattering, hence lower mobilities.

Figure 12 shows the saturation velocity of FinFETs and planar bulk MOSFETs as a function of the gate length. The saturation velocity of FinFETs is seen to be lower than that of planar bulk MOSFETs. This is due to two reasons, namely, the difference in the dominant crystal orientation of the planar bulk (100) compared to the Fin-FET (110), and the smaller volume available for the flow of carriers in the velocity saturated part of the channel for the FinFET compared to the planar bulk MOSFET.

4.1.3 Transconductance and Voltage Gain

Two of the important analog figures of merit are the

Figure 10: Source/Drain resistance extraction from a plot RTOTAL vs L. The S/D Series resistance of FinFETs is seen to be 3-4 times higher than planar MOSFETs. This is due to higher spreading resistance encountered in FinFETs due to its 3-dimensional current flow path.

Figure 11: Comparison of mobility in FinFETs versus planar bulk MOSFETs. At lower electric fields, mobility of FinFETs is higher owing to reduced coulomb scattering which is due to their lower doping. Mobility is extracted using the split CV method, and the channel length is equal to 1 µm.





transconductance (Gm) and the voltage gain (Av). In Figure 13a and b we show the transconductance and the voltage gain, respectively, as a function of the gate length for gate voltage overdrives of 0.2 V and 0.6 V. For both the FinFET and the planar bulk MOSFET, the transconductance is seen to saturate at short gate lengths; however, this effect is more predominant in the case of the FinFET compared to the planar bulk MOSFET, and more so at an overdrive of 0.6 V. The scaling behavior of the Gm of the planar bulk MOSFET is thus better than that of the FinFET as we go to shorter lengths and larger gate drives. On the other hand, the voltage gain of the FinFET is much better than that of the MOSFET over the entire range of lengths and gate drives; even though this difference decreases somewhat on going to short lengths, FinFETs still have two to three times higher voltage gain compared to planar bulk MOSFETs. This information is depicted in another way in Figure 14, which plots the transconductance versus voltage gain of planar bulk MOSFETs and FinFETs at gate voltage overdrives of 0.2 V and 0.6 V. The different data points in the graph correspond to different gate lengths ranging from 60 nm to 500 nm. If we first compare the planar bulk MOSFET and FinFET at a gate voltage overdrive of 0.2 V (dark and light squares, respectively), we see that for the same gate lengths, FinFETs are able to achieve a voltage gain that is an order of magnitude higher, at roughly similar (or a slightly reduced) transconductance. At a gate voltage overdrive of 0.6 V, the gap between the achievable trans-conductance becomes significantly large (as much as two times). Thus at low gate voltage overdrives, FinFETs have superior performance compared to planar bulk MOSFETs, but this performance advantage is rapidly

lost upon increasing the gate voltage overdrive, which is due to a combination of a high series resistance and a low saturation velocity. At medium to high gate voltage overdrives, planar bulk MOSFETs have much better Gm’s due to their low series resistances and higher saturation velocities. There is thus a performance-based trade-off between the planar bulk MOSFET and the FinFET.

4.2 High-Frequency (RF) Performance

Till now we have looked at the DC and low-frequency analog performance of FinFETs and benchmarked it against that of planar FETs. FinFETs are observed to have a high source/drain series resistance, which degrades their currents and transconductances. At High-Frequency(s) (RF) frequencies, the device performance is additionally impacted due to parasitic capacitances. There are several components of parasitic capacitance in a conventional planar MOSFET. These comprise the outer fringing capacitance (Cof), the inner fringing capaci-tance (Cif), the overlap capacitance (Cov) and the top plate capacitance (Ctop). These are shown in Figure 15.

In a FinFET, apart from the above-mentioned compo-nents, there exist additional parasitic capacitance com-ponents on account of their three-dimensional nature. Considerable work on these additional parasitic capaci-tances has been done by Wu et al. [34]. The major addi-tional parasitic capacitance component in FinFETs is the one between the gate and the inner walls of the source, drain, and the access lines. This is shown in Figure 16.

The combined effect of the reduced analog transcon-ductance and the increased parasitic capacitance is to degrade the cutoff frequency, fT, which is proportional to the ratio of the transconductance to the total gate capacitance (which includes the parasitic capacitance). This is shown in Figure 17. In this figure, we have plotted the “extrinsic” fT, which is the actual cutoff frequency,

Figure 12: Comparison of saturation velocity in FinFETs versus Planar bulk MOSFETs. Due to the dominant (110) orientation, and due to the smaller volume available for current flow, in FinFETs, their saturation velocity is lower compared to planar MOSFETs. Saturation velocity is calculated as the ratio of peak intrinsic transconductance (Gmmax,i/W) to specific oxide capacitance (Coxsp).

(a) Length scaling of transconductance (b) Length scaling of voltage gain

Figure 13: Length scaling of transconductance (Gm) and voltage gain (Av) of FinFETs and planar MOSFETs. FinFETs show a lower transconductance on account of a higher series resistance and lower saturation velocity, and a higher voltage gain due to a much lower output conductance which offsets the reduced transconductance.





Figure 14: Plot of transconductance (Gm) versus voltage gain (Av) of FinFETs versus planar bulk MOSFETs for gate voltage overdrives of 0.2 V and 0.6 V. Dark symbols represent planar bulk MOSFETs, while light symbols represent FinFETs. Pla-nar bulk is able to reach high Gm but at reduced Av, while the opposite is true for FinFETs.

Figure 15: Parasitic capacitances in a conventional planar MOSFET. It is comprised of the top fringing capacitance, outer fringing capacitance, inner fringing capacitance and the and gate overlap (or LDD underlap) capacitance.

Figure 16: Important component of a FinFET’s parasitic capacitance is the one existing between the gate and the inner walls of the source, drain and the access lines.

taking into account the additional parasitic capacitances, as well as the “intrinsic” fT, which is the maximum achievable cutoff frequency in the absence of parasitic capacitances. The impact of higher parasitic capacitances is clearly seen: in the absence of parasitic capacitances, the cutoff frequencies of FinFETs and planar MOSFETs are nearly identical, whereas in the presence of parasitic capacitances, the FinFET exhibits a much reduced cutoff frequency as compared to the planar FET.

4.3 Impact of the Fin Width

An important determinant of the FinFET performance is the width of the patterned width, known as the fin width

(Wfin). The fin width is very important as it controls the electrostatics of a FinFET, and thereby it strongly affects its performance. Going to a narrower fin width increases the electrostatic control of the gate over the channel, thereby suppressing short channel effects and making it possible to scale the channel length even further. From an analog point of view, an increased gate control of the channel translates into a decreased drain control over the channel, resulting in a decreased channel length modula-tion and lower output conductance (Gds), which is desir-able. There are two main drawbacks to decreasing the fin width. The first is the lower electron mobility of the (110)

Figure 17: Comparison of intrinsic and extrinsic cutoff frequencies of FinFETs and planar FETs. While the intrinsic cutoff frequencies of FinFETs is nearly equal to that of planar FETs, the extrinsic cutoff frequency is much reduced owing to higher parasitic capacitances.





sidewall as compared to the (100) top surface. This can be circumvented by changing the sidewall orientation of nFinFETs. The hole mobility of the (110) sidewall is in fact higher than the (100) orientation; hence, pFinFET performance is expected to be improved compared to planar pFETs. The second drawback to decreasing the fin width is from a technological point of view: it is more challenging to fabricate narrow-width FinFETs on two counts: series resistance and variability. Due to current crowding issues, the series resistance of narrow fins increases dramatically, degrading the drive current and transconductance. Secondly, process-induced variations in the fins become more prominent on going to narrower fin widths. This is known as “fin width roughness” and has a strong negative impact on the device-to-device variability, degrading the mismatch parameters. For example, the use of selective epitaxial growth (SEG) on the source and drain regions is known to alleviate the series resistance problem, and the fin roughness is sensitive to variables such as the fin definition method, the type and thickness of the sacrificial spacer, the etch recipe, etc. Hence the choice of fin width is to be made by carefully weighing all the relative pros and cons from a physical as well as a technological point of view.

4.4 Noise and Mismatch

Noise and mismatch are important considerations for analog and RF applications. The low-frequency (1/f) noise as well as the mismatch is dependent on the quality of the fin wall, which depends on the process-induced roughness. Since there is a strong correlation between fin width and fin roughness, we observe a strong correlation between fin width and the noise/mismatch performance. For extremely narrow fins which suffer from roughness as well as series resistance problems, we see higher noise and mismatch parameters. In the case of FinFETs with somewhat relaxed fin width, we see that the noise is comparable to planar FETs, while the mismatch perfor-mance is better. The improved mismatch in this case is attributed to a combination of a lower channel doping and the absence of threshold voltage implants and halo implants in the case of FinFETs.

5. Summary and Conclusions

In this paper, we have taken a comprehensive look at undoped double gate MOSFETs, also known as MuG-FETs or FinFETs, which are promising candidates for scaling CMOS into the sub-32 nm era on account of their potentially improved channel control and reduced dopant fluctuations. We first presented the motivation behind multigate FETs, and then traced the evolution of multigate FETs, and also discussed the classification of multigate FETs based on current flow. We then outlined the aspects of the FinFET’s fabrication technology. We

then went into the many aspects of the FinFET’s perfor-mance by looking at their DC, low-frequency analog, and high-frequency (RF) performance parameters, and by benchmarking the FinFET’s performance with that of the planar bulk MOSFET, and discussing their relative merits and demerits. No discussion on FinFETs would be complete without discussing the impact of the fin width. Here again, we looked at the many trade-offs involving fin width considerations. We also discussed briefly the noise and mismatch performance of FinFETs and con-cluded by making an overall assessment of the FinFET technology. In conclusion, FinFETs are a promising choice for scaling CMOS into the sub-32 nm era as they are motivated by sound theoretical principles. However, they suffer from the problems of high parasitics and fin roughness. The success of the FinFET technology depends largely on the ability to overcome these two considerable challenges.

6. Acknowledgments

The author wishes to acknowledge IMEC’s industrial affiliation programs, Nano-RF and EMERALD, for supporting this work.

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AUTHORVaidyanathan Subramanian received his Bachelors’ Degree in Materials Science and Engineering from IIT Chennai in 2000 and his Masters’ Degree in Electrical Engineering from Penn State University, USA. From 2003 to 2008, he was a researcher at IMEC, Belgium, where he worked on aspects of technology, characterization and modeling of deep sub-micron

DOI: 10.4103/0256-4602.72582; Paper No TR 12_10; Copyright © 2010 by the IETE

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CMOS devices. In 2008, he obtained his PhD from KU Leuven, Belgium on the topic “Analog/RF performance of Multiple Gate MOSFETs”. Since 2008, he is working in the Compact Modeling and Enablement Group, IBM SRDC, Bangalore, India on FET modeling for analog/RF/mixed signal Industry Process Design Kits (PDKs). His expertise includes Multi-Gate (FinFET) modeling, Bulk & SOI FET modeling, High Voltage FET modeling and ESD FET modeling. He has (co)-authored more than 25 papers.

E-mail: : [email protected]



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