Workshop on the Future of Spintronics, June 5, 2016 1

MTJ based Random Number Generation and Analog-to-Digital

Conversion

Chris H. KimUniversity of Minnesota

Switching Probability of an MTJSwitching probability (%)

1009080706050403020

0

Pulse amplitude (V)0.4 0.5 0.6 0.7 0.8 0.9 1.0

Puls

e w

idth

(ns)

123456789

10

Psw=50% Psw=100% 10

Psw=0%

H. Zhao, JP Wang, JAP, 2011

• Psw=100% (write) or 0% (read) : STT-MRAM• Psw=50% switching: Random number generation• 0%<Psw<100%: Analog to digital conversion, time to

digital conversion 6

Anti-parallel:High R

Parallel: Low R

MTJ based TRNG- Unconditional Reset Scheme -

• 50% switching utilized for generating random bits• Large reset voltage required every cycle slow,

high power, short lifetime

V

VPERTURB+

VRESET

0

One cycleRepeat

tRESET tREAD

1. Reset 2. Perturb

3. Read resolved stateTime

tPERTURB

7

New Conditional Perturb Scheme

• Perturbs MTJ according to the previously sampled MTJ state, thereby eliminating the reset phase fast, low power, long lifetime

V

VPERTURB+

VPERTURB-

0

One cycleRepeat

tREAD

2. Conditional Perturb

1. Read resolved state

Time

tPERTURB

8

MTJ Measurement Setup

• Random number generator measurement setup with sub-50 ps pulse width resolution

Pulse Generator 1(Picosecond 10070ATM)

Pulse Generator 2(*HP 8110ATM or

**Picosecond 10060ATM)

Power Combiner

(Picosecond 5331-104TM)

Bias-Tee(Picosecond 5542-229TM)

MTJ

DAQ Board (NI PCI-6251TM)

LabV

iew

TM In

terf

ace

ADCResistance

Random Number

Reset or -Perturb

+Perturb

Read10kOhm

11

MgO 0.85nm

Capping layerCo20Fe60B20 1.9nm

Co40Fe40B20 2.4nmRu 0.85nm

Co70Fe30 2.3nm

PtMn 15nm

Seed layer

Dimension 170x50nm2

RATMR 107%

5.26 Ω∙μm2

100nm

Thermal stability 61

W. Choi, Y. Lv, JP Wang, C. Kim, IEDM 2014

NIST Randomness Test Results

• Both schemes show similar level of randomness• The output data fail to pass the frequency and

cumulative sums tests

Test Pass/Fail1 Frequency Fail2 Block frequency Pass3 Cumulative Sums Fail4 Runs Pass5 Longest-Run-of-Ones Pass6 Rank Pass7 FFT Pass

8 Non-overlapping Template Matching

9 Serial Pass

10 Approximate Entropy Pass

# of segments: 55

Pass

13

Test Pass/Fail1 Frequency Fail2 Block frequency Pass3 Cumulative Sums Fail4 Runs Pass5 Longest-Run-of-Ones Pass6 Rank Pass7 FFT Pass

8 Non-overlapping Template Matching

9 Serial Pass

10 Approximate Entropy Pass

# of segments: 55

Pass

Unconditional reset scheme Conditional perturb scheme

• Simple single-parameter feedback control• The proposed techniques were implemented

in a real-time feedback loop

Real-Time Output Probability Tracking

Vref

Sense Amp.

Random number output

10 bit counter

10 bit counter

Adjust tPERTURB-

Ref. CLK (Sense amp

enable)

1 bit shift register

10 b

it di

gita

l co

mpa

rato

r

a

a/b < 49% or 49% < a/b < 51% or

a/b >51%

Adjust tPERTURB- while keeping VPERTURB+,

tPERTURB+, and VPERTURB- constant

Counts the number of 1's Multiply by 2 Compare

Counts the total number of bits

Bidirectionalpulse generator

b

Polarity selection circuit

Probability tracking schemeConditional perturb scheme

VMTJ

14W. Choi, Y. Lv, JP Wang, C. Kim, IEDM 2014

Measured Probability and Randomness- Real-Time Output Probability Tracking-

• Proposed conditional perturb and real-time probability tracking provides good randomness while improving reliability, speed, and power

46474849505152535455

7.57.67.77.87.9

88.18.28.38.48.5

1 57 113 169 225 281# of 1 Kbit segments

Initial locking period

Min. pulse width step: 50ps

VPERTURB+: +220mV, tPERTURB+: 8.0ns, VPERTURB-: -215mV

Prob

abili

ty (%

)-P

ertu

rb p

ulse

wid

th (n

s)

Test Pass/Fail1 Frequency2 Block frequency Pass3 Cumulative Sums4 Runs Pass5 Longest-Run-of-Ones Pass6 Rank Pass7 FFT Pass

8 Non-overlapping Template Matching

9 Serial Pass

10 Approximate Entropy Pass

Conditional perturb scheme, # of segments: 55

Pass

Raw data after probability tracking

Pass

Pass

15

MTJ based ADC

Slide 9

0102030405060708090

Prob

abili

ty (%

)

30 °C85 °C

0102030405060708090

370

390

410

430

450

470

490

510

530

550

VIN (mV)

Prob

abili

ty (%

)

128 bits / sample 2,048 bits / sample

30 °C85 °C

tPERTURB = 5ns tPERTURB = 5ns

370

390

410

430

450

470

490

510

530

550

VIN (mV)

• A short 5ns tPERTURB used for suppressing thermal activation switching

• Averaging more bits gives a smoother and more accurate probability curve (128 bits vs. 2,048 bits)

• Temperature sensitivity is acceptably low

W. Choi, Y. Lv, JP Wang, C. Kim, VLSI Tech. Symposium, 2015

Measured Worst Case DNL and INL

Slide 10

0

0.5

1

1.5

2

2.5

64 512 4096# of bits / sample

30 °C85 °C

0

0.5

1

1.5

2

2.5

64 512 4096# of bits / sample

Wor

st c

ase

INL

(LSB

)

30 °C85 °C

tPERTURB = 5ns1LSB = 4mV

tPERTURB = 5ns1LSB = 4mV

Wor

st c

ase

DN

L (L

SB)

Our target

• A 5-bit ADC resolution is assumed (i.e. 1LSB = 4mV)• DNL of 1 LSB can be achieved by averaging more

random bits (e.g. 2,048 bits)• INL cannot be improved by simply averaging more bits

One-time Digital Calibration for Improving INL

Slide 11

• Basic idea: Pre-calibrate MTJ transfer curve and store the inverse function in a look-up table to compensate for inherent non-linearity

VINMTJ-based

ADC1bit Accumul-ator + DAC

Moving Average Filter

Look Up TableDOUT

DOUT_CAL

VIN

Prob

abili

ty (%

)

MTJ

Counter + Register

DO

UT Linearizer

DOUT_CAL

J. Kim, et al., TCAS-I, 2010, J. Daniels, et al., VLSI Circuits Symposium, 2010.

Measured DNL and INL @ 85 C

Slide 12

-2

-1

0

1

2

DN

L (L

SB)

2,048 bits / sample @ 85ºC

Before digital calibration

DNLMAX = -0.75 / +0.73

-2

-1

0

12

INL

(LSB

)

Digital Out

INLMAX = -1.50 / +1.53

After digital calibration

DNLMAX = -1.00 / +0.82

Digital Out

INLMAX = -0.71 / +0.72

tPERTURB = 5ns tPERTURB = 5ns2,048 bits / sample @ 85ºC

3 7 11 15 19 23 27 31 35 393 7 11 15 19 23 27 31 35 39

0.81 LSB

• Target DNL / INL of 1 LSB can be met after one-time calibration

• ADC resolution limited to 5-bit due to narrow input voltage range

Proposed Input Range Enhancement Technique

Slide 13

VIN

Prob

abili

ty (%

)

2X Input range (2∙VIN,DYN)

Proposed scheme

VINPr

obab

ility

(%)

1X Input range (VIN,DYN)

VMTJ

MTJ

0V

VMTJ

MTJ

VOFFSET

Original scheme

VOFFSET = 0VVOFFSET = VIN,DYN

Implementation of Input Range Enhancement Technique

Slide 14

Volt. dividerfor 2M VOFFSETs

VOFFSETVREF

Sense Amp.

Bit stream of 0's and 1's

Counter

Bidirectionalpulse generator

CountRegister

DOUT

VIN

MTJ

Sample / hold circuit

Analog buffer

Input range enhancement technique

• A voltage divider and an analog buffer control the MTJ bottom node voltage

Measured DNL and INL @ 85 C

Slide 15

• Target DNL / INL of 1 LSB can be met after calibration • 8-bit ADC resolution with good linearity is achieved

2,048 bits / sample @ 85ºC

Before digital calibration

INLMAX = -1.52 / +1.55

After digital calibration

-2

-1

0

1

2

DN

L (L

SB)

DNLMAX = -1.00 / +1.00

tPERTURB = 5ns

Digital Out

-2

-1

0

1

2

INL

(LSB

)

DNLMAX = -1.00 / +1.00

tPERTURB = 5ns

INLMAX = -0.88 / +0.87

Digital Out

2,048 bits / sample@ 85ºC

0 28 56 84 112 140 168 196 224 252 0 28 56 84 112 140 168 196 224 252

0.68 LSB

ADC Performance Summary

Slide 16

Original MTJ-based ADC

+ Digital calibration

+ Digital calibration + Input range enhancement

DNLMAX (LSB)

0.74 1.32

1.00 0.76

1.00 0.84

Bits

5

5

8

0.75 1.53

1.00 0.72

1.00 0.88

Bits

5

5

8

30 ºC 85 ºC2,048 bits / sample

Input range

128mV(X1)

128mV(X1)

1024mV(X8)

DNLMAX (LSB)

INLMAX (LSB)

INLMAX (LSB)

• ADC resolution (=8 bit) was limited by the minimum voltage step (=1mV) of pulse generator

• Ideally, resolution could be as high as 14 bits

W. Choi, Y. Lv, JP Wang, C. Kim, VLSI Tech. Symposium, 2015

Summary• MTJ-based TRNG

– First demonstration of TRNG based on the random switching probability of MTJ

– Conditional perturb and real-time output probability tracking improved lifetime, speed, and power

• MTJ-based ADC– Digital calibration for improved linearity and input

range enhancement technique– 2,048 bits averaged to generate one ADC sample– Insensitive to temperature using a 5ns pulse width

Slide 17