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M.Tech (VLSI & Embedded systems) COURSE STRUCTURE Academic year 2013-14 M.Tech VLSI & ES 1st semester S.No Code Course Theory Practical Credits 1 MEP1 1401 Advanced optimization techniques 3+1* - 4 2 ECEP2 1401 Embedded system design 3+1* - 4 3 ECEP1 1405 VLSI technology & Design 3+1* - 4 Elective-I 4 ECEP1 1412 ECEP1 1404 ECEP2 1402 Analog & Digital IC design Digital design through VERILOG Embedded software design 3+1* - 4 Elective-II 5 ECEP2 1403 ECEP1 1410 ECEP1 1417 Advanced Microcontrollers & Processors DSP Processors & Architectures VLSI Signal processing 3+1* - 4 6 ECEP1 1209 HDL Programming laboratory - 3 2 7 GMRP 10206 Term-paper - - 2 Total 20 03 24

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M.Tech (VLSI & Embedded systems)

COURSE STRUCTURE

Academic year 2013-14

M.Tech VLSI & ES 1st semester

S.No Code Course Theory Practical Credits

1 MEP1 1401 Advanced optimization techniques 3+1* - 4

2 ECEP2 1401 Embedded system design 3+1* - 4

3 ECEP1 1405 VLSI technology & Design 3+1* - 4

Elective-I

4

ECEP1 1412

ECEP1 1404

ECEP2 1402

Analog & Digital IC design

Digital design through VERILOG

Embedded software design

3+1* - 4

Elective-II

5

ECEP2 1403

ECEP1 1410

ECEP1 1417

Advanced Microcontrollers & Processors

DSP Processors & Architectures

VLSI Signal processing

3+1* - 4

6 ECEP1 1209 HDL Programming laboratory - 3 2

7 GMRP 10206 Term-paper - - 2

Total 20 03 24

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M.Tech VLSI & ES I1st semester

S.No Code Course Theory Practical Credits

1 ECEP2 1404 Algorithms for VLSI design Automation

3+1* -4

2 ECEP1 1408 Embedded and Real time systems 3+1* - 4

3 CSEP1 1413 Soft computing techniques 3+1* - 4

Elective-III

4

ECEP2 1405

ECEP2 1406

ECEP2 1407

Design of fault tolerant system

Embedded networking

Low power VLSI design

3+1* - 4

Elective-IV

5

ECEP2 1408

ECEP2 1409

ECEP1 1416

CPLD and FPGA Architectures

& applications

Hardware software co design

System modeling & simulation

3+1* - 4

6 ECEP2 1210 Embedded systems laboratory - 3 2

7 GMRP 10202 Comprehensive Viva-voce - - 2

Total 20 03 24

M.Tech VLSI &ES III semester:S.No Code Course Theory Practical Credits

1 GMRP 20403 Internship - - 42 GMRP 22005 Project work - - -

M.Tech VLSI & ES IV semester S.No Code Course Theory Practical Credits

1 GMRP 22005 Project work - -- 20

*Tutorial

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: ADVANCED OPTIMIZATION TECHNIQUES Course code: MEP1 1401

L T P C 3 1 0 4

Course objectives:

This course is designed for first year M.Tech students. The course is intended to make the students understand the basic concepts and advanced concepts of optimization techniques.

The main objective of the course is to: Develop systematic approach to handle problems to design of electrical circuit etc; with a goal of

maximizing the profit and minimizing cost. Understand the various optimization techniques such as classified optimization, linear programming.

One dimensional minimization methods, unconstrained optimization techniques, constrained optimization techniques and dynamic programming.

Understand the necessary sufficient conditions for finding the solution of the problems in classical optimization.

Comprehend the numerical methods for finding approximate solution of complicated problems. Apply methods like north-west corner rule, least count method etc. to solve the transportation

problem.

Course outcomes: Design of mechanical systems and interdisciplinary engineering applications and business solutions

using suitable optimization technique. Apply numerical or iterative techniques in power systems for optimal power flow solutions. Optimize the parameters in control systems for desired steady state or transient response. Optimize the cost function in deciding economic factors of power systems. Design of electrical systems optimally using suitable techniques like univariate method, steepest

descent method etc.

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UNIT – I:Linear programming-Two-phase simplex method, Big-M method, duality, interpretation,applications.Assignment problem- Hungarian’s algorithm, Degeneracy, applications, unbalanced problems, traveling salesman problem.

UNIT – II:Classical optimization techniques-Single variable optimization with and without constraints, multi –variable optimization without constraints, multi – variable optimization with constraints – method of Lagrange multipliers, Kuhn-Tucker conditions.Numerical methods for optimization-Nelder Mead’s Simplex search method, Gradient of a function, Steepest descent method, Newton’s method, types of penalty methods for handling constraints.

UNIT –III:Genetic algorithm (GA) -Differences and similarities between conventional and evolutionary algorithms, working principle, reproduction, crossover, mutation, termination criteria, different reproduction and crossover operators, GA for constrained optimization, draw backs of GA.Genetic Programming (GP)-Principles of genetic programming, terminal sets, functional sets, differences between GA & GP, random population generation, solving differential equations using GP.

UNIT – IV:Multi-Objective GA-Pareto’s analysis, Non-dominated front, multi – objective GA, Nondominated sorted GA, convergence criterion, applications of multi-objective problems .Basic Problem solving using Genetic algorithm, Genetic Programming & Multi Objective GA and simple applications of optimization for engineering systems.Text books: 1. Optimal design – Jasbir Arora, Mc Graw Hill (International) Publishers2. Optimization for Engineering Design – Kalyanmoy Deb, PHI Publishers3. Engineering Optimization – S.S.Rao, New Age Publishers- 18 - Approved by BOS on 25th July 2009Reference Books: 1.Genetic algorithms in Search, Optimization, and Machine learning , D.E.Goldberg, Addison-Wesley Publishers2. Genetic Programming- Koza3. Multi objective Genetic algorithms - Kalyanmoy Deb, PHI Publishers

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: EMBEDDED SYSTEM DESIGN Course Code: ECEP2 1401

L T P C 3 1 0 4Course objectives:

Students undergoing this course are expected to:

Know embedded systems and applications with Current Technologies and Integration in system Design. Learn the Embedded system design flow, hardware design concepts and software development. Understand about Embedded board Input / output, board bus, board memory concepts. Understand various Interfacing techniques and device drivers. Learn complete embedded system life cycle, embedded operating systems and software utility tools.

Course Outcomes:

After undergoing the course, students will be able to

Design of Embedded system and they can implement in various real time applications. Analyze the complete embedded life cycle in designing of embedded systems (hardware and

software). Append various external devices to embedded systems. Identify the proper driver configuration for embedded system in various applications like automated

washing machines. Select suitable operating system for real time embedded systems based on application requirement.

Page 6: M.Tech (VLSI & Embedded systems) - Welcome to · PDF fileCPLD and FPGA Architectures ... SYLLABUS Course Title: EMBEDDED SYSTEM DESIGN Course Code: ... M. Tech (VLSI & Embedded systems)

UNIT – I IntroductionAn Embedded System-Definition, Examples, Current Technologies, Integration in system Design, Embedded system design flow, hardware design concepts, software development, processor in an embedded system and other hardware units, introduction to processor based embedded system design concepts.

UNIT – II Embedded HardwareEmbedded hardware building blocks, Embedded Processors – ISA architecture models, Internal processor design, processor performance, Board Memory – ROM, RAM, Auxiliary Memory, Memory Management of External Memory, Board Memory and performance. Embedded board Input / output – Serial versus Parallel I/O, interfacing the I/O components, I/O components and performance, Board buses – Bus arbitration and timing, Integrating the Bus with other board components, Bus performance.

UNIT – III Embedded Software Device drivers, Device Drivers for interrupt-Handling, Memory device drivers, On-board bus device drivers, Board I/O drivers, Explanation about above drivers with suitable examples. Embedded operating systems –Multitasking and process Management, Memory Management, I/O and file system management, OS standards example – POSIX, OS performance guidelines, Board support packages, Middleware and Application Software – Middle ware, Middleware examples, Application layer software examples.

UNIT – IV Embedded System Design, Development, Implementation and TestingEmbedded system design and development lifecycle model, creating an embedded system architecture, introduction to embedded software development process and tools- Host and Target machines, linking and locating software, Getting embedded software into the target system, issues in Hardware-Software design and co-design.Implementing the design-The main software utility tool, CAD and the hardware, Translation tools, Debugging tools, testing on host machine, simulators, Laboratory tools, System Boot-Up.

Text Books: 1. Embedded Systems Architecture: A Comprehensive Guide for Engineers and Programmers,-Tammy

Noergaard, Elsevier(Singapore) Pte.Ltd. Publications, 2005.

Reference Books: 1. Embedded system Design: A Unified Hardware/Software Introduction-Frank Vahid, Tony D. Givargis, John Wily & Sons Inc.2002.2. Embedded System Design- Peter Marwedel, Science Publishers, 2007.3. Embedded System Design, -Arnold S Burger, CMP.booksusa 2002.4. Embedded Systems: Architecture, Programming and Design-Rajkamal,, TMH Publications, Second Edition, 2008.

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: VLSI TECHNOLOGY & DESIGN Course Code: ECEP1 1405

L T P C 3 1 0 4Course objectives Students undergoing this course are expected to:

Know about the IC fabrication process and technology involved in the production process Understand the concepts of Layout design, Floor planning and Routing. Comprehend the electrical properties of MOS devices and the relation between physical and electrical

parameters of MOS device. Know about circuit characterization and performance estimation. Understand and to design of Logic Gates using the traditional and alternative logics. Analyze the combinational networks and Sequential Networks.

Course outcomes

After undergoing this course, students will be able to:

Identify the issues related to the IC Fabrication Process. Explore the design of better devices with IC technology Analyze the electrical properties of MOSFET Analyze parasitics and routings of ICS Perform circuit characterization and performance estimation. Apply the concepts of Logic Gates, Combinational and Sequential networks to design the better. Draw better layouts and Optimized floor planning and Routing.

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UNIT – I Review of Microelectronics and introduction to MOS technologies: (MOS, CMOS, Bi CMOS) Technology trends and projections. MOS Fabrication Processes.Basic Electrical Properties Of MOS, CMOS & BICMOS Circuits: Ids-Vds relationships, Threshold voltage Vt, Gm, Gds and Wo, Pass Transistor, MOS,CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuit model, Latch-up in CMOS circuits.

UNIT – IICIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION Resistance estimation - Capacitance estimation - Inductance - Switching characteristics - Transistorsizing - Power dissipation and design margining - Charge sharing - Scaling. LOGIC GATES: Static complementary gates, switch logic-pass transistor and transmission gate logic, Alternative gate circuits.

UNIT – IIICOMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network delay, interconnect design, power optimization, Switch logic networks, Gate and Network testing. SEQUENTIAL SYSTEMS: Memory cells and Arrays, clocking disciplines, Design, power optimization, Design validation and testing.

UNIT – IV LAYOUT DESIGN AND TOOLS: Stick Diagrams, Scalable Design rules, Layout Design tools. FLOOR PLANNING & ROUTING: Floor Planning concepts – Shape functions and Floorplan sizing – Types of Local Routing problems – Area routing – Channel routing – Global routing – Algorithms for Global Routing

Text Books: 1. Essentials of VLSI Circuits and Systems, K. Eshraghian et . al PHI of India Ltd.,2005 2. Modern VLSI Design, 3rd Edition, Wayne Wolf, Pearson Education, fifth Indian Reprint, 2005.

Reference books: 1. Principals of CMOS Design – N.H.E Weste, K.Eshraghian, Adison Wesley, 2nd Edition. 2. Introduction to VLSI Design – Fabricius, MGH International Edition, 1990. 3. CMOS Circuit Design, Layout and Simulation – Baker, Li Boyce, PHI, 2004. 3 4. Hill- D.- D. Shugard J. Fishburn and K. Keutzer, “Algorithms and Techniques for VLSI Layout Synthesis”, Kluwer Academic Publishers, 1989.

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: ANALOG AND DIGITAL IC DESIGN (Elective-I) Course Code: ECEP1 1412

L T P C 3 1 0 4Course objectives: Students undergoing this course are expected to:

Understand the fundamental analog IC blocks

Understand the basic analog IC blocks like mirrors, references , basic amplifiers and opamps Understand the PLL and switched capacitor circuits by using MOSFETS Learn VHDL modeling of combinational and sequential circuits Learn the internal circuit details of different varieties of ADC and DAC

Course outcomes

At the end of the course, the students can be able to :

Design and implement the fundamental analog IC blocks

Demonstrate the internal circuits and topologies of Opamp

Analyze the PLL and switched capacitors Demonstrate the VHDL models for combinational and sequential circuits Draw and explain the internal structures of ADC and DAC

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UNIT-ICURRENT MIRRORS AND SINGLE STAGE AMPLIFIERS: Simple COMS, BJT current mirror, Cascode, Wilson and Widlar current mirrors. Common Source amplifier source follower, common gate amplifierOPERATIONAL AMPLIFIERS: General considerations one – state op-amps, two stage opamps-gains boosting stage- comparison I/P range limitations slew rate.PHASED LOCKED LOOP DESIGN: PLL concepts- The phase locked loop in the locked condition Integrated circuit PLLs – phase Detector- Voltage controlled oscillator case study.UNIT -IICOMPORATORS: Using an op-amp for a comparator-charge injection error- latched Comparator SWITHCHED CAPACITORS CIRCUITS: Basic Building blocks op-amps capacitors switches –non-over lapping clocks-Basic operations and analysis-resistor equivalence of la switched capacitor- parasitic sensitive integrator parasitic insensitive integrators signal flow graph analysis-First order filters- switch sharing fully differential filters.UNIT-IIICOMBINATIONAL IC DESIGN BY USING VERILOG: VERILOG modeling for decoders, encoders, multiplexers, adders and subtractors.SEQUENCIAL IC DESIGN BY USING VHD: VERILOG modeling for larches, flip flops, counters, shift registers, FSMs.LOGIC FAMILIES & CHARACTERISTICS: COMS, TTL, ECL, logic families COMS / TTL- interfacing and comparison of logic families.UNIT-IVDIGITAL INTEGRADED SYSTEM BUILDING BLOCKS: Multiplexers, decoders, barrel shifters,counters and digital single bit adders.NYQUIST RATE D/A CONVERTERS: Decoder based converter resistor storing converters folded resistor string converter – Binary scale converters – Binary weighted resistor converters – Reduced resistance ratio ladders – R-2R based converters – Thermometer code current mode D/A converters. NYQUIST RATE A/D CONVERTERS: Integrating converters – successive approximation converters. DAC based successive approximation – flash converters time interleaved A/D converters.Text Books: 1. Analog Integrated circuit Design - David A Johns, Ken Martin, John Wiley & Sons.2. Design of Analog CMOS Integrated Circuits-Behzad Razavi, TMH3. Digital Integrated Circuit Design - Ken Martin, Oxford University 20004. Digital Design Principles & Practices - John F Wakerly, Pearson Education & Xilinx Design Series, 3rd Ed.(2002)

Reference Books: 1., Digital Integrated Circuit Design- Ken Martin Oxford University, 2000.2. “Digital Design Principles & Practices”- John F Wakerly, Pearson Education &

Xilinx Design Series, 3rd Ed. (2002)3. “Verylog HDL-A Guide to Digital Design and Synthesis- Samir Palnitkar, Prentice Hall India(2002)

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: DIGITAL DESIGN THROUGH VERILOG (Elective-I) Course Code: ECEP1 1404

L T P C 3 1 0 4

Course Objectives:

Students undergoing this course are expected to:

Learn the design and implement of the fundamental digital logic circuits using verilog hardware description language.

learn the design issues of system on chip.

understand the system level design and related concepts.

have awareness on FPGA and CPLD architectures

implement digital systems on FPGA and CPLD architectures.

Course Outcomes:

After undergoing the course, students will be able to

Design and implement the fundamental digital logic circuits using verilog HDL.

Perform system level design.

Implement design rule checks and timing parameters.

Demonstrate the architectural details of FPGAs and CPLDs.

Perform Mini projects on FPGA and CPLD board.

UNIT IINTRODUCTION TO VERILOG : Verilog as HDL, Levels of Design Description, Concurrency, Simulationand Synthesis, Functional Verification, System Tasks, Programming Language Interface (PLI), Module,Simulation and Synthesis Tools, Test Benches.LANGUAGE CONSTRUCTS AND CONVENTIONS : Introduction, Keywords, Identifiers, White SpaceCharacters, Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors,Parameters, Memory, Operators, System Tasks, Exercises.GATE LEVEL MODELING : Introduction, AND Gate Primitive, Module Structure, Other Gate Primitives,Illustrative Examples, Tri-State Gates, Array of Instances of Primitives, Additional Examples, Design of Flipflops with Gate Primitives, Delays, Strengths and Contention Resolution, Net Types, Design of BasicCircuits, Exercises.

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UNIT IIBEHAVIORAL MODELING : Introduction, Operations and Assignments, Functional Bifurcation,InitialConstruct, Always Construct, Examples, Assignments with Delays, Wait construct, Multiple Always Blocks,Designs at Behavioral Level, Blocking and Non blocking Assignments, Thec ase statement, Simulation Flow. iƒ and iƒ-else constructs, assign-deassign construct, repeat construct, for loop, the disable construct, while loop, forever loop, parallel blocks, force-release construct, Event.

MODELING AT DATA FLOW LEVEL : Introduction, Continuous Assignment Structures, Delays andContinuous Assignments, Assignment to Vectors, Operators.

SWITCH LEVEL MODELING.Introduction, Basic Transistor Switches, CMOS Switch, Bi-directional Gates, Time Delays with SwitchPrimitives, Instantiations with Strengths and Delays, Strength Contention with Trireg Nets, Exercises.

UNIT IIISYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES : Introduction, Parameters, Path Delays,Module Parameters, System Tasks and Functions, File-Based Tasks and Functions, Compiler Directives,Hierarchical Access, General Observations, Exercises,

FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES : Introduction, Function, Tasks, User-Defined Primitives (UDP), FSM Design (Moore and Mealy Machines)

DIGITAL DESIGN WITH SM CHARTS : State Machine Charts, Derivation of SM Charts, Realization of SM Charts, Implementation of the Dice Game, Alternative realizations for SM Charts using Microprogramming, Linked State Machines.

UNIT IVDESIGNING WITH PROGRAMMABLE GATE ARRAYS AND COMPLEX PROGRAMMABLE LOGIC DEVICES : Xilinx 3000 Series FPGAs, Designing with FPGAs, Using a One-Hot State Assignment, Altera Complex Programmable Logic Devices (CPLDs), Altera FLEX 10K Series CPLDs.

VERILOG MODELS : Static RAM Memory, A simplified 486 Bus Model, Interfacing Memory to aMicroprocessor Bus, UART Design, Design of Microcontroller CPU.

Text Books: 1. Design through Verilog HDL – T.R. Padmanabhan and B. Bala Tripura Sundari, WSE, 2004 IEEEP press.2. A Verilog Primier – J. Bhaskar, BSP, 2003.

Reference Books: 1. Fundamentals of Logic Design with Verilog – Stephen. Brown and Zvonko Vranesic, TMH, 2005.2. Digital Systems Design using VHDL – Charles H Roth, Jr. Thomson Publications, 2004.3. Advanced Digital Design with Verilog HDL – Michael D. Ciletti, PHI, 2005.

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: EMBEDDED SOFTWARE DESIGN (Elective- I) Course Code: ECEP2 1402

L T P C 3 1 0 4

Course objectives:

Students undergoing this course are expected to:

Learn about embedded systems Design tool chain. Understand the Current Technologies for Execution environments, Memory Organization, System Startup,

Special software techniques and Hardware software duality. Understand the Real time back ground debug mode, JTAG, ICE etc.. Analyze the Complete Run time issues like porting the kernel, Bugs, libraries etc.. Understand various methods to test the embedded system.

Course outcomes:

At the end of the course, student can able to

Design and analyze an embedded system. Identify the various steps involved in embedded Software development. Analyze the various intermediate results during debug process to re assemble the system

components based on requirement. Get exposure on current software porting technologies and problems. Test the software for an embedded system to justify the system design.

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UNIT-IEmbedded Design Life Cycle: Introduction, Product Specification, Hardware/software partitioning, Iteration and Implementation, Detailed hardware and software design, Hardware/Software integration, Product Testing and Release, Maintaining and upgrading existing products. Selection Process: Packaging the Silicon, Adequate Performance, RTOS Availability, Tool chain Availability, Other issues in the Selection process.

UNIT –II Partitioning decision: Hardware/Software Duality, Hardware Trends, ASICs and Revision Costs.Development Environment: The Execution Environment, Memory Organization, System Startup. Special Software Techniques: Manipulating the Hardware, Interrupts and Interrupt service Routines (ISRs), Watchdog Times, Flash Memory, Design Methodology. Basic Tool Set: Host – Based Debugging, Remote Debuggers and Debug Kernels, ROM Emulator, Logic Analyzer.

UNIT- III BDM: Background Debug Mode, Joint Test Action Group (JTAG) and Nexus. ICE – Integrated Solution: Bullet Proof Run Control, Real time track, Hardware Break points, Overlay memory, Timing Constrains, Usage Issue, Setting the Trigger. Testing: Why Test? When to Test? Which Test? When to Stop? Choosing Test cases, Testing Embedded Software, Performance Testing Maintenance and Testing, The Future.

UNIT- IVWriting Software for Embedded Systems: The compilation Process, Native Versus Cross-Compilers, Runtime Libraries, Writing a Library, Using alternative Libraries, using a standard Library, Porting Kernels, C extensions for Embedded Systems, Downloading. Emulation and debugging techniques; Buffering and Other Data Structures: What is a buffer? Linear Buffers, Directional Buffers, Double Buffering, Buffer Exchange, Linked Lists, FIFOs, Circular Buffers, Buffer Under run and Overrun, Allocating Buffer Memory, Memory Leakage. Memory and Performance Trade-offs.

Text books: 1. Microprocessors and Microcontrollers-Bary B Brey, PHI 2. Embedded Systems-An introduction to processes, tools and techniques - Arnold Berger, Elsevier,2010

New Delhi

Reference books: 1. Embedded system Design: A Unified Hardware/Software Introduction-Frank Vahid, Tony D. Givargis, John Wily & Sons Inc.2002.2. Embedded Systems: Architecture, Programming and Design-Rajkamal,, TMH Publications,Second Edition, 2008.

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M. Tech (VLSI & Embedded systems)

1st semesterA Y -2013-14

SYLLABUS

Course Title: ADVANCED MICROCONTROLLERS & PROCESSORS Course Code: ECEP2 1403 (Elective-II)

L T P C 3 1 0 4

Course objectives

The course content enables students to:

Understand basic knowledge of Various Microcontrollers and Processors by understanding the architecture of General , Atmel, ARM & PIC Microcontrollers family

understand how a microcontroller is organized learn assembly language programming and interfacing know AVR hardware design issues. understand embedded ARM applications

Course outcomes

At the end of the course, students are able to:

Design the home appliances and toys using Microcontroller chips. Design computers like desktops, laptops using various processors. Design the high speed communication circuits using serial bus connection. Apply commercial CPU(s) as realistic vehicles to demonstrate these concepts by introducing

students to CPU instructions and internal register structures. Analyze full internal workings of a typical simple CPU including the utilization of the various

hardware resources during the execution of instructions.

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UNIT-1: General MicrocontrollersIntroduction to the 8051& 8052 microcontrollers, features, architecture, memory organization, addressing modes, instruction set, assembly programming, software development tools, parallel I/O ports, interrupts, timers/counters, serial communication, data and control transfer operations, serial data transmissions, programming and interfacing using 8051.Atmel Microcontrollers: Introduction to Atmel microcontrollers (89CXX and 89C20XX), Architectural overview of Atmel 89C51 and Atmel 89C2051,pin descriptions of Atmel microcontrollers, using flash memory devices Atmel 89XX and Atmel 89C20XX, Applications of MCS-51 and Atmel 89C51 AND 89C2051 microcontrollers.UNIT-II: PIC MicrocontrollersAn introduction to PIC microcontrollers, PIC 8 Series and PIC 16 series microcontrollers and PIC family of microcontrollers (16C6X/7X,16F84A, 12F50X and 16F8XX), architecture, instruction set , programming using assembly and c languages of the PIC microcontrollers, interfacing PIC Microcontroller to other devices, applications of PIC microcontrollers.AVR Microcontrollers: Introduction to AVR microcontroller, AVR RISC microcontroller architecture, AVR instructions set, AVR hardware design issues, hardware and software interfacing with AVR, communications links for the AVR, AVR system development tools.UNIT-III: AVR Microcontrollers FamilyIntroduction to AVR family of microcontrollers, Introduction to ATMEGA 8 and AT90S1200 microcontrollers, architecture and pin diagram of the ATMEGA 8 and AT90S1200 microcontrollers, programming of ATMEGA 8 using c and assembly languages, interfacing of ATMEGA8 to other modules.ARM Processors: An introduction to ARM processors, ARM architecture, ARM Instructions set, thumb instructions set, design issues, c and assembly programming in ARM, architectural support for system development, optimized primitives, exception and interrupt handling, caches memory protecting units, memory management units, embedded operating system using in the ARMUNIT-IV: ARM Processor CoresIntroduction to ARM processors cores, embedded ARM applications, architecture, instruction set, programming using assembly and c languages of ARM 7TDMI and ARM9TDMI processors, interfacing ARM 7TDMI and ARM9TDMI processors to other devices, applications of ARM 7TDMI and ARM9TDMI processors.Embedded processors: Introduction to embedded processors, ISA architecture models, internal processor design, processor performance, configurability features, processor architecture, instruction set, programming of embedded processors (power PC processor, Micro blaze processor and Nios processor) and interfacing to other modules.Text Books:

1. Microcontrollers-Theory and Applications-Ajay V Deshmukh-TMH 2005 Publication.2. Programming and customising the AVR microcontroller- Dhananjay V Gadre-TMH 2000

Publications.3. ARM system – on chip Architecture- Stephen B Furber-Pearson Publishers second edition.4. Embedded systems architecture- Tammy Noergaard-Elsevier Publications.

Reference Books:

1.8051 Microcontroller-Hardware, Software and applications- V.Udayashankara, M.S.Mallikarjuna Swamy-TMH Publications.

2. PIC microcontrollers- lucio Bi Jasio-Newnes Publishers.3. ARM system – on chip Architecture - Stephen B Furber-Pearson Publishers.

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M. Tech (VLSI & Embedded systems)

1st semesterA Y -2013-14

SYLLABUS

Course Title: DSP PROCESSORS AND ARCHITECTURES Course Code: ECEP1 1410 (Elective-II)

L T P C 3 1 0 4

Course objectives

Students undergoing this course are expected to:

understand the basic DFT, FFT and rate conversion algorithms.

understand the number format, dynamic range and sources of errors in DSP systems.

learn about TMS programmable DSPs and their programming capabilities.

Understand basic DSP algorithms on TMS processors.

Know FFT algorithms on TMS320C54XX DSP device

Course outcomes

After undergoing the course, students will be able to

Apply DFT and FFT algorithms for DSP application

Apply the number format, dynamic range and various sources of errors in DSP system

Implement application programs on a DSP processor

Implement various DSP algorithms on TMS processors. Implement FFT algorithms on TMS320C54XX DSP device

UNIT IINTRODUCTION TO DIGITAL SIGNAL PROCESING: Introduction, A Digital signal-processing system, The sampling process, Discrete time sequences. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), linear time invariant systems, Digital filters, Decimation and interpolation, Analysis and Design tool for DSP Systems MATLAB, DSP using MATLAB.

COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS: Number formats for signals and coefficients in DSP systems, Dynamic Range and Precision, Sources of error in DSP implementations, A/D Conversion errors, DSP Computational errors, D/A Conversion Errors, Compensating filter.

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UNIT IIARCHITECTURES FOR PROGRAMMABLE DSP DEVICES : Basic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for External interfacing.

EXECUTION CONTROL AND PIPELINING: Hardware looping, Interrupts, Stacks, Relative Branch support, Pipelining and Performance, Pipeline Depth, Interlocking, Branching effects, Interrupt effects, Pipeline Programming models.

UNIT IIIPROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Commercial Digital signal-processing Devices, Data Addressing modes of TMS320C54XX DSPs, Data Addressing modes of TMS320C54XX Processors, Memory space of TMS320C54XX Processors, Program Control, TMS320C54XX instructions and Programming, On-Chip Peripherals, Interrupts of TMS320C54XX processors, Pipeline Operation ofTMS320C54XX Processors.

IMPLEMENTATIONS OF BASIC DSP ALGORITHMS: The Q-notation, FIR Filters, IIR Filters, Interpolation Filters, Decimation Filters, PID Controller, Adaptive Filters, 2-D Signal Processing.

UNIT IVIMPLEMENTATION OF FFT ALGORITHMS: An FFT Algorithm for DFT Computation, A Butterfly Computation, Overflow and scaling, Bit-Reversed index generation, An 8-Point FFT implementation on the TMS320C54XX, Computation of the signal spectrum.

INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSPDEVICES: Memory space organization, External bus interfacing signals, Memory interface, Parallel I/Ointerface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA). A Multichannel buffered serial port (McBSP), McBSP Programming, a CODEC interface circuit, CODEC programming, A CODEC-DSP interface example.

Text books: 1. Digital Signal Processing – Avtar Singh and S. Srinivasan, Thomson Publications, 2004.2. DSP Processor Fundamentals, Architectures & Features – Lapsley et al. S. Chand & Co, 2000.

Reference Books: 1. Digital Signal Processors, Architecture, Programming and Applications – B. Venkata Ramani

and M. Bhaskar, TMH, 2004.2. Digital Signal Processing – Jonatham Stein, John Wiley, 2005.

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: VLSI SIGNAL PROCESSING (Elective-II) Course Code: ECEP1 1417

L T P C 3 1 0 4

Course objectives:

Students undergoing this course are expected to:

Understand the pipelining and parallel processing techniques to the VLSI systems Analyse the retiming, unfolding & folding concepts for register minimization Understand the systolic architectures Understand the various arithmetic circuits for signal processing Understand and apply the fast convolution algorithms for signal processing applications

Course outcomes:

After undergoing the course, students will be able to

Design parallel processors in VLSI systems Implement the register minimization using the retiming, unfolding & folding concepts. Design systolic architecture using canonical mapping and generalized mapping Design parallel bit circuits Implement signal processing applications like FFT etc

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UNIT- IIntroduction to the VLSI Signal Processing Typical Signal Processing Algorithms, Overview of VLSI Architectures, Representations of DSP Algorithms.

Pipelining and parallel processing

Introduction, Data Flow Graph Representation, Loop bound and Iteration Bound, Algorithms for computing Iteration bound, Pipelining of FIR filters, Parallel Processing,

UNIT- IIRetiming

Definitions and Properties, Solving systems of inequalities, Retiming techniques.

Unfolding and Folding Unfolding Algorithm, Properties of unfolding, Critical Path, Unfolding and Retiming, Folding Transformation, Register Minimization techniques. Register Minimization in folded architectures.

UNIT- IIISystolic Architecture DesignMatrix Operations and 2D Systolic Array Design, Parallel Algorithm Expressions, Canonical Mapping Methodology, Generalized Mapping.

Arithmetic components

Parallel bit circuits: Carry-Look ahead addition, Prefix Computations, Carry-Save Addition, Multiplication.

UNIT- IVFast Convolution

Introduction, Cook-Toom algorithm, Winogard algorithm, Iterated Convolution and Cyclic convolution.

Programmable Digital Signal Processors

Important Features, DSP Processors for Mobile and Wireless Communications, Processors for Multidimensional Signal Processing.

Text Books:

1. K. K. Parhi, “VLSI Digital Signal Processing Systems, Design and Implementation”, John Wiley, 1999.

Reference Books:

1. S.Y.Kung, “VLSI Array Processors”, Prentice-Hall, 1988

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M. Tech (VLSI & Embedded systems)1st semesterA Y -2013-14

SYLLABUS

Course Title: HDL PROGRAMMING LABORATORY Course Code: ECEP1 1209

L T P C 0 0 3 2

Course Objectives:

Students undergoing this course are expected to:

Learn the design and implementation of fundamental digital logic circuits using verilog hardware description language.

learn functionality of designed circuits using functional simulator.

understand the timing and critical issues during simulation.

synthesize the design.

learn place and route techniques of different FPGA vendors.

Course Outcomes:

After undergoing the course, students will be able to

Design and implement the fundamental digital logic circuits using verilog HDL.

Perform system level design.

Implement design rule checks and timing parameters.

know the resources consumed by the design on FPGA.

Optimize the Interconnections during place and route.

1. Digital Circuits Design (Sub-System Level) Description using Verilog and VHDL.

2. Verification of the Functionality of Designed Circuits using functional Simulator.

3. Timing simulation for critical path time calculation.

4. Synthesis Reports of top-order designed Digital circuits.

5. Place and Route techniques for major FPGA vendors such as Xilinx, Altera and Actel etc.

6. Implementation of Designed Digital Circuits using FPGA and CPLD devices

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M. Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: Algorithms for VLSI design Automation Course Code: ECEP2 1404

L T P C 3 1 0 4

Course objectives:

Students undergoing this course are expected to

Learn design methodologies for VLSI Understand Tractable and Intractable methods for VLSI Design. Know Backtracking, Branch and Bound Methods for digital design Understand Working of Genetic Algorithms for VLSI design Learn the various techniques of routing and placement understand the logic synthesis and verification for design of digital circuits Understand physical design automation of FPGA’s and MCM’s.

Course outcomes

After undergoing the course, students will be able to

Design VLSI digital circuits Implement tractable and intractable methods for VLSI design Apply Backtracking, Branch and Bound Methods for combinational optimization Apply Genetic Algorithm for combinational optimization Apply the concept of routing and placement for layout compaction Implement logic synthesis and verification for design of digital circuits Analyze the physical design flow of FPGA’s and MCM’s.

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UNIT I

PRELIMINARIES: Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph Theory, Computational Complexity, Tractable and Intractable Problems.GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION: Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu search, Genetic Algorithms.

UNIT II

Layout Compaction, Placement, Floorplanning and Routing Problems, Concepts and Algorithms.MODELLING AND SIMULATION: Gate Level Modelling and Simulation, Switch level modeling and simulation

UNIT III

LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology, Binary –Decision diagram, Two – Level Logic Synthesis.HIGH LEVEL SYNTHESIS: Hardware Models, Internal representation of the input algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High –level Transformations.

UNIT IVPHYSICAL DESIGN AUTOMATION OF FPGA’S: FPGA technologies, Physical Design cycle for FPGA’s partitioning and Routing for segmented and staggered models.PHYSICAL DESIGN AUTOMATION OF MCM’S: MCM technologies, MCM physical design cycle, Partitioning, Placement – Chip array based and full custom approaches, Routing – Maze routing, Multiple stage routing, Topologic routing, Integrated Pin – Distribution and routing, routing and programmable MCM’s.

Text Books:

1. Algorithms for VLSI Design Automation- S.H.Gerez, WILEY student edition, John Wiley & Sons (Asia) Pvt. Ltd. 1999.2. Algorithms for VLSI Physical Design Automation- Naveed Sherwani, 3rd edition Springer International

Edition, 2005

Reference Books:

1. Computer Aided Logical Design with Emphasis on VLSI – Hill & Peterson, Wiley, 1993.2. Modern VLSI Design: Systems on silicon – Wavne Wolf, Pearson Education Asia, 2nd Edition, 1998.

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M. Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: EMBEDDED AND REAL TIME SYSTEMS Course Code: ECEP1 1408

L T P C 3 1 0 4

Course objectives:

This course enables the students to

Design and development of an embedded system, including hardware and embedded software development.

Understand the basics of an embedded system. Program an embedded system with Real-Time aspects. Design, implement and test a real time embedded system. Learn the difference between real-time and standard operating systems. Know the significance of a real time OS in an embedded System.

Course outcomes

After undergoing this course, students will be able to:

handle many issues involved with embedded systems. Understand Real-Time Operating System concepts. Program using system calls in ID Environment. Program an embedded system with tasks and executive. Understand the tools to build an embedded real-time system. Design and implement a small embedded system Present design information effectively in the forms of technical reports and oral presentations

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UNIT I: INTRODUCTIONEmbedded systems over view, design challenges, processor technology, Design technology, Trade-offs. Single purpose processors, RT-level combinational logic, sequential logic (RTlevel),custom purpose processor design(RT -level), optimizing custom single purposeprocessors. General Purpose Processors - Basic architecture, operations, programmer’s view, development environment, Application specific Instruction –Set processors (ASIPs)-Micro controllers and Digital signal processsors.

UNIT II: STATE MACHINE AND CONCURRENT PROCESS MODELS AND COMMUNICATION PROCESSESIntroduction, models Vs Languages, finite state machines with data path model (FSMD), program state machine model(PSM, concurrent process model, concurrent processes, communication among processes, synchronization among processes, Implementation, data flow model, real-time systems. Communication Processes - Need for communication interfaces, RS232/UART, RS422/RS485, USB, Infrared, IEEE1394 Firewire, Ethernet, IEEE 802.11, Blue tooth.

UNIT III: INTRODUCTION TO REAL TIME SYSTEMS AND PROGRAMMING LANGUAGES AND TOOLS

Introduction – Issues in Real Time Computing, Structure of a Real Time System, Task classes, Performance Measures for Real Time Systems, Estimating Program Run Times. Task Assignment and Scheduling –Classical uniprocessor scheduling algorithms, Uniprocessor scheduling of IRIS tasks, Task assignment, Mode changes, and Fault Tolerant Scheduling.Programming Languages and Tools – Desired language characteristics, Data typing, Control structures, Facilitating Hierarchical Decomposition, Packages, Run – time (Exception) Error handling, Overloading and Generics, Multitasking, Low level programming, Task Scheduling, Timing Specifications, Programming Environments, Run – time support.UNIT IV: REAL TIME DATABASES AND DESIGN TECHNOLOGYReal time Databases – Basic Definition, Real time Vs General Purpose Databases, Main Memory Databases, Transaction priorities, Transaction Aborts, Concurrency control issues, Disk Scheduling Algorithms, Two –phase Approach to improve Predictability, Maintaining Serialization Consistency, and Databases for Hard Real Time Systems. Automation, Synthesis, parallel evolution of compilation and synthesis, Logic synthesis, RT synthesis, Behavioral Synthesis, Systems Synthesis and Hard ware/Software Co-Design, Verification, Hardware/Software co-simulation, Reuse of intellectual property codes.

Text Books:

1.Embedded System Design-A Unified Hardware/Software Introduction- Frank Vahid, Tony .Givargis, John Wiley & Sons, Inc.2002.2.Embedded/Real Time Systems- KVKK prased, Dreamtech press-2005.3. Krishna. C. M, Kang. G, Shin, “Real Time Systems”, McGraw Hill, 2003.

Reference Books: 1. Herma. K, “Real Time Systems – Design for distributed Embedded Applications”, Kluwer Academic, 2002.2. Charles Crowley, “Operating Systems-A Design Oriented approach” McGraw Hill 2004.3. Raymond J.A.Bhur, Donald L.Bailey, “An Introduction to Real Time Systems”, PHI 2002.

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M. Tech (VLSI & Embedded systems)

2nd semesterA Y -2013-14

SYLLABUS

Course Title: SOFT COMPUTING TECHNIQUES Course Code: CSEP1 1413

L T P C 3 1 0 4

Course objectives: This course is designed for first year M.Tech students. The course is intended to make the students understand concepts about Soft Computing and its application in various field.

The main objective of the course is to

know Soft Computing basics and its branches understand the basic implementation details on Artificial Neural Networks understand fuzzy logic and it application in ANN. introduction of Support vector machine and its application elaborate discussion on applications of Soft Computing

Course outcomes

After undergoing this course, students will be able to

differentiate between Soft Computing and Hard computing. understand its branches Artificial Neural Networks, Fuzzy Logic, and Support Vector machine understand various applications of soft computing. judge less complexity by using various soft computing methods

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UNIT I:Basic elements of soft Computing – Introduction to soft computing, Fuzzy logic, Neural Networks and Evolutionary Computing, Approximations of Multivariate functions, Non – linear Error surface and optimization. Artificial Neural Networks- Introduction, Basic models of ANN, important terminologies, Basic Learning Laws, Supervised Learning Networks, Perceptron Networks, Adaptive Linear Neuron, Backpropagation Network.Radial basis function network and Hopfield Networks.

UNIT II :Unsupervised Learning Network- Introduction, Fixed Weight Competitive Nets, Maxnet, Hamming Network, Kohonen Self-Organizing Feature Maps, Learning Vector Quantization, Counter Propagation Networks, Adaptive Resonance Theory Networks. Special Networks-Introduction to various networks.

Introduction to Classical Sets and Fuzzy Sets- Crisp Sets and Fuzzy Sets- operations. Classical Relations and Fuzzy Relations- Cardinality, Properties and composition. Tolerance and equivalence relations. Membership functions- Features, Fuzzification, membership value assignments, Defuzzification.

UNIT-III :Fuzzy Logic-Classical& Fuzzy logic, Operations, Boolean Logic, Multivalued Logics, Fuzzy Rule Base and Approximate Reasoning ,Fuzzy Decision making ,Fuzzy Logic Control Systems.Genetic Algorithm- Introduction, Traditional Optimization and search techniques, Search space, Operators: Encoding, Selection, Crossover and Mutation. Stopping Condition of GA.

UNIT IV:Support Vector Machine -Introduction, optimal hyper plane for linearly separable pattern, linear classifier, nonlinear classifier problem, optimal plane for non-separable pattern, example XOR problem, support vector machine for non-linear regression., summary and discussion.Applications of Soft Computing - A fusion Approach of Multispectral Images with SAR Image for flood area analysis, Optimization of TSP using GA Approach and GA-Fuzzy system for Control of flexible Robots.

Text Books: 1. Principles of Soft Computing- S N Sivanandam, S N Deepa, Wiley India, 20112. V. Kecman, “Learning and Soft computing”, Pearson Education, India

Reference Books: 1.Soft Computing and Intelligent System Design -Fakhreddine O Karray, Clarence D Silva,. Pearson Edition, 2004. 2.Introduction to Fuzzy Systems, Guanrong Chen, Trung Tat Pham, Chapman & Hall/CRC, 2009. 3 .S. Haykins,“Neural networks: a comprehensive foundation”. Pearson Education, India..

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M.Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: DESIGN OF FAULT TOLERANT SYSTEMS (Elective-III) Course Code: ECEP2 1405

L T P C 3 1 0 4

Course objectives :

This course enables the students to

Learn the concepts of faults and failure for a digital system. know about different types of redundancy. Learn about self-checking circuits. Know the testing of combinational circuits. Know the testing of sequential circuits. Learn about automatic testing systems.

Course outcomes:

After undergoing this course, students will be able to

Design a fault tolerant digital system Minimize the error for a given system. Design self-checking circuits. design and test combinational circuits. design and test a sequential circuits. Design an automatic testing system using BIST for basic sequential circuits

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UNIT IBASIC CONCEPTS: Reliability concepts, Failure & Faults, Reliability and failure rate, Relation between reliability and Meantime between failure, Maintainability and Availability, Reliability of series, Parallel and Parallel-Series combinational circuits.’FAULT TOLERANT DESIGN: Basic concepts – Static, dynamic, hybrid, Triple Modular Redundant System, Self purging redundancy, Siftout redundancy (SMR), SMR Configuration, Use of error correcting code, Time redundancy and software redundancy.

UNIT IISELF CHECKING CIRCUITS: Basic concepts of Self checking circuits, Design of Totally SelfChecking checker, Checkers using m out of n codes, Berger code, Low cost residue code.

FAIL SAFE DESIGN: Strongly fault secure circuits, fail-safe design of sequential circuits using partition theory and Berger code, totally self-checking PLA design.

UNIT IIIDESIGN FOR TESTABILITY FOR COMBINATIONAL CIRCUITS: Basic concepts of testability,controllability and observability, the Reed Muller’s expansion technique, OR-AND-OR design, use of control and syndrome testable design. Theory and operation of LFSR, LFSR as Signature analyzer, Multiple-input Signature Register.

UNIT IVDESIGN FOR TESTABILITY FOR SEQUENTIAL CIRCUITS: Controllability and observability bymeans of scan register, Storage cells for scan design, classic scan design, Level Sensitive Scan Design (LSSD).BUILT IN SELF TEST: BIST concepts, Test pattern generation for BIST exhaustive testing,Pseudorandom testing, pseudo exhaustive testing, constant weight patterns, Generic offline BIST architecture.

Text Books: 1. Fault Tolerant & Fault Testable Hardware Design-Parag K. Lala (PHI)2. Digital Systems Testing and Testable Design-M. Abramovili, M.A. Breues, A. D. Friedman – Jaico

publications.

Reference Books: 1. Fault tolerant systems- Israel Koren, C.Manikrishna, Morgan Kaufmann, 2007.

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M.Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: EMBEDDED NETWORKING (Elective-III) Course Code: ECEP2 1406

L T P C 3 1 0 4

Course objectives :

Students undergoing this course are expected to

Know basic concepts of embedded Networking Learn about control area network. Learn the network simulation, advanced features and testing of embedded network Know the CAN open standard. Understand the micro CAN open

Course Outcomes:

At the end of the course student can able to

Analyze embedded Networking applications Apply the concept of CAN in embedded applications like automotives Simulate and test the designed embedded networks Design embedded application using CAN open standard use micro CAN open for designing networking applications

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UNIT-IEmbedded networking – code requirements – Communication requirements – Introduction to CAN open –CAN open standard.Object directory – Electronic Data Sheets & Device – Configuration files – Service Data Objectives – Network management CAN open messages – Device profile encoder.

UNIT-IICAN open configuration – Evaluating system requirements choosing devices and tools – Configuring single devices.Overall network configuration – Network simulation – Network Commissioning – Advanced features and testing.

UNIT-IIIController Area Network – Underlying Technology CAN Overview – Selecting a CAN Controller – CAN development tools.Implementing CAN open Communication layout and requirements – Comparison of implementation methods.

UNIT-IVMicro CAN open – CAN open source code – Conformance test – Entire design life cycle.Physical layer –Data types – Object dictionary – Communication object identifiers – Emerging objects – Node states.

Text Books:

1. Embedded Networking with CAN and CAN open- GlafP.Feiffer, Andrew Ayre and Christian Keyold, Embedded System Academy 2005.

Reference books: 1. Principles of Embedded Networked Systems Design-Gregory J. Pottie, William J. Kaiser Cambridge University Press, Second Edition, 2005.

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M.Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: LOW POWER VLSI DESIGN (Elective-III) Course Code: ECEP2 1407

L T P C 3 1 0 4

Course objectives:

This course enables the students to

Understand the limitations of low power design

Know the importance of Bi-CMOS and advanced Bi-CMOS circuits

Learn the different isolation techniques in chip design

Understand the construction of low power memory elements

Learn design issues of Latches and Flip-Flops

Course outcomes

At the end of the course, the students can:

Design and estimate the power of different circuits

Apply Bi-CMOS and advanced Bi-CMOS circuits for different applications

Apply different isolation techniques in chip design

Design low power memory elements

Demonstrate the Latches and Flip-Flops in detail

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UNIT IIntroduction to low- voltage low power design, limitations, Silicon-on-Insulator. Bi CMOS processes. Integration and Isolation considerations, Integrated Analog/Digital CMOS Process.

UNIT IIConventional CMOS and BiCMOS logic gates. Performance evaluation. Comparison of advanced BiCMOS Digital circuits. ESD-free Bi CMOS Digital circuit.

UNIT IIIDesign and Test of Low Voltage CMOS Circuits: Introduction , circuit design style , Leakage current in deep submicrometer transistors , Deep submicrometer device design issues, Low voltage circuit design issues.Low power static RAM architectures: Introduction , organization of a static RAM , MOS static RAM memory cell , banked organization of SRAMs, Reducing voltage swings on bit lines, reducing power in the write driver circuits , Reducing power in sense amplifier circuits.

UNIT IVEvolution of Latches and Flip flops-quality measures for latches and Flip flops, Design perspective.Low energy computing using energy recovery techniques: Energy dissipation in transistor channel using an RC model , Energy recovery circuit design.

Text books: 1. CMOS/BiCMOS ULSI low voltage, low power -Yeo Rofail/ Gohl(3 Authors)-Pearson Education Asia 1st

Indian reprint,20022. Low Power CMOS VLSI Circuit Design - Kaushik Roy, Sharat Prasad, 2000.

Reference Books:

1. Practical Low Power Digital VLSI Design - Gary Yeap, 1997.

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M.Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: CPLD AND FPGA ARCHITECTURES & APPLICATIONS Course Code: ECEP2 1408 (Elective-IV)

L T P C3 1 0 2

Course objectives:

The main objective of the course is to:

Understand various PLDs, FPGAs and CPLD architectures. Analyze various FPGA like Xilinx XC4000 & ALTERA’s FLEX 8000/10000 AT &T ORCA’s. Analyze design methods of various FSMs. understand Digital front end digital design tools for FPGAs & ASICs understand System level design using mentor graphics EDA tool

Course outcomes

At the end of the course, the students can able to:

Implement the routing architecture, design flow, technology mapping for FPGAs. Design Xilinx XC4000 & ALTERA’s FLEX 8000/10000 AT &T ORCA’s in FPGA through

mapping. Realize of state machine charts using PAL in FSMs. Design Controller, data path design, Functional partition using digital design tools. Design the system level design for various architectures using mentor graphics EDA tools

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UNIT –I

PLDs: ROM, PLA, PAL, CPLD, FPGA – Features, Architectures, Programming,Applications and Implementation of MSI circuits using Programmable logic Devices.

CPLDs: Complex Programmable Logic Devices: Altera series – Max 5000/7000 series and Altera FLEX logic-10000 series CPLD, AMD’s- CPLD (Mach 1 to 5), Cypress FLASH 370 Device technology, Lattice pLSI’s architectures – 3000 series – Speed performance and in system programmability.

UNIT – II

FPGAs: Field Programmable Gate Arrays- Logic blocks, routing architecture, design flow, technology mapping for FPGAs, Case studies Xilinx XC4000 & ALTERA’s FLEX 8000/10000 AT &T ORCA’s(Optimized Reconfigurable Cell Array): ACTEL’s ACT-1,2,3.

Finite State Machines (FSM): Top Down Design, State Transition Table, State assignments for FPGAs, Realization of state machine charts using PAL, Alternative realization for state machine charts using microprogramming, linked state machine

UNIT-III

FSM Architectures: Architectures Centered around non registered PLDs, Design of state machines centered around shift registers, One_Hot state machine, Petrinets for state machines-Basic concepts and properties.

Design Methods: One –hot design method, Use of ASMs in one-hot design method, Applications of onehot design method, Extended Petri-nets for parallel controllers, Meta Stability, Synchronization, Complex design using shift registers.

UNIT-IV

System Level Design: Controller, data path designing, Functional partition, Digital front end digital design tools for FPGAs & ASICs, System level design using mentor graphics EDA tool

Case studies: Design considerations using CPLDs and FPGAs of parallel adder cell, parallel adder sequential circuits, counters, multiplexers, parallel controllers.

Text Books: 1. Field Programmable Gate Array Technology - S. Trimberger, Edr, 1994, Kluwer Academic Publications.2. Engineering Digital Design - RICHARD F.TINDER, 2nd Edition, Academic press.3. Fundamentals of logic design-Charles H. Roth, 4th Edition Jaico Publishing House.

Reference Books: 1. Digital Design Using Field Programmable Gate Array-P.K.Chan & S. Mourad, 1994, Prentice Hall.2. Field programmable gate array- S. Brown, R.J.Francis, J.Rose ,Z.G.Vranesic, 2007, BSP

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M.Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: HARDWARE SOFTWARE CO-DESIGN ( Elective-IV) Course Code:ECEP2 1409

L T P C 3 1 0 4

Course objectives:

Students undergoing this course are expected to

Learn basic concepts of Hardware software Co-design Know the Co-design Models, Algorithms and methodology etc… Understand Embedded Architectures, Embedded Software Development needs, Compilation

Technologies. Learn the Design specification and verification. Know the System-level performance modeling, low-level performance modeling and High-level

synthesis

Course Outcomes:

At the end of the course student can able to

Analyze any embedded system’s hardware and software design issues Choose different Co-design Models, Algorithms and methodology etc., for embedded system design Apply Embedded Software Development tools, Compilation Techniques for embedded applications Test the hardware and software individually Have complete knowledge on System-level performance modeling, low-level performance modeling

and High-level synthesis

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UNIT I

Co – Design Models, Architectures, Languages, A Generic Co-Design Methodology, Hardware – Software Synthesis Algorithms : Hardware – Software Partitioning, Distributed System Co-Synthesis.Prototyping and Emulation techniques, Prototyping and Emulation Environments, Future Developments in Emulation and Prototyping, Architecture Specialization Techniques,

UNITII

System Communication infrastructure, Target Architectures and Application System Classes, Architectures for Control Dominated System and Data – Dominated Systems.Modern Embedded Architectures, Embedded Software Development needs, Compilation Technologies, Practical Consideration in a compiler Development Environment. Design specification and verification: Design, Co- Design, The Co- Design Computational Model, Concurrency, coordinating Concurrent Computations, interfacing components

UNIT III

Design Verification, Implementation Verification, Verification Tools, Interface Verification.System – Level Specification, Design representation for system level synthesis, System level specification Languages, Heterogeneous Specifications and Multi Language Co – Simulation. The cosyma system and Lycos system.

UNIT IV System-level performance modeling vs. low-level performance modeling - Modeling of execution speed (system latency) and energy consumption for hardware and software - Estimation of memory requirements. High-level synthesis - behavioral specification of hardware, module set allocation, resource binding, operation scheduling, controller synthesis.

Text Books:

1. Hardware /Software Co – Design Principles and Practice, Kluwer AcademicPublishers,2nd printing 2000.

Reference Books:

1. Embedded System Design- Arnold S. Berger, CMP books, USA 2002.2. Computers as Components: Principles of Embedded Computer Systems Design-Wayne Wolf, Morgan

Kaufman Publishers, 2005.

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M.Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: SYSTEM MODELLING & SIMULATION (Elective-IV) Course code: ECEP1 1416

L T P C 3 1 0 4

Course objectives:

Students undergoing this course are expected to

Analyze approaches to system modeling and simulation

Understand simulation model for linear systems.

Developing simulation for motion control models.

Analyze state machine model

Develop Petri nets for a problem and its analysis

Understand the simulation of queuing systems

Know how to optimize the model

Course Outcomes:

Analyze the given system or problem Design a model to represent the system or problem simulate for the designed model Develop simulation models for time and event driven systems Design simulation models for given system using petri nets Analyze the queuing systems Optimize the model to get optimum performance

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UNIT I -INTRODUCTION TO SIMULATION - 14PBasic Simulation Modeling, Systems, Models and Simulation, Alternative approach to modeling and simulation.Guidelines for determining levels of model detail, Techniques for increasing model validity and credibility.Classification of Simulation Software,Desirable Software features, General purpose simulation packages – Arena, Extend and others,Object Oriented Simulation.

UNIT II -DISCRETE EVENT SIMULATION - 16PDiscrete Event Simulation, Simulation of Single server queingsystem, Simulation diagrams, Queing theory, simulating queing systems, Types of Queues, Multiple servers,Simulation of Inventory System.

UNIT III-BUILDING SIMULATION MODELS-13PModeling input signals, delays, System Integration, Linear Systems, Motion Control models, numerical experimentation,System identification, Searches, Alpha/beta trackers, multidimensional optimization and modeling and simulation methodology.

UNIT IV -STATE MACHINES MODEING AND SIMULATION -17PDisturbance signals, state machines, petri nets & analysis, System encapsulation,Probabilistic systems, Discrete Time Markov processes, Random walks, Poisson processes, the exponential distribution, simulating a poison process, Continuous – Time Markov processes.

Text Books: 1. System Modeling & Simulation, An introduction – Frank L.Severance, John Wiley&Sons, 2001.2. Simulation Modeling and Analysis – Averill M.Law, W.David Kelton, TMH, 3rd Edition,2003.

Reference Books:1. Systems Simulation – Geoffery Gordon, PHI, 1978

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M. Tech (VLSI & Embedded systems)2nd semesterA Y -2013-14

SYLLABUS

Course Title: EMBEDDED SYSTEMS LABORATORY Course Code: ECEP2 1210

L T P C 0 0 3 2

Course outcomes:

The main objective of the course is to:

Learn the complete knowledge on architecture of ARM and Programming Learn how to Interface different modules with ARM processor Understand the I2C Serial Communication Bus architecture and Programming. Simulate master slave devices using I2C Learn the Universal Serial Bus(USB) architecture and analyzing the properties of Different USB

Devices.

Course outcomes:

At the end of the course student can able to

Design prototype embedded projects using ARM9

Program and test different software and hardware modules

Program the I2C Serial Communication Bus . Test and identify the real time bugs with master and slave devices using I2C Capture the real time data transfer properties like Automatic Speed Detection and digital I/O for synchronizing etc using USB Analyzer.

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PART-1: Experiments on ARM 9 1. Basic data streaming with LEDs.2. Interfacing of Seven Segment Display.3. Interfacing of Matrix Key Pad. 4. Serial communication (USART).

PART-2: Experiments on I2C Development Board1. Simulate an I2C master or slave device.2. Program and verify I2C-based memory device.3. Passively monitor an I2C bus in real-time.

PART-3: Experiments on USB Analyzer1. Real-time capture and delayed-download capture2. High-Speed USB Chirp Detection3. Automatic Speed Detection4. Digital I/O for synchronizing