MPC5748GEVBUG, MPC5748G EVB User Guide · The EVB has connectors for various peripheral daughtercards (for example MLB) that provide ... MPC5748G EVB User Guide, User Guide, Rev

© 2015 Freescale Semiconductor, Inc. All rights reserved.

MPC5748G EVB User Guide By: Alasdair Robertson

Freescale Semiconductor, Inc. Document Number: MPC5748GEVBUG

User Guide Rev. 0 , 08/2015

MPC5748G EVB User Guide, User Guide, Rev. 0, 08/2015

2 Freescale Semiconductor, Inc.

Contents

1. INTRODUCTION ................................................................................................................................................................................. 3

1.1. Peripheral Daughtercards ............................................................................................................................................................. 3

2. EVB FEATURES .................................................................................................................................................................................. 3

3. CONFIGURATION OVERVIEW ......................................................................................................................................................... 5

4. MCU DAUGHTERCARD INFORMATION ........................................................................................................................................ 6

4.1. Fitting a daughtercard .................................................................................................................................................................. 6 4.2. Removing a daughtercard ............................................................................................................................................................ 6

5. INITIAL CONFIGURATION ............................................................................................................................................................... 7

5.1. Power Supply Configuration ....................................................................................................................................................... 7 5.1.1. Power Supply Connectors (P21, P23) .................................................................................................................................... 7 5.1.2. Power Switch (SW5) .............................................................................................................................................................. 8 5.1.3. Regulator Power Jumper (J23) ............................................................................................................................................... 8 5.1.4. Power Status LED’s and Fuse ................................................................................................................................................ 8 5.1.5. MCU Power Supply Jumpers (J18, J19, J20, J21, J22, J23) .................................................................................................. 9 5.1.6. Daughtercard Power Jumpers (J3 to J11) ............................................................................................................................. 10 5.1.7. Peripheral Power Supply Jumpers (J24, J25) ....................................................................................................................... 11 5.1.8. EVB Voltage Regulators ...................................................................................................................................................... 11

5.2. Reset Control (J9, SW1) ............................................................................................................................................................ 13 Note that removing jumper J9 will mean that an external reset source will not reset the MCU. This will impact most debuggers

which will typically issue a reset before establishing a debug connection. .......................................................................................... 13 5.2.1. Reset LEDs ........................................................................................................................................................................... 13

5.3. MCU Clock Configuration ........................................................................................................................................................ 14 5.3.1. External Clock Input (P7) ..................................................................................................................................................... 15 5.3.2. MCU Clock Configuration (J1, J2 on Daughtercard) ........................................................................................................... 15

5.4. Debug Connectors (P8, P10) ..................................................................................................................................................... 16 5.4.1. Debug Connector Pinouts ..................................................................................................................................................... 16

6. COMMUNICATIONS & MEMORY INTERFACES: ........................................................................................................................ 17

6.1. CAN Interfaces (P14, P15, J14, J15) ......................................................................................................................................... 17 6.2. LIN Interfaces (P9, P11, J10, J12) ............................................................................................................................................. 18 6.3. USB RS232 Serial Interface (P17, J16) ..................................................................................................................................... 19 6.4. USB HOST / OTG Interfaces .................................................................................................................................................... 20 6.5. Ethernet (P6, J5, J6, J7, J8, R45, R80) ....................................................................................................................................... 20 6.6. FlexRay (P2, P3, J1, J2, J3, J4) .................................................................................................................................................. 22 6.7. SD Card Socket (P200) .............................................................................................................................................................. 23

7. AV INTERFACE CONNECTORS ...................................................................................................................................................... 23

7.1. SAI Audio Connectors (P24, P25) ............................................................................................................................................. 23 7.2. TWRPI Connectors (P26, P27) .................................................................................................................................................. 25 7.3. MLB Daughtercard Connector (P16) ......................................................................................................................................... 25

8. USER INTERFACE (I/O) .................................................................................................................................................................... 26

8.1. GPIO Matrix .............................................................................................................................................................................. 26 8.2. User Switches (SW3, SW4, SW6, SW7, P22) ........................................................................................................................... 27 8.3. Hex Encoder Switch (SW2, J26, P20) ....................................................................................................................................... 28 8.4. User LED’s (DS2, DS3, DS7, DS8, P19) .................................................................................................................................. 29 8.5. ADC Input Potentiometer (J17, RV1) ....................................................................................................................................... 29

9. MCU PORT PIN EVB FUNCTIONS .................................................................................................................................................. 30

10. DEFAULT JUMPER SUMMARY TABLE ........................................................................................................................................ 31

11. DEFAULT JUMPER DIAGRAM ....................................................................................................................................................... 33

12. REVISION HISTORY ......................................................................................................................................................................... 33

13. APPENDIX .......................................................................................................................................................................................... 34



1. Introduction

This user guide details the setup and configuration of the Freescale MPC5748G customer Evaluation

Board (hereafter referred to as the EVB). The EVB is intended to provide a mechanism for easy

evaluation of the MPC5748G family of microcontrollers, and to facilitate hardware and software

development. Various daughtercards are available which connect to the EVB via two high density

connectors. Please consult your Freescale representative for more details on daughtercard pricing and

availability.

The EVB is intended for bench / laboratory use and has been designed using normal temperature

specified components (+70°C).

This product contains components that may be damaged by electrostatic discharge. Observe precautions

for handling electrostatic sensitive devices when using this EVB and associated microcontroller.

The user manual is intended to be read alongside the respective MCU documentation available at

www.freescale.com and includes:

Reference Manuals

Product Data Sheets

Application notes

Chip Errata

1.1. Peripheral Daughtercards

The EVB has connectors for various peripheral daughtercards (for example MLB) that provide

additional peripheral functionality. These are not supplied with the EVB and must be sourced separately.

Please contact your Freescale representative for pricing and availability.

2. EVB Features

The EVB provides the following key features:

Single 10-14 V DC external power supply input with on-board regulators to provide all of the

necessary EVB and MCU voltages. Power may be supplied to the EVB via a 2.1 mm barrel style

power jack or a 2-way screw type connector. 12 V operation allows in-car use if desired.

Master power switch and regulator status LED’s.

USB Serial interface

2 x High Speed CAN transceiver routed to 3-way headers

2 x LIN interfaces routed to standard Molex headers

Main clock supplied from on board crystal or SMA connector

User reset switch with reset status LED’s

Ethernet PHY and RJ45 socket configurable as RMII or MII

USB Type A Host interface

USB Type AB (micro USB) OTG interface

http://www.freescale.com/



2 x FlexRay interfaces with standard 2-pin connectors

14-pin JTAG and 50 pin Nexus (Trace) connectors

2 x High Density daughter card connectors allowing an MCU specific daughtercard to be fitted1

MLB daughtercard connector

SAI Audio board connectors (2 x 0.1 inch pitch headers and 2 x TWRPI style headers)

SD connector (mounted to the underside of the board) supporting hardware write protect and

card detection

4 user LEDs wired to MCU ports, also available at a user header

4 user pushbutton switches wired to MCU ports, also available at a user header

Hexadecimal encoded switch wired to 4 MCU ports, also available at a user header

Simple potentiometer connected to analogue input channel

NOTE

To alleviate confusion between jumpers and connector headers, all EVB

jumpers are 2 mm pitch whereas headers are 0.1 inch (2.54 mm). This

prevents inadvertently fitting a jumper to a header.

1 There is no MCU fitted to the EVB. A daughtercard must be fitted before the EVB can be used.

Configuration Overview


Freescale Semiconductor, Inc. 5

3. Configuration Overview

Throughout this document, all of the default jumper and switch settings are clearly marked with “(D)”

and are shown in blue text. This allows a more rapid return to the default state of the EVB if required.

Note that the default configuration for 3-way jumpers is a header fitted between pins 1 and 2. On the

EVB, 2-way, and 3-way jumpers have been aligned such that pin1 is either to the top or to the left of the

jumper. On 2-way jumpers, the source of the signal is connected to pin1.

The EVB has been designed with ease of use in mind and has been segmented into functional blocks as

shown below. Detailed silkscreen legend has been used throughout the board to identify all switches,

jumpers and user connectors.

Figure 1. EVB Functional Blocks



4. MCU Daughtercard information

In order to use the EVB, an MCU daughtercard must be fitted as described in the following section.

Before fitting or removing a daughtercard, ensure the EVB is powered OFF

4.1. Fitting a daughtercard

Gently place the daughtercard on the EVB connectors ensuring the correct orientation as shown in the

following figure. The connectors are polarized so the daughtercard will only fit in one orientation (with

the jumpers at the bottom of the daughtercard). Once the connectors have been located correctly, firmly

push down all four corners of the daughter card simultaneously in order to ensure the connectors are

mated. (The following picture also shows the default jumper positions for the 256BGA daughtercard)

Figure 2. Daughtercard Fitted to EVB

4.2. Removing a daughtercard

In order to prevent damage to the daughtercard connectors, it is important to remove the daughtercard

correctly. Carefully lift either the top or bottom edge of the daughtercard and it should easily lift off as

shown in the following figure (viewed from the left side of the EVB).

Figure 3. Removing a daughtercard

CAUTION

Do not attempt to lift the left or right edge of the daughtercard as this will

result in connector damage.

Initial Configuration



5. Initial Configuration This section details the power, reset, clocks, and debug configuration which is the minimum

configuration needed in order to power ON the EVB.

5.1. Power Supply Configuration

The EVB requires an external power supply voltage of between 10 V-14 V DC (nominal 12 V),

minimum 2 A. This allows the EVB to be used in a vehicle if required. The 12 V input is regulated on

the EVB using two switching and three linear regulators to provide the required voltages of 5.0 V, 3.3 V

(both linear and switcher) and 1.25 V (linear). For flexibility, there are two power supply input

connectors on the EVB as detailed below:

5.1.1. Power Supply Connectors (P21, P23)

2.1 mm Barrel Connector – P21

This connector should be used to connect the supplied wall-plug mains adapter. Note – if a

replacement or alternative adapter is used, care must be taken to ensure the 2.1 mm plug uses the

correct polarisation as shown below:

Figure 4. 2.1mm Power Connector

2-Way Screw Type Connector – P23

This can be used to connect a bare wire lead to the EVB, typically from a laboratory power supply.

The polarisation of the connectors is clearly marked on the EVB. Care must be taken to ensure

correct connection.

Figure 5. 2-Lever Power Connector

The Power supply section is located in the bottom left corner of the EVB



5.1.2. Power Switch (SW5)

Slide switch SW5 can be used to isolate the power supply input from the EVB voltage regulators if

required.

Moving the slide switch to the right (away from the fuse) will turn the EVB OFF.

Moving the slide switch to the left (towards the fuse) will turn the EVB ON.

5.1.3. Regulator Power Jumper (J23)

All of the regulators are permanently powered from the main 12 V supply line and active with the

exception of the 1.25 V linear regulator which has a 3-way jumper to allow selection of the input

voltage.

The table below details the jumper configurations for the linear 1.25 V regulator source voltage. By

default, the regulator is powered from the 12 V supply line.

Table 1. 1.25 V Linear Regulator Source Select (J23)

Jumper Position PCB Legend Description

J23

(INPUT SEL)

1-2 (D) 12V 1.25V Linear regulator is powered from main 12V

2-3 5V 1.25V Linear regulator is powered from 5V switching regulator output

Removed 1.25V Linear regulator is not powered (disabled)

5.1.4. Power Status LED’s and Fuse

When power is applied to the EVB, five green LED’s adjacent to the voltage regulators show the

presence of the supply voltages as follows:

LED DS4 – Indicates that the 1.25V linear regulator is enabled and working correctly



LED DS9 – Indicates that the 5.0V switching regulator is enabled and working correctly

LED DS10 – Indicates that the 3.3V switching regulator is enabled and working correctly

If no LED’s are illuminated when power is applied to the EVB and the regulators are correctly enabled

using the appropriate jumpers, it is possible that either power switch SW5 is in the “OFF” position or

that the fuse F1 has blown. The fuse is provided to protect the external power supply and for EVB

circuitry reverse-bias protection. If the fuse has blown, check the polarity of your power supply and

replace the fuse with a 20 mm 1.5 A fast blow fuse.

Note that the fuse will not protect against one of the EVB regulators being shorted. If this happens,

damage is likely to occur to the EVB and / or components.

CAUTION

In the event of a short in the regulator output, the regulator and/or the

shorted component may be hot




5.1.5. MCU Power Supply Jumpers (J18, J19, J20, J21, J22, J23)

All of the regulated power supplies are routed to the MCU daughtercard via jumpers. This allows each

power supply to be individually isolated and facilitates current measurement at the respective jumper.

Note that only the daughtercard is connected to the power lines after the jumpers so MCU current

measurements are accurate. There are an additional two jumpers that control the voltages used by EVB

peripherals connected to the VDD_HV_A and VDD_HV_B domains as described in section 5.1.7.

Figure 6. Power Supply Jumper Schematic

The MCU Daughtercard power jumpers are in the bottom left quarter of the EVB, above the power area



The power supply jumper description table is shown in the following table:

Table 2. Daughter Card Power Supply Jumpers (on main board)


J18

1V25L

Fitted (D) 1.25V Linear regulator output is routed to daughter card

Removed 1.25V Linear regulator output is disconnected from daughtercard

J19

5V0S

Fitted (D) 5.0V Switching regulator output is routed to daughter card

Removed 5.0V Switching regulator output is disconnected from daughtercard

J20

3V3L



J21

5V0L



J22

3V3S

Fitted (D) 3.3V Switching regulator output is routed to daughter card

Removed 3.3V Switching regulator output is disconnected from daughtercard

J23

INPUT SEL (Above Power

Jack)

1-2 (D) 12V 1.25v Linear regulator is powered by main 12V input

2-3 5V 1.25v Linear regulator is powered by output from 5.0V switching reg

Removed 1.25v Linear regulator is not powered (disabled)

5.1.6. Daughtercard Power Jumpers (J3 to J11)

The following power control jumpers are located on the MCU daughtercard. Note that not all of the

jumpers will be on each daughtercard variant.

Table 3. MCU Power Supply Jumpers (on daughtercard)


J3

ADC0

1-2 (D) 3V3 MCU ADC0 pin is connected to 3.3V (Linear)

2-3 5V0 MCU ADC0 pin is connected to 5.0V (Linear)

Removed MCU ADC0 pin is not connected to power

J4

ADC1

1-2 (D) 3V3 MCU ADC1 pin is connected to 3.3V (Linear)

2-3 5V0 MCU ADC1 pin is connected to 5.0V (Linear)

Removed MCU ADC1 pin is not connected to power

J5

HVA

1-2 (D) 3V3 MCU VDD_HV_A domain is connected to 3.3V (Switching Regulator)

2-3 5V0 MCU VDD_HV_A domain is connected to 5.0V (Switching Regulator)

Removed MCU VDD_HV_A domain is not connected to power

J6

HVB

1-2 (D) 3V3 MCU VDD_HV_B domain is connected to 3.3V (Switching Regulator)

2-3 5V0 MCU VDD_HV_B domain is connected to 5.0V (Switching Regulator)

Removed MCU VDD_HV_B domain is not connected to power

J7

HVC

1-2 (D) 3V3 MCU VDD_HV_C domain is connected to 3.3V (Switching Regulator)

2-3 5V0 MCU VDD_HV_C domain is connected to 5.0V (Switching Regulator)

Removed MCU VDD_HV_C domain is not connected to power





J8 2

FLA

Fitted (D) MCU VDD_HV_FLA pin is connected to 3.3v (Switching Regulator)

Removed MCU VDD_HV_C domain is connected to 5.0V (Switching Regulator)

J9

REG

1-2 (D) 3V3 MCU ballast transistor collector is connected to 3.3V (Switching)

2-3 5V0 MCU ballast transistor collector is connected to 5.0V(Switching)

Removed MCU ballast transistor collector is not connected to power

J10

VDDLV

1-2 (D) REG MCU VDD_LV domain is powered from ballast transistor

2-3 1V25L MCU VDD_LV domain is powered from 1.25V Linear regulator

Removed MCU VDD_LV domain is not powered

J11

DAC

1-2 (D) HVA MCU VIN1_CMP_REF is powered from VDD_HV_A

2-3 USR MCU VIN1_CMP_REF is powered from user testpoint (TPH3)

Removed MCU VIN1_CMP_REF is not powered

5.1.7. Peripheral Power Supply Jumpers (J24, J25)

There are two additional power supply jumpers controlling the I/O voltage for the peripherals on the

EVB in the HVA and HVB voltage domains.

The settings on these jumpers must match the VDD_HV_A and VDD_HV_B jumper voltage setting on

the MCU daughtercard.

The default configuration matches the MCU daughtercard default configuration with both jumpers set to

3.3V.

Table 4. Peripheral Power Control (J24, J25)


J24

HVA

1-2 (D) 3V3 EVB peripherals in HVA domain are set to use I/O voltage of 3.3V

2-3 5V0 EVB peripherals in HVA domain are set to use I/O voltage of 5.0V

Removed Invalid Configuration, avoid!

J25

HVB

1-2 (D) 3V3 EVB peripherals in HVB domain are set to use I/O voltage of 3.3V

2-3 5V0 EVB peripherals in HVB domain are set to use I/O voltage of 5.0V


5.1.8. EVB Voltage Regulators

The following table shows the usage of each EVB voltage regulator. This provides a useful cross

reference point should any regulator be disabled. In addition, the distribution of the peripheral voltages

HVA (J24) and HVB (J25) are shown.

2 Note that jumper J8 (FLA) jumper must only be fitted when VDD_HV_A (J5) is connected to 3.3V.

The peripheral power jumpers are in the bottom left quarter of the EVB, above the power area



Table 5. Power Supply Distribution

Regulator Used On

12V

(Unregulated)

P12V

All voltage regulators (switching and Linear, jumper selectable on 1.25V linear)

1.25V linear regulator LED supply via FET

MCU Daughtercard connector

MLB Daughtercard connector

FlexRay transceiver VBAT pin

5.0V

Switcher

5V0_SR

Daughtercard connector (post daughtercard power jumper)

Daughtercard connector (direct feed via zero ohm link)

Peripheral power control jumpers (position 2-3)

CAN transceivers VCC (main power)

USB RS232 (FTDI) transceiver (main power and protection diode)

USB Host / OTG transceiver power (VBAT) pin

FlexRay Transceiver power pins (VCC / VBUF)

SAI Audio connector

Input to 1.25V linear regulator (in alternate jumper configuration)

3.3V

Switcher

3V3_SR



Peripheral power control jumpers (position 1-2)

Reset LED’s (user and target)

USB HOST / OTG transceiver I/O voltage (USB operation is fixed at 3.3V)3

Ethernet Transceiver supply and I/O (Ethernet operation is fixed at 3.3V) 3

SAI Audio connector


SD Card power supply / pullup resistors (SD Card operation is fixed at 3.3V)3

User LED’s supply voltage

Hex encoder switch supply voltage

User pushbutton switches supply voltage

5.0V

Linear

5V0_LR



3.3V

Linear

3V3_LR




ADC Input Pot (user variable resistor)

1.25V

Linear

1V25_LR



J24 PER_HVA

Reset control circuitry (including reset pullup)

JTAG Pullup resistors & reference voltage

CAN Transceiver I/O Voltage select

LIN Transceiver Enable (and I/O voltage select)

USB RS232 (FTDI) transceiver I/O voltage select

FlexRay Transceiver I/O Voltage select (and pullups)

J25 PER_HVB Nexus Connector reference voltage and Pullups

3 These voltages are fixed due to device specifications and cannot be changed.




Note that the JTAG pins are in domain VDD_HV_A whereas the Nexus pins are VDD_HV_B.

Normally this would mean that for trace, the HVA and HVB domains should be at the same voltage

however some development tools can automatically adapt to the voltages on the trace signals. Please

consult your tools vendor for further details.

5.2. Reset Control (J9, SW1)

The MCU has a single bi-directional open drain Reset pin. Rather than connect multiple devices to the

reset pin directly, a reset-in and reset-out buffering scheme has been implemented on the EVB as shown

in Figure 7 below. The reset “in” from the reset switch (SW1) and the debug connectors are logically

OR’d together using an AND gate and then connected to the buffer to provide an open-drain output.

The “reset-out” circuitry provides a buffered reset signal that can be used to drive any circuitry requiring

a reset control from the MCU.

Figure 7. EVB Reset Control

Jumper J9 is used to disconnect the reset signal from the external reset sources if required.

Table 6. Reset Control (J9)


J9 (EN) Fitted (D)

Reset from reset switch and debug connectors is active

Removed Reset from reset switch and debug connectors is inactive

Note that removing jumper J9 will mean that an external reset source will not reset the MCU. This will

impact most debuggers which will typically issue a reset before establishing a debug connection.

5.2.1. Reset LEDs

As can be seen in Figure 7 above, there are two reset LED’s that can be used to identify the source /

cause of a reset:

The reset circuitry and switch are located in the top left quarter of the EVB next to theRJ45 connector



RED LED D1 (titled “MCU”) will illuminate if:

The MCU issues a reset (in this condition ONLY this LED will be illuminated and LED DS1

will be off)

There is a target reset (ie from the reset switch or from the debugger in which case LED DS1

will be ON)

YELLOW LED DS1 (titled “USR”) will illuminate when an external hardware device issues a reset to

the MCU:

The reset switch is pressed

There is a reset being driven from one of the debug connectors

Table 7. Reset LED Decoding

LED DS1 (Yellow) LED D1 (Red) Description

OFF OFF No Reset being issued from MCU or external logic

OFF ON MCU has issued a reset

ON OFF External reset issued from switch or debug BUT not being issued to MCU

(check J9 is fitted on the EVB)

ON ON External reset issued from reset switch or debug and has been issued to MCU.

5.3. MCU Clock Configuration

There are 2 clock configuration jumpers on the daughtercard and an external clock input connector on

the main board to allow an externally generated clock to be supplied if desired. See Figure 8 below.

Figure 8. EVB Clock Selection




5.3.1. External Clock Input (P7)

The external clock input on the EVB is applied via SMA connector P7. When driving an external clock

into the SMA connector, the jumpers on the daughtercard must be reconfigured to route the external

clock to the MCU.

Note that the following conditions must be met when supplying an external clock:

The clock frequency must be between 8MHz and 40MHz

The amplitude of the clock input should not exceed the voltage being driven into the

VDD_HV_A pins. This is selectable between 3.3V and 5.0V on the daughtercard.

5.3.2. MCU Clock Configuration (J1, J2 on Daughtercard)

There are two external clock crystals on the MPC5748G daughtercards:

40MHz fast external crystal for clocking the main system clock

32KHz slow external crystal for accurate time of day keeping

The 40MHz crystal is connected to the MCU XTAL and EXTAL pins via 3-way jumper headers as

shown in the diagram above. These jumpers allow an external clock to be routed from the SMA

connector (P7) on the main board if desired. The default configuration is with both daughtercard

jumpers (J1 and J2) set to position 1-2 which routes the external 40MHz crystal to the MCU pins. If you

wish to supply a clock via the SMA connector on the main EVB, move the daughtercard jumpers J1 and

J2 to position 2-3.

The 32 KHz external crystal is permanently connected to the MCU EXTAL32 and XTAL32 pins and

has no configuration options.

Table 8. EXTAL Clock Source Selection (J1, J2 Daughtercard)


J1 (XTAL) 1-2 (D) Y1 MCU XTAL signal is routed to crystal Y1

2-3 GND MCU XTAL signal is Grounded (for ext clock mode)4

J2 (EXTAL) 1-2 (D) Y1 MCU EXTAL signal is routed to crystal Y1

2-3 EXT MCU EXTAL signal is routed from EVB SMA P7

4 Note that the XTAL pin is left open by default with J1 in position 2-3. Resistor R34 must be populated with a zero

ohm resistor in order to ground the XTAL pin.

The external SMA clock connector is located in the top left corner of the EVB



5.4. Debug Connectors (P8, P10)

The EVB provides two debug connectors:

Standard 14 pin JTAG

50 Pin Nexus connector (Samtec ASP-148422-01, Nexus Standard HP50 connector)

There is no user configuration required to use the connectors however the following points should be

noted:

The JTAG connector is routed to the JTAG signals in the default position which are powered

from the MCU VDD_HV_A power domain. The Nexus signals are located in the VDD_HV_B

power domain. If you are using Nexus, you may have to ensure that the VDD_HV_A and

VDD_HV_B domains are at the same voltage. Consult your tools vendor for specific information

The Nexus signals are not bonded out in every MCU package. Before using Nexus, please ensure

the MCU fitted to the EVB (via the daughtercard) supports the Nexus signals.

5.4.1. Debug Connector Pinouts

The following tables list the pinouts for each of the debug connectors used on the EVB

Table 9. 14-Pin JTAG Debug Connector Pinout

Pin No Function Connection Pin No Function Connection

1 TDI PC0 2 GND GND

3 TDO PC1 4 GND GND

5 TCLK PH9 6 GND GND

7 EVTI PL8 8 N/C ---

9 RESET JTAG-RSTx 10 TMS PH10

11 VREF PER_HVA 12 GND GND

13 RDY --- 14 JCOMP 10K Pulldown

Table 10. 50-pin Samtec (Nexus) Debug Connector Pinout


1 MSEO_0 PL9 2 VREF PER_HVB

3 MSEO_1 PL11 4 TCK PH9

5 GND GND 6 TMS PH10

7 MDO0 PL2 8 TDI PC0

9 MDO1 PL3 10 TDO PC1

11 GND GND 12 JCOMP 10K Pulldown

13 MDO2 PL4 14 RDY ---

15 MDO3 PL5 16 EVTI PL8

17 GND GND 18 EVTO PL12

19 MCKO PL10 20 RESET DBUG_RST

21 MDO4 PL6 22 RST_OUT MCU_RST

23 GND GND 24 GND GND

25 MDO5 PL7 26 CLKOUT Test Point

27 MDO6 PL13 28 TD/WT ---


The JTAG and Nexus debug connectors are in the top right corner of the EVB

Communications & Memory Interfaces:




31 MDO7 PL14 32 DAI1 ---

33 MDO8 PL15 34 DAI2 ---


37 MDO9 PM0 38 ARBREQ ---

39 MDO10 PM1 40 ARBGRT ---


43 MD011 PM2 44 MDO13 PM8

45 MDO12 PM7 46 MDO14 PM9


49 MDO15 PM10 50 N/C ---

6. Communications & Memory Interfaces:

This section details the communication interface and storage peripherals that are implemented on the

EVB.

6.1. CAN Interfaces (P14, P15, J14, J15)

The EVB incorporates two identical CAN interface circuits connected to MCU CAN0 and CAN1 using

MC33901 transceivers. Both transceivers are configured for high speed operation by pulling pin 8 to

GND via a 4.7K Ohm resistor. There are test points to allow the Select pin to be driven high if desired.

The MC33901 is pin compatible with other CAN transceivers supporting full CAN FD data rates.

For flexibility, the CAN transceiver I/O is connected to a standard 0.1” connector (P14 for CAN1 / P15

for CAN0) rather than using non standard DB9 connectors. The pinout of these headers is shown below

and is also detailed on the PCB silkscreen

Figure 9. CAN Physical Interface Connectors

The CAN0 and CAN1 MCU TX/RX signals are jumpered as shown in the table below to allow the

transceivers to be isolated from the respective MCU pin if desired. The default configuration is with all

jumper headers fitted routing the TX and RX signals to the MCU.

H

L

GND

1

The CAN Physical interface circuits are located on the left edge of the EVB



Table 11. CAN Control Jumpers (J51, J53)


J15 (CAN0)

Posn 1-2

FITTED (D) TX

MCU CAN0_TX signal (PB0) is routed to CAN interface

Removed MCU CAN0_TX signal (PB0) is not routed to CAN interface

J15 (CAN0)

Posn 3-4

FITTED (D) RX

MCU CAN0_RX signal (PB1) is routed to CAN interface

Removed MCU CAN0_RX signal (PB1) is not routed to CAN interface

J14 (CAN1)

Posn 1-2

FITTED (D) TX

MCU CAN1_TX signal (PC10) is routed to CAN interface

Removed MCU CAN1_TX signal (PC10) is not routed to CAN interface

J14 (CAN1)

Posn 3-4

FITTED (D) RX

MCU CAN1_RX signal (PC11) is routed to CAN interface

Removed MCU CAN1_RX signal (PC11) is not routed to CAN interface

NOTE

Care should be taken when fitting the jumper headers to the 2x2 jumper

blocks J14 and J15 as they can easily be fitted in the incorrect orientation.

Jumper headers should be fitted horizontally.

The CAN TX / RX MCU pins are powered from the VDD_HV_A domain, which is configured between

3.3V and 5.0V on the daughtercard using jumper J5. The CAN transceivers I/O voltage is connected to

the PER_HVA net configured with jumper J24 on the main EVB. Care must be taken to ensure that the

MCU VDD_HV_A and PER_HVA supplies are the same when using the CAN transceiver.

6.2. LIN Interfaces (P9, P11, J10, J12)

The EVB incorporates two identical LIN transceiver circuits connected to MCU LIN0 and LIN1 using a

Freescale MC33662LEF transceiver supporting both master and slave mode (jumper selectable)

The output from the LIN transceiver is connected to a standard 4-pin Molex connector as used on most

other Freescale EVB’s supporting LIN as shown in the following figure:

Figure 10. LIN Molex Physical Interface Connector

The LIN Physical interface circuits are located on the left edge of the EVB




The LIN0 and LIN1 MCU TX/RX signals are jumpered as shown in the following to allow the

transceivers to be isolated from the respective MCU pin if desired. The default configuration is with all

jumper headers fitted routing the TX and RX signals to the MCU.

Each transceiver also has a master mode enable jumper which is fitted by default to configure the

transceiver for Master mode. To configure the transceiver for slave mode, remove the respective

“Master_EN” jumper.

Table 12. LIN Control Jumpers (J10, J11, J12, J13)


J10 (LIN0)

Posn 1-2

FITTED (D) RX

MCU LIN0_RX signal (PB3) is routed to LIN0 interface

Removed MCU LIN0_RX signal (PB3) is not routed to LIN0 interface

J10 (LIN0)

Posn 3-4

FITTED (D) TX

MCU LIN0_TX signal (PB2) is routed to LIN0 interface

Removed MCU LIN0_TX signal (PB2) is not routed to LIN0 interface

J11

(Master_EN)

FITTED (D)

LIN0 is configured in Master Mode

Removed LIN0 is configured in Slave Mode

J12 (LIN1)

Posn 1-2

FITTED (D) RX

MCU LIN1_TX signal (PC7) is routed to LIN1 interface

Removed MCU LIN1_TX signal (PC7) is not routed to LIN1 interface

J12 (LIN1)

Posn 3-4

FITTED (D) TX

MCU LIN1_RX signal (PC6) is routed to LIN interface

Removed MCU LIN1_RX signal (PC6) is not routed to LIN interface

J13

(Master_EN)

FITTED (D)

LIN1 is configured in Master Mode

Removed LIN1 is configured in Slave Mode

NOTE


blocks J10 and J12 as they can easily be fitted in the incorrect orientation.

Jumper headers should be fitted horizontally

The LIN TX / RX MCU pins are powered from the VDD_HV_A domain, which is configured between

3.3V and 5.0V on the daughtercard using jumper J5. The LIN transceivers enable pin is connected to the

PER_HVA net configured with jumper J24 on the main EVB. Care must be taken to ensure that the

MCU VDD_HV_A and PER_HVA supplies are the same when using the LIN transceiver.

Note that in order for the LIN transceiver to function, external power must be supplied via pin 3 of the

molex connector as detailed in Figure 10.

6.3. USB RS232 Serial Interface (P17, J16)

The EVB incorporates a USB RS232 serial interface providing RS232 connectivity via a direct USB

connection between the PC and the EVB. The circuit contains an FTDI FT2232D USB to Serial

interface which should automatically install the drivers for two additional COM ports on your PC. Note

that only one of these is used so you will need to try both (usually the higher numbered COM port is the

active one). For more information on the USB drivers and general fault finding, consult the FTDI

website at http://www.ftdichip.com/

The MCU LIN2 signals are routed to the FTDI transceiver via a 2-way jumper header (J16) allowing the

transceiver to be isolated from the MCU pin if desired. The default configuration is with the jumper

The USB RS232 interface is on the left hand edge of the board (USB Type B socket)

http://www.ftdichip.com/



header fitted, routing the TX and RX signals from the MCU to the FTDI transceiver. No other

configuration is required.

Table 13. USB RS232 Control Jumpers


J16

Posn 1-2

FITTED (D) RX

MCU LIN2_RX signal (PC9) is routed to the FTDI interface

Removed MCU LIN2_RX signal (PC9) is not routed to the FTDI interface

J16

Posn 3-4

FITTED (D) TX

MCU LIN2_TX signal (PC8) is routed to the FTDI interface

Removed MCU LIN2_TX signal (PC8) is not routed to the FTDI interface

NOTE


block J16 as they can easily be fitted in the incorrect orientation. Jumper

headers should be fitted horizontally.

The MCU LIN2 (SCI) pins are powered from the VDD_HV_A domain, which is configured between

3.3V and 5.0V on the daughtercard using jumper J5. The FTDI transceiver I/O voltage pin is connected

to the PER_HVA net configured with jumper J24 on the main EVB. Care must be taken to ensure that

the MCU VDD_HV_A and PER_HVA supplies are the same when using the FTDI transceiver.

6.4. USB HOST / OTG Interfaces

The EVB includes Type A (Host) and Type AB (OTG) USB interfaces, routed to standard and micro

USB sockets respectively. Each USB circuit contains a USB83340 transceiver with a shared USB power

switch. There is no user configuration required on either of the USB circuits.

The USB transceivers have a 3.3V (only) interface. All of the USB0 (connected to the OTG transceiver)

and USB1 (connected to the HOST transceiver) signals are in the VDD_HV_A domain and must be

configured as 3.3V via daughtercard jumper J5. If VDD_HV_A is set to 5V, the USB0 and USB1 MCU

signals should be left tri-stated to prevent damage to the USB transceivers.

6.5. Ethernet (P6, J5, J6, J7, J8, R45, R80)

The MPC5748G supports both MII and RMII Ethernet interfaces. The EVB incorporates a DP83848c

transceiver supporting both MII and RMII modes. The transceiver is connected to a pulse J1011F21PNL

RJ45 connector which includes a built-in isolation transformer.

The default configuration, with all 2-way jumpers fitted and all 3-way jumpers in position 1-2,

configures the transceiver for MII mode with the reset signal to the PHY being driven from the MCU

Reset out (eg any reset causing the MCU Reset line to assert will reset the PHY)

In order to configure the EVB for RMII mode, jumpers J5, J6 and J7 need to be changed as described in

Table 14 below. In addition, a surface mount 0Ω resistor needs to be de-soldered and moved as shown in

the figure below. This option is fitted as a resistor instead of a jumper to maintain signal integrity on the

Ethernet clock signal.

The USB interfaces are on the top right quarter on the board on the top edge

The USB interfaces are on the top right quarter on the board on the top edge




For MII mode (default) R45 should have a jumper populated as shown. For RMII mode, remove R45

and fit it between R45 and R80

Figure 11. MII / RMII Clock Selection Resistor

To change the reset routing so that the Ethernet PHY can be reset via MCU pin PI11 (rather than being

tied to the MCU reset), jumper J8 should be moved to position 2-3

Table 14. Ethernet Control jumpers (J5, J6, J7, J8, R45, R80)


J5

1-2 (D) MII Ethernet PHY is configured in MII mode

2-3 R Ethernet PHY is configured in RMII mode


J6

(X1)

1-2 (D) Ethernet PHY X2 clock is connected to 25MHz xtal

2-3 Ethernet PHY X2 clock is not connected to 25MHz xtal5, 6

J7

(X2)

1-2 (D) Ethernet PHY X1 clock is connected to 25MHz xtal

2-3 Ethernet PHY X1 clock is driven from 50MHz xtal

Removed Ethernet PHY X1 clock is disconnected (invalid configuration, avoid)

J8

(RST)

1-2 (D) NORM The Ethernet PHY will be reset along with MCU reset

2-3 PI11 The Ethernet PHY reset is controlled via MCU pin PI11 (Pulled high)


R45 (R80) Fitted R45 MII Mode – Clock is supplied from PHY to MCU

R45 to R80 RMII Mode – Clock is supplied from external 50MHz oscillator to MCU

The MCU Ethernet signals are all in the VDD_HV_B domain. The Ethernet PHY will ONLY function

with 3.3V I/O so VDD_HV_B must be set to 3.3V on the MCU daughtercard before the Ethernet is

used. If VDD_HV_B is set to 5V, the signals routed to the Ethernet PHY (see the EVB schematics) must

be left as tristate.

5 If jumper J7 is in position 1-2 (25MHz XTAL), J6 must be fitted and R45 must be fitted.

6 If jumper J7 is in position 2-3 (50MHz oscillator), J6 must be removed and R45 must be removed and placed

between R45 and R80

For RMII mode

remove R45 and re-fit

in this position



6.6. FlexRay (P2, P3, J1, J2, J3, J4)

The EVB incorporates two FlexRay TJA1080TS/N interfaces connected to MCU FlexRay channels A

and B and routed to two Molex 1.25mm pitch PicoBlade shrouded headers (standard on many Freescale

EVB’s). Jumpers are provided to disconnect the MCU signals from the FlexRay interface if required as

well as providing general configuration.

By default, all of the jumper headers are fitted which routes the MCU signals to the FlexRay physical

interface as well as configuring the controller for a default mode of operation (Transmitter enabled,

Receiver enabled, not in low power mode). Please consult the FlexRay transceiver and general FlexRay

specifications before changing any of the mode jumpers.

Table 15. FlexRay Configuration Jumpers (J1, J2, J3, J4)


FlexRay A

J3

Posn 1-2

FITTED (D) TX

MCU PC5 is connected to FlexRay A transceiver TX

Removed MCU PC5 is not connected to FlexRay A transceiver TX

J3

Posn 3-4

FITTED (D) TXEN

MCU PE2 is connected to FlexRay A transceiver TXEN

Removed MCU PE2 is not connected to FlexRay A transceiver TXEN

J3

Posn 5-6

FITTED (D) RX

MCU PE3 is connected to FlexRay A transceiver RX

Removed MCU PE3 is not connected to FlexRay A transceiver RX

J2

Posn 1-2

FITTED (D) BGE

FlexRay A PHY Bus Guardian Enable (Transmitter is enabled)

Removed FlexRay A PHY transmitter is disabled (Receive only mode)

J2

Posn 3-4

FITTED (D) EN

FlexRay A PHY is enabled

Removed FlexRay A PHY is disabled

J2

Posn 5-6

FITTED (D) STBN

FlexRay A PHY will not enter Standby Mode

Removed FlexRay A PHY will enter Standby Mode

J2

Posn 7-8

FITTED (D) WAKE

FlexRay A PHY Wakeup signal pulled low

Removed FlexRay A PHY Wakeup signal pulled high

FlexRay B

J4

Posn 1-2

FITTED (D) TX

MCU PE4 is connected to FlexRay B transceiver TX

Removed MCU PE4 is not connected to FlexRay B transceiver TX

J4

Posn 3-4

FITTED (D) TXEN

MCU PC4 is connected to FlexRay B transceiver TXEN

Removed MCU PC4 is not connected to FlexRay B transceiver TXEN

J4

Posn 5-6

FITTED (D) RX

MCU PE5 is connected to FlexRay B transceiver RX

Removed MCU PE5 is not connected to FlexRay B transceiver RX

J1

Posn 1-2

FITTED (D) BGE

FlexRay B PHY Bus Guardian Enable (Transmitter is enabled)

Removed FlexRay B PHY transmitter is disabled (Receive only mode)

J1

Posn 3-4

FITTED (D) EN

FlexRay B PHY is enabled

Removed FlexRay B PHY is disabled

J1

Posn 5-6

FITTED (D) STBN

FlexRay B PHY will not enter Standby Mode

Removed FlexRay B PHY will enter Standby Mode

J1

Posn 7-8

FITTED (D) WAKE

FlexRay B PHY Wakeup signal pulled low

Removed FlexRay B PHY Wakeup signal pulled high

The FlexRay interface is in the top right corner of the EVB on the top edge

AV Interface Connectors



The MCU FlexRay pins are powered from the VDD_HV_A domain, which is configured between 3.3V

and 5.0 V on the daughtercard using jumper J5. The FlexRay tranceivers I/O voltage pin is connected to

the PER_HVA net configured with jumper J24 on the main EVB. Care must be taken to ensure that the

MCU VDD_HV_A and PER_HVA supplies are the same when using the FlexRay transceiver.

6.7. SD Card Socket (P200)

The EVB supports a 4-bit SD interface (note that MPC5748G supports 8-bit SD data) which is routed to

a full sized SD card connector on the underside of the EVB. There is no user configuration required.

The SD socket has hardware card detection (routed to PA0) and write protection (routed to PH8) status

outputs which will be grounded when active.

The MCU SD card signals are all in the VDD_HV_A domain. The SD card specification is for an

interface voltage of between 2.7V and 3.6V so the SD card can only be used when VDD_HV_A is set to

3.3V (PER_HVA has no impact on the voltage on the SD card)

CAUTION

If VDD_HV_A is set to 5V, damage may be caused to an SD card if an

attempt is made to access it in software. If you need to leave the SD card

in the socket with VDD_HV_A set to 5V, ensure all the SD card pads are

left as high impedance

7. AV Interface Connectors

This section details the Audio / Video interface connectors on the EVB. Each of these connectors can be

used to add additional daughtercards (not supplied) to add functionality.

7.1. SAI Audio Connectors (P24, P25)

The EVB includes two 0.1” headers that can be used to interface to an SAI audio board (available

separately, please consult your Freescale representative). There is no EVB configuration required when

using these connectors other than to ensure the EVB is switched off prior to fitting or removing the

daughtercard.

The pinout of the connectors is shown below for reference and these connectors can also be used for

GPIO connectivity

Important:

The EVB daughtercards are supplied with a 40 MHz crystal which is a requirement for FlexRay in

order to generate the correct clock timing. If you have changed the default crystal on the daughtercard

and wish to use FlexRay, you must ensure a 40 MHz crystal is fitted.

The SD socket is mounted on the underside of the board in the top left corner

The SAI audio connector is on the bottom edge of the EVB



Table 16. 50-pin SAI Audio Daughtercard Connector P24


1 3.3V 3V3_SR 2 GND GND

3 SAI0_DATA3 PF2 4 GND GND




11 SAI0_BCLK PF1 12 GND GND

13 SAI0_SYNC PB10 14 GND GND

15 SAI0_MCLK PF0 16 GND GND

17 eMIOS1_7H PH5 18 GND GND

19 I2C_SCL3 PE11 20 GND GND

21 I2C_SDA3 PE10 22 GND GND

23 SAI1_DATA0 PJ2 24 GND GND

25 SAI1_BCLK PJ3 26 GND GND


29 SAI1_SYNC PF6 30 GND GND

31 SAI1_MCLK PF7 32 GND GND

33 I2C_SCL2 PE9 34 GND GND

35 I2C_SDA2 PE8 36 GND GND

37 SAI2_DATA0 PI14 38 GND GND

39 SAI2_BCLK PJ1 40 GND GND

41 SAI2_SYNC PJ0 42 GND GND

43 SAI2_MCLK PI15 44 GND GND


47 GPIO Control PA5 48 GND GND

49 5.0V 5V0_SR 50 GND GND

Table 17. 20-pin SAI Audio Daughtercard Connector P25


1 N/C N/C 2 GND GND

3 DSPI0_SIN PA12 4 GND GND

5 DSPI0_SOUT PA13 6 GND GND

7 DSPI0_SCK PA14 8 GND GND

9 DSPI0_SS0 PA15 10 GND GND

11 DSPI3_SOUT PG2 12 GND GND

13 DSPI3_SS3 PG3 14 GND GND

15 DSPI3_SCK PG4 16 GND GND

17 DSPI3_SIN PG5 18 GND GND

19 N/C N/C 20 GND GND

Note that connector P25 is not populated and must be fitted if required

CAUTION

Before the daughtercard is installed or removed, the EVB must be

powered OFF to prevent potential damage to the EVB or daughter card

components.

AV Interface Connectors



7.2. TWRPI Connectors (P26, P27)

The EVB includes two fine pitch TWRPI headers that can be used to interface to an SAI audio board

(available separately, please consult your Freescale representative) along with the 0.1” headers

mentioned in the section above. There is no EVB configuration required when using these connectors

other than to ensure the EVB is switched off prior to fitting or removing the daughtercard. The pinout of

the connectors is shown below for reference.

Table 18. TWRPI Connector P26


1 5V 5V0_SR 2 3.3V 3V3_SR

3 GND GND 4 3.3V 3V3_LR

5 GND GND 6 GND GND

7 GND GND 8 ADC0 PD5

9 ADC1 PD6 10 GND GND

11 GND GND 12 ADC2 PD4



17 ID0 PD77 18 ID17 PD8

19 GND GND 20

Table 19. TWRPI Connector P27


1 GND GND 2 GND GND

3 I2C0_SCL PO0 4 I2C0_SDA PO1

5 GND GND 6 GND GND

7 GND GND 8 GND GND

9 DSPI0_SIN PA12 10 DSPI0_SOUT PA13

11 DSPI0_SS0 PA15 12 DSPI0_SCK PA14


15 GPIO0/IRQ PK3 16 GPIO1 PK0

17 GPIO2 PK1 18 GPIO3 PK2

19 GPIO4 PK4 20 N/C N/C

7.3. MLB Daughtercard Connector (P16)

There is a 40-pin interface connector on the EVB for connecting an MLB (Media Local Bus)

daughtercard. There is no hardware configuration possible at EVB level for this connector.

MLB Daughtercards are available direct from SMSC

As with all daughtercards, the EVB must be powered OFF to prevent damage to the EVB or daughter

card components.

7 ID0 and ID1 have a 10K pullup to 3V3

The TWRPI connectors are at the bottom right hand corner

The MLB daughtercard connector is on the RHS of the EVB



8. User Interface (I/O)

This section details the user I/O available on the EVB and includes the GPIO matrix, switches, LED’s

and the ADC variable resistor.

8.1. GPIO Matrix

All of the available GPIO pins (those not already used for existing EVB peripherals) are available at the

GPIO matrix shown below. The matrix provides an easy to follow, intuitive, space saving grid of 0.1”

header through-hole pads. Users can solder wires, fit headers or simply insert a scope probe into the

respective pad.

To use the matrix, simply read the port letter from the top or bottom row of text then the pad number

from the columns on the left or right of the matrix. For example, the 1st pad available on Port B is PB5

as highlighted in green below.

Figure 12. GPIO Matrix

If a pad is populated in the matrix, it means this is available for exclusive use as GPIO. The exception to

this are the port pins detailed below which are also shared with switches or user LED’s (shaded red in

the matrix diagram above).

PG2, PG3, PG4, PG5 – User LED’s 1..4

PD0, PD1, PD2, PD3 – HEX Encoder Switch

PA1,PA2, PF9, PF11 – User pushbutton Switches

In addition there are GPIO pins that are shared with the SAI Audio and TWRPI connectors as detailed

below and shaded orange. These are totally available unless the SAI / TWRPI headers are being used.

PA[12..15], PD[4..8], PG[2..5], PK[0..4], PO[0..1]

The GPIO matrix is on the bottom edge of the EVB above the SAI audio connector

User Interface (I/O)



8.2. User Switches (SW3, SW4, SW6, SW7, P22)

There are 4 active high (pulled low, driven to 3.3V) pushbutton switches (SW3, SW4, SW6, SW7)

connected to a 4 way header (P22) in a box titled “User Switches”. The switches are also directly

connected to MCU ports so no additional wiring is required unless you require to route these to a

different GPIO port.

The switches are connected as follows:

Table 20. User Pushbutton Switches (SW3, SW4, SW6, SW7)

Switch Number MCU Pin P18 Connection Pin

SW3 1 PA1 Pin1 (UpperMost)

SW4 2 PA2 Pin2

SW6 3 PF9 Pin3

SW7 4 PF11 Pin4

NOTE

The MCU ports used on the user pushbutton switches are also routed to

the GPIO matrix.

There are zero ohm resistors on the direct connections between each

switch and the MCU pins. These can be removed if required to isolate the

switch from the respective MCU pin (useful if the switch is being

manually routed to another pin on the GPIO matrix).

The user pushbutton switches are in the bottom left corner of the EVB



8.3. Hex Encoder Switch (SW2, J26, P20)

There is a single hex encoded 16 position rotary switch on the EVB. This outputs a binary encoded hex

value (active high) on 4 MCU ports (Port D[0..3]) as well as a 4 pin header P20. There is a jumper J26

which can be used to isolate the supply to the hex encoder if required. This prevents any voltage being

asserted on the MCU pins irrespective of the position of the switch

Table 21. Hex Encoder Switch (SW2)

Position HEX_SW4

(PD3, P20-4)

HEX_SW3

(PD2, P20-3)

HEX_SW2

(PD1, P20-2)

HEX_SW1

(PD0, P20-1)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

A 1 0 1 0

B 1 0 1 1

C 1 1 0 0

D 1 1 0 1

E 1 1 1 0

F 1 1 1 1

Table 22. Hex Encoder Switch Power Jumper (J26)


J26

(3V3)

FITTED (D)

The hex encoder switch is powered with 3.3V (functional)

Removed The hex encoder switch is not powered and will not drive outputs

NOTE

The MCU ports used on the user pushbutton switches are also routed to

the GPIO matrix.

There are zero ohm resistors on the direct connections between the switch

output and the MCU pins. These can be removed if required to isolate the

switch from the respective MCU pin (useful if the switch is being

manually routed to another pin on the GPIO matrix).

The hex encoder switch is located above the user pushbutton switches

User Interface (I/O)



8.4. User LED’s (DS2, DS3, DS7, DS8, P19)

There are four active low user LED’s connected directly to 4 MCU ports (PG[2..5]) as well as to a 4 pin

header.

Table 23. User LEDs (DS2, DS3, DS7, DS8, P19)

Switch Number MCU Pin P19 Connection Pin

DS2 1 PG2 Pin1 (Upper Pin)

DS3 2 PG3 Pin2

DS7 3 PG4 Pin3

DS8 4 PG5 Pin4

NOTE

The MCU ports used on the LEDs are also routed to the GPIO matrix.

There are zero ohm resistors on the direct connections between each LED

and the MCU pins. These can be removed if required to isolate the LED

from the respective MCU pin (useful if the LED is being manually routed

to another pin on the GPIO matrix).

8.5. ADC Input Potentiometer (J17, RV1)

There is a small variable resistor RV1 on the EVB which routes a voltage between 0v and 3.3V to MCU

pin PB4. This is useful for quick ADC testing. Jumper J17 which is fitted by default can be removed to

disconnect MCU PB4 from RV1 if desired.

Table 24. ADC Input Potentiometer Enable (J19)


J17

FITTED (D) Output from RV1 is routed to MCU PB4 pin

Removed MCU PB4 is not connected to RV1

There is also a test point TP18 connected to the variable resistor output for monitoring purposes.

The user LED’s are above the user switches in the lower right quarter

The ADC Pot is to the right of the user LED’s in the lower right corner



9. MCU Port Pin EVB Functions

The table below shows what each MCU pin is used for on the EVB. Note that not all MCU pins will be

available depending on the device package being used.

Table 25. Port Pin Functions

No PortA PortB PortC PortD PortE PortF PortG PortH

0 SD Card CAN0 JTAG GPIO 3 MLB SAI Audio Ethernet Ethernet

1 GPIO 2 CAN0 JTAG GPIO 3 MLB SAI Audio Ethernet Ethernet

2 GPIO 2 LIN0 USB1 GPIO 3 FlexA SAI Audio GPIO 4, 5 Ethernet

3 Ethernet LIN0 USB1 GPIO 3 FlexA SAI Audio GPIO 4 , 5 SAI Audio

4 GPIO ADC Pot FlexB GPIO 5 FlexB SAI Audio GPIO 4, 5 SAI Audio

5 SAI Audio GPIO FlexA GPIO 5 FlexB SAI Audio GPIO 4 , 5 SAI Audio

6 MLB GPIO LIN1 GPIO 5 SD Card SAI Audio GPIO MLB

7 Ethernet GPIO LIN1 GPIO 5 SD Card SAI Audio GPIO MLB

8 Ethernet EXTAL32 RS232 GPIO 5 SAI Audio GPIO GPIO SD Card

9 Ethernet XTAL32 RS232 GPIO SAI Audio GPIO 2 MLB JTAG

10 Ethernet SAI Audio CAN1 GPIO SAI Audio GPIO USB1 JTAG

11 Ethernet GPIO CAN1 GPIO SAI Audio GPIO 2 USB1 USB1

12 GPIO 5 GPIO Flex GPIO Ethernet GPIO Ethernet USB1

13 GPIO 5 MLB Flex GPIO 1 Ethernet GPIO Ethernet GPIO

14 GPIO 5 MLB Flex MLB USB1 Ethernet USB1 GPIO

15 GPIO 5 MLB Flex MLB USB1 Ethernet USB1 GPIO

No PortI PortJ PortK PortL PortM PortN PortO PortP PortQ

0 SD Card SAI Audio GPIO 5 GPIO NEXUS GPIO GPIO 5 GPIO USB0

1 SD Card SAI Audio GPIO 5 GPIO NEXUS GPIO GPIO 5 GPIO USB0

2 SD Card SAI Audio GPIO 5 NEXUS NEXUS GPIO GPIO GPIO USB0

3 SD Card SD Card GPIO 5 NEXUS GPIO GPIO GPIO GPIO USB0

4 USB1 GPIO GPIO 5 NEXUS GPIO GPIO GPIO GPIO USB0

5 USB1 GPIO GPIO NEXUS GPIO GPIO GPIO GPIO USB0

6 USB0 GPIO GPIO NEXUS GPIO GPIO GPIO GPIO USB0

7 USB1 GPIO GPIO NEXUS NEXUS GPIO GPIO GPIO USB0

8 MLB GPIO GPIO JTAG NEXUS GPIO GPIO GPIO -

9 GPIO GPIO GPIO NEXUS NEXUS GPIO GPIO GPIO -

10 GPIO GPIO GPIO NEXUS NEXUS GPIO GPIO GPIO -

11 Ethernet GPIO GPIO NEXUS GPIO GPIO GPIO GPIO -

12 GPIO 1 GPIO GPIO NEXUS GPIO GPIO GPIO USB0 -

13 GPIO 1 GPIO GPIO NEXUS GPIO GPIO GPIO USB0 -

14 SAI Audio GPIO GPIO NEXUS GPIO GPIO GPIO USB0 -

15 SAI Audio GPIO GPIO NEXUS GPIO GPIO GPIO USB0 -

1 Shared with MLB header (via no populated zero ohm resistors)

2 Shared with user switches

3 Shared with Hex Encoder Switch

4 Shared with user LED’s

5 Shared with TWRPI (P26, P27) or SAI Audio P25

Default Jumper Summary Table



10. Default Jumper Summary Table The following tables detail the default (D) jumper configuration of the EVB and daughtercards

Table 26. Default Jumper Positions (Main Board)

Jumper Default

Posn

PCB

Legend

Description

J1 Posn 1-2 Fitted (D) BGE FlexRay B PHY Bus Guardian Enable (Transmitter is enabled)

J1 Posn 3-4 Fitted (D) EN FlexRay B PHY is enabled

J1 Posn 5-6 Fitted (D) STBN FlexRay B PHY will not enter Standby Mode

J1 Posn 7-8 Fitted (D) WAKE FlexRay B PHY Wakeup signal pulled low

J2 Posn 1-2 Fitted (D) BGE FlexRay A PHY Bus Guardian Enable (Transmitter is enabled)

J2 Posn 3-4 Fitted (D) EN FlexRay A PHY is enabled

J2 Posn 5-6 Fitted (D) STBN FlexRay A PHY will not enter Standby Mode

J2 Posn 7-8 Fitted (D) WAKE FlexRay A PHY Wakeup signal pulled low

J3 Posn 1-2 Fitted (D) TX MCU PC5 is connected to FlexRay A transceiver TX

J3 Posn 3-4 Fitted (D) TXEN MCU PE2 is connected to FlexRay A transceiver TXEN

J3 Posn 5-6 Fitted (D) RX MCU PE3 is connected to FlexRay A transceiver RX

J4 Posn 1-2 Fitted (D) TX MCU PE4 is connected to FlexRay B transceiver TX

J4 Posn 3-4 Fitted (D) TXEN MCU PC4 is connected to FlexRay B transceiver TXEN

J4 Posn 5-6 Fitted (D) RX MCU PE5 is connected to FlexRay B transceiver RX

J5 1-2 (D) MII Ethernet PHY is configured in MII mode

J6 (X1) 1-2 (D) Ethernet PHY X2 clock is connected to 25MHz xtal

J7 (X2) 1-2 (D) Ethernet PHY X1 clock is connected to 25MHz xtal

J8 (RST) 1-2 (D) NORM The Ethernet PHY will be reset along with MCU reset

J9 (EN) Fitted (D) Reset from reset switch and debug connectors is active

J10 (LIN0) 1-2 Fitted (D) RX MCU LIN0_RX signal (PB3) is routed to LIN0 interface

J10 (LIN0) 3-4 Fitted (D) TX MCU LIN0_TX signal (PB2) is routed to LIN0 interface

J11 (Master_EN) Fitted (D) LIN0 is configured in Master Mode

J12 (LIN1) 1-2 Fitted (D) RX MCU LIN1_TX signal (PC7) is routed to LIN1 interface

J12 (LIN1) 3-4 Fitted (D) TX MCU LIN1_RX signal (PC6) is routed to LIN interface

J13 (Master_EN) Fitted (D) LIN1 is configured in Master Mode

J14 (CAN1) 1-2 Fitted (D) TX MCU CAN1_TX signal (PC10) is routed to CAN interface

J14 (CAN1) 3-4 Fitted (D) RX MCU CAN1_RX signal (PC11) is routed to CAN interface

J15 (CAN0) 1-2 Fitted (D) TX MCU CAN0_TX signal (PB0) is routed to CAN interface

J15 (CAN0) 3-4 Fitted (D) RX MCU CAN0_RX signal (PB1) is routed to CAN interface

J16 Posn 1-2 Fitted (D) RX MCU LIN2_RX signal (PC9) is routed to the FTDI interface

J16 Posn 3-4 Fitted (D) TX MCU LIN2_TX signal (PC8) is routed to the FTDI interface

J17 Fitted (D) Output from RV1 is routed to MCU PB4 pin

J18 (1V25L) Fitted (D) 1.25V Linear regulator output is routed to daughter card

J19 (5V0S) Fitted (D) 5.0V Switching regulator output is routed to daughter card



J22 (3V3S) Fitted (D) 3.3V Switching regulator output is routed to daughter card

J23 (INPUT SEL) 1-2 (D) 12V 1.25V Linear regulator is powered from main 12V

J24 (HVA) 1-2 (D) 3V3 EVB peripherals in HVA domain are set to use I/O voltage of 3.3V

J25 (HVB) 1-2 (D) 3V3 EVB peripherals in HVB domain are set to use I/O voltage of 3.3V

J26 (3V3) Fitted (D) The hex encoder switch is powered with 3.3V (functional)



Table 27. Default Jumper Positions (Daughtercards)

Note that not all jumpers will be present on all of the daughtercards.

Jumper Default

Posn

PCB

Legend

Description

1 (XTAL) 1-2 (D) Y1 MCU XTAL signal is routed to crystal Y1

J2 (EXTAL) 1-2 (D) Y1 MCU EXTAL signal is routed to crystal Y1

J3 (ADC0) 1-2 (D) 3V3 MCU ADC0 pin is connected to 3.3V (Linear)

J4 (ADC1) 1-2 (D) 3V3 MCU ADC1 pin is connected to 3.3V (Linear)

J5 (HVA) 1-2 (D) 3V3 MCU VDD_HV_A domain is connected to 3.3V (Switching Regulator)

J6 (HVB) 1-2 (D) 3V3 MCU VDD_HV_B domain is connected to 3.3V (Switching Regulator)

J7 (HVC) 1-2 (D) 3V3 MCU VDD_HV_C domain is connected to 3.3V (Switching Regulator)

J8 (FLA ) Fitted (D) MCU VDD_HV_FLA pin is connected to 3.3v (Switching Regulator)

J9 (REG) 1-2 (D) 3V3 MCU ballast transistor collector is connected to 3.3V (Switching)

J10 (VDDLV) 1-2 (D) REG MCU VDD_LV domain is powered from ballast transistor

J11 (DAC) 1-2 (D) HVA MCU VIN1_CMP_REF is powered from VDD_HV_A

J12 Fitted (D) Ballast collector supply is enabled (jumper can be used for current measure)

J13 1-2 (D) ** Only valid on certain devices – External Ballast enabled.

Default Jumper Diagram



11. Default Jumper Diagram The diagram below shows the location and configuration of the default jumpers of the main board and

provides an easy to use cross reference. By default all of the jumpers are fitted to the daughtercard (3

way jumpers in position 1-2).

NOTE

Following figure is of an older board revision however there were no

additional jumpers and no jumpers have moved position.

Figure 13. Default Jumper Position

12. Revision History

Date Substantial changes

August 2015 Initial release



13. Appendix

The following EVB schematics are detailed in the following sections:

Main EVB (motherboards)

324BGA Daughtercard

256BGA Daughtercard

176QFP Daughtercard

100QFP Daughtercard (MPC5746C only)

Main EVB

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

X5

Freescale AISG Applications, East Kilbride

X6

X2X3X4

Audio - SAI Audio. AVB and TWRPI headers

Revision Information

0.1DesignerAlasdair Robertson

CommentsRev Date

Power - Switching voltage regulators

Reset and External Clock Input

Sheet 8Sheet 9Sheet 10Sheet 11Sheet 12Sheet 13Sheet 14Sheet 15Sheet 16

These schematics are provided for reference purposes only. As such,Freescale does not make any warranty, implied or otherwise, as to thesuitability of circuit design or component selection (type or value) used inthese schematics for hardware design using the Freescale MPC574xG familyof Microprocessors. Customers using any part of these schematics as abasis for hardware design, do so at their own risk and Freescale does notassume any liability for such a hardware design.

Sheet 2Sheet 3Sheet 4Sheet 5Sheet 6Sheet 7Comms - CAN and LIN

Comms - EthernetComms - USB Interfaces

Memory - SD Card SlotAV - MOST Interface

User notes are given throughtout the schematics.

Specific PCB LAYOUT notes are detailed in ITALICS

Caution:

19 Feb 2012

Comms - RS232 (USB FTDI interface)

Comms - FlexRAY

User - Switches, LED's and PotentiometerUser - GPIO Pin Matrix

Table Of Contents:

Notes:

MPC574xx Customer Evaluation Board (X-MPC574XG-MB)

- All components and board processes are to be ROHS compliant- All small capacitors are 0402 unless otherwise stated- All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated- All jumpers are denoted Jx. Jumpers are 2mm pitch- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2. 2 Pin jumpers generally have the "source" on pin 1.- All switches are denoted SWx- All test points (SMT wire loop style) are denoted TPx- Test point Vias (just through hole pads) are denoted TPVx

X1Power - Main input and Linear voltage regulators

Daughter Card Connectors (Sockets)

JTAG and Nexus Connectors

Start of capture, Working version01 Feb 20121st release for internal review (Complete Board)

28 Feb 2012Alasdair RobertsonAlasdair Robertson 2nd release for internal review (split into main board and DC)

Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes.

Alasdair RobertsonVersion sent to Pre Layout, incorporating fixes from reviewFinal review (including new USB transceiver)11 Mar 2013

Alasdair Robertson13 Mar 201314 Mar 2013 Alasdair Robertson Component consolodation, Few minor changes. Sent to Layout

3 Different test points used in design:

TPVx - Through Hole Pad small

TPHx - Through Hile Pad Large (for standard 0.1" header).Also used on IO Matrix (IOMx)

TPX - Surface Mount Wire Loop

29 Mar 2013 Alasdair Robertson Changes made during layout to Daughtercard Connectors

A Post Layout (Back Annotated). Matches PCB RevAAlasdair Robertson02 Apr 2013 Alasdair Robertson LAY RefDes Resequence and SCH BackAnnotateX717 Apr 2013

AX1 24 Jun 2013 Alasdair Robertson Fixes and changes to RevA Prototype designAX2 10 July 2013 Alasdair Robertson Added CAN Term (DNP)AX3 12 July 2013 Alasdair Robertson Corrected ground on ADC PotB 12 July 2013 Alasdair Robertson Production ReleaseBX1 20 Aug 2013 Alasdair Robertson Change to Ethernet 50MHz clock controlC 20 Aug 2013 Alasdair Robertson Production ReleaseCX1 18 Dec 2013 Alasdair Robertson CAN transceivers -> MC33901, ENET clock in RMII modeCX2 05 May 2014 Alasdair Robertson Added comment about LM1117 VREG outputCX3 25 June 2014 Alasdair Robertson PH3..5 now GPIO matrix (was SAI), PM4, PD13, PM3 to SAICX4 26 June 2014 Alasdair Robertson Minor changes made during layout (no component changes)CX5 26 June 2014 Alasdair Robertson Part Manager Tidy upCX6 18 Aug 2014 Alasdair Robertson Added additional connector with DSPI Signals for AVBCX7 03 Sept 2014 Alasdair Robertson Added additional TWRPI header (Sheet 12)D 24 Sept 2014 Alasdair Robertson Released to Production (RevD PCB)D1 14 Aug 2015 Alasdair Robertson Tidy up Schematics for UM (RevD PCB)

Drawing Title:

Size Document Number Rev

Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:

Automotive Microcontroller ApplicationsEast Kilbride, Scotland

This document contains information proprietary to Freescale and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of Freescale

SCH-27897 PDF: SPF-27897 D1

MPC574xx Customer EVB Main Board

B

Friday, August 14, 2015

Index and Title Page

A. Robertson

A. Robertson

A. Robertson

1 16

Freescale General Business Use

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27897 PDF: SPF-27897 D1


B



A. Robertson

A. Robertson

A. Robertson

1 16


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27897 PDF: SPF-27897 D1


B



A. Robertson

A. Robertson

A. Robertson

1 16


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Rfb1

Rfb2

Main EVBPower In

Vout = 1.25(1 + (R2/R1)) = 5.0V

(060350V)

GND Test Points, Top Side

Rfb1

Rfb2

Vout = 1.25(1 + (R2/R1)) = 3.295V

3.3V Linear Regulator (800mA Max **)

(35V TANT)(35VTANT)

(0402 50V)

Could also use 2x82 Ohm resistors for RFB2 but not in agile...

1% resitors1% resitors

Rfb1

Rfb2

Vout = 1.25(1 + (R2/R1)) = 1.25V

1% resitors


(35V TANT)(35VTANT)

Power Input and Linear Voltage Regulators

Input 12V DC nominal (range 10v - 14v)See note on schematic sheet 3 regarding 3.3V regulator when running at < 11V)

1.25V for External core supply. Simpler to use linear rather than switcher so can safelypower from 5V switcher (slight ripple not an issue) for reduced heat dissipation

(c200 radpol 50V)

2.1mm BarrelConnector

(2 Screw Connector)

(Power Switch)

Power Supply Input and Filter Test and reference points

GND Test Points for underside of board


(35V TANT)(35VTANT)

(CC7343-4325V)

(10v-14v)

(3A)

(3A)

1K Loadresistor toensure properregulation if1.25V MCUjumper removed

The LM1117 linear regulators provide a maximum outputcurrent of 800mA in ideal conditions. The currentrequirement for each regulator is in the region of 10'sof mA (significantly under the maximum rating) sothese regulators will run cool on the EVB.

** Notes on Linear Regulator LM1117

VFused12V-IN VSwitched

3V3_LRP12V

GND

1V25_LR

GND

P12V

5V0_SR

GND

P12V

GND

GND

GND

5V0_LRP12V

GND

GND

P12V

Drawing Title:


Date: Sheet of

Page Title:

Automotive MicrocontrollerApplicationsEast Kilbride, Scotland

SCH-27897 PDF: SPF-27897 D1


B



2 16

Freescale General Business UseDrawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



2 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



2 16


DS6

LED GREEN

AC

R3051K

GND13

1

GND4

1

C2680.1UF

TP17

1

L527uH

1 2F1

Fuse Holder

1 2

GND10

1

R77 0

R72 100DNP

GND17

1

GND7

1

GND1

1

+ C2710UF R73 100

U16

LM1117MPX-ADJADJ

1

VOUT2IN

3TAB_VOUT

4

R273270

GND5

1

P23

A1

B2

+ C2610UF

U15

LM1117MPX-ADJADJ

1

VOUT2IN

3TAB_VOUT

4

GND8

1

+ C3010UF

DS5

LED GREEN

AC

R76 0

GND12

1

+ C321000UF

GND2

1

DS4

LED GREEN

A C

GND15

1

+ C2910UF

C2691000pF

R74 100

P211

32

R271 5.6

GND3

1

R284 0

+C3368UF

R75 0

DNP

SW51 34 2

5

R272 0R70 300

GND11

1

+ C2810UF

GND9

1

TP16

1

GND14

1

TP15

1

D202B340A

AC

R274560

U14

LM1117MPX-ADJADJ

1

VOUT2IN

3TAB_VOUT

4

GND6

1

J231

2

3

GND16

1

R285 0

GND18

1

Q1BSH103

1

23

R71 158

+ C3110UF

R283 1.8K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Design requiresB220A-13-Fdiode. Use3Aversion toreduce no ofcomponents

(12v input, 2.0A Output, 89% Efficient, 11.24w)

Switching Voltage Regulators and Supply Jumpers

5.0v Switching Regulator

(121025V)

(060350V)

(0603 50V)

(All Resistors 1% 0603_CC)

Rfb1

Rfb2

Vout = 1.21(1 + Rfb2/Rfb1) = 4.98V

APXE100ARA151MF80G

(121025V)

APXE100ARA151MF80G

(060350V)

3.3v Switching Regulator

(12v input, 2A Output, 83% Efficient)

(0603 50V)

(All Resistors 1% 0603_CC)

Rfb1

Rfb2

Vout = 1.21(1 + Rfb2/Rfb1) = 3.3V

Using Adjustable version of LM2676 rather than fixed 3.3V /5V regulators to reduce number of components in BOM.

Where possible, components have been shared accross theregulator designs to further reduce component count.

The 3.3v regulator design is optimised for an input voltage of 12V. Ifthe input voltage drops below approx 11V, the 3.3v output voltageripple may increase. This can be reduced by increasing the bulk storagecapacitor if required.

Caution

Global MCU DaughtercardSupply Jumpers and DC power

Peripheral Power Control

These jumpers control the voltage of theperipherals connected to MCU pads in theVDD_HV_A / HV_B domains and are requiredso the respective jumpers at the MCU canbe used for MCU current measurement.

The settings on these jumpers mustmirror the setting of the respectiveMCU VDD_HV_A / HB_V jumpers

To DaughtercardConnectors

MCU_3V3_S

MCU_5V0_S

MCU_3V3_L

MCU_5V0_L

MCU_1V25_L

DC_5V0_S

DC_3V3_S

DC_5V0_L

DC_3V3_L

DC_1V25_L

DC_P12V

P12V

GND

5V0_SR

GND

GND

3V3_SR

P12V

GND

3V3_SR

5V0_SR

3V3_LR

5V0_LR

1V25_LR

5V0_SR

3V3_SR

PER_HVA PER_HVB

P12V

DC_5V0_S 4

DC_3V3_S 4

DC_5V0_L 4

DC_3V3_L 4

DC_1V25_L 4

DC_P12V 4

MCU_1V25_L 4

MCU_5V0_S 4

MCU_5V0_L 4

MCU_3V3_S 4

MCU_3V3_L 4

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


Switching Voltage Regulators

3 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



3 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



3 16


D5B340A

AC

C266

0.1UF

R267 0DNP

TP19

1

J181 2

TP20

1

C267

0.1UF

R297 261.0

C265 10nF

R291 0

R266 0DNP

C264 10nF

+ C36150uF

D6B340A

AC

R298 1.65K

J28DNP

12

J211 2

R294 0

J251

2

3

C34

10uF

R300560

J201 2

U17 LM2676S-ADJ

INPUT2

SW_OUT1

C_BOOST3

GN

D4

TAB

8

FEEDBACK6

ON/OFF7

NC5 R263 0

DNP

DS9

LED GREEN

AC

J191 2

DS10

LED GREEN

AC

R293 1.47K

R265 0DNP

C35

10uF

R292 1.0K

U18 LM2676S-ADJ

INPUT2

SW_OUT1

C_BOOST3

GN

D4

TAB

8

FEEDBACK6

ON/OFF7

NC5

R264 0DNP

R268 0DNP

J241

2

3

L7 27uH1 2

R296 1.47K

J27DNP

12

R295 1.0K

+ C37150uF

L6 27uH1 2

R299270

J221 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Socket

Not routed through the connectors:- Crystal signals- Specific MCU power pins (Power supplies are however taken to daughtercard)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)


Socket

Notes:

- there was no neat way to fit these connectors onto a B sized sheet so unfortunately the sheet size has beenincreased to C so will need to be printed on larger paper.

- The MCU Clock circuitry (apart from external clock) is local to the daughtercard so not pinned out on theconnectors- Power is supplied to the daughtercard via MCU specific jumpered supplies (left connector) or direct suppliesfrom the regulators (right connector)

(GND) (GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND) (GND)

(GND)(GND)

(GND)

(GND)(GND)

(GND)(GND)

(GND)

(GND)(GND)

(GND) (GND)

(GND)

(GND)

(GND)

(GND) (GND)PM11 PC1PH10 PE3PH4 PH5

PL4

PE15

PL9

PL3

PH12

PG11

PG10

PL8

PORSTx

PH11

PE14

PG15

PC4

PQ1

PQ2

PQ6

PP13PP12

PE2

PA6

PA5

PQ4

PQ5PQ7 PI4PP15 PP14

PL12 PL2

PL13PL6PM0

PM10

PL7

PM8PH3

PM6

PI11PI12PD12PD9PD13

PI15PD10PB7

PB3PH8

PH7

PP8

PH6

PP3PE7PK9

PC12PK11

PP4PC8 PK14PK13 PK12

PC9PP2 PL0PK15PC15 PP1PP7

PC14PP6 PJ4

PO12PO7PO10PO4 PH14PO9 PO13

PO1PG5PH13PO14

PO0 PG4PI7 PH15PP0 PO15

PE10PE1 PE0PI6 PO6PO5PE11 PG2PG3 PA2

PE9PE8 PA1

MCU-RSTxPG9 PN15PA0 PO3

PG7 PG6PG8 PC11PC10 PO2

PB0

PB10PN0

PN6PN3PA15PN10

PA4PJ13

PN9PJ9

PB1 PK1PK2 PF12

PK3PK5PF11

PF9PA14PN13

PN11PJ11PJ10PK0

PL10

PE5

PG14

PM12

PQ0PI5

PC5

PQ3

PE4PC3

PC2

PA8

PH2-RPG0-RPF14

PA9PA10

PA7

PG1PF15PE13

PA11PE12

PL11 PL5

PH1-RPH0-RPA3

PG12-RPG13-R

PI13

PM4PL1

PM5

PM3

PM14PM13

PB12

PF5PI9PD8

PJ3PJ2PB4

PM15PF2

PD7PJ5PJ0

PD5PB5

PJ1PD1PB11

PI10PD0PB6

PN1PF6PD4

PI14PJ7PD11PJ6PD6PD2

PJ8PD3

MLB_DATMLB_CPMLB_CN

MLB_CLKMLB_SIG

MLB_SNMLB_SP

MCU_5V0_S

MCU_1V25_L

MCU_3V3_S

MCU_3V3_LMCU_5V0_L

PO11PO8

PA12

PF0PF1PN2

PN5

PA13PN4

PJ14PN7PF10PN8

PJ15

PC7PN12PJ12

PF8

PK7PC6

PF13PK4PK6

PN14PK8

DC_3V3_S

DC_5V0_LDC_3V3_L

DC_5V0_SDC_5V0_SDC_5V0_S

DC_P12VDC_1V25_L

PF3PF7PF4

PL15

PM2PM1

PL14

PM7PM9

MLB_DNMLB_DP

PE6PI3PP10PP5PI1PI2PP9PC13PI0PK10

PB2

PP11

EXT-CLK

PC0

PH9

GND GNDGND GND

PH7 13PH6 13PB3 7

PP8 16PH8 14

PP3 16PE7 14PK9 16

PC12 11PK11 16

PP4 16PK14 16PK12 16PC9 8PL0 16

PP1 16

PC14 11PJ4 16

PH14 16PO13 16

PO1 12,16PH13 16PG4 12,15,16PH15 16PO15 16PE10 12PE0 13PO6 16

PG2 12,15,16PA2 15,16PE9 12PA1 15,16MCU-RSTx 5,6PN15 16PO3 16

PG6 16PC11 7PO2 16

PB0 7PK1 12,16PF12 16

PK3 12,16PK5 16PF11 15,16

PC1 6PE3 11PH5 16

PQ3 9PC3 9PE4 11

PL10 6PE15 9PORSTx 5PE2 11PL4 6PG11 9PQ1 9

PG10 9PQ2 9PL8 6PQ6 9

PP13 9PP12 9PI4 9PP14 9

PL2 6PL5 6PL13 6PM0 6

PA10 10PA9 10PA8 10PF14 10PG0-R 10PH2-R 10

PG12-R 10PG13-R 10

PM10 6PM4 12,16PL1 16

PM5 16PI13 13,16PB12 16PD9 16PI12 13,16PB7 16PI15 12

MLB_CN 13MLB_CP 13

PI14 12PJ7 16PD11 16PJ6 16PD6 12,16PD2 15,16PD3 15,16PJ8 16

PB6 16PD0 15,16PI10 16

PD4 12,16PF6 12PN1 16

PC88PK1316

PP216PK1516PC1511PP716

PP616

PO1216PO716PO1016PO416PO916

PG512,15,16PO1416PO012,16PI79PP016

PE113PI69PO516PE1112PG312,15,16

PE812

PG913PA014

PG716PG816PC107

PB17PK212,16

PF915,16PA1412,16PN1316

PN1116PJ1116PJ1016PK012,16PJ916PN916

PJ1316PA416

PN1016PA1512,16PN316PN616

PN016PB1012

PM1116PH106PH416PE511PM1216PI59PQ09PC511

PG149PH129PC411

PL96PC29PA613PL36PH119PA512PE149PQ49PG159PQ59PQ79PP159

PL126PL116PL66PL76

PE1210PA1110

PA710PE1310PF1510PG110PH1-R10PH0-R10PA310

PM86PH316PM312,16PM616PM1316PM1416

PD1312,13,16PD1216PI1110PD1016

MLB_DAT13MLB_SIG13MLB_CLK13

MLB_SN13MLB_SP13

PD712,16PJ516PJ012

PD512,16PB516PB1116PD115,16PJ112

PD812,16PI916PF512PB415PJ212PJ312

PF212PM1516

MCU_5V0_S3

MCU_1V25_L3

PO11 16PO8 16

PN5 16PA12 12,16PN2 16PF1 12PF0 12

PN4 16PA13 12,16

PN8 16PF10 16PN7 16PJ14 16

PJ15 16

PC7 7PN12 16PJ12 16

PF8 16

PK7 16PC6 7

PF1316PK412,16PK616PK816PN1416

DC_5V0_S3

DC_P12V3DC_1V25_L3

PF4 12PF7 12PF3 12

PL156PM16PM26

PL14 6PM9 6PM7 6

MLB_DN 13MLB_DP 13


PB27

PP1116

EXT-CLK5

PC0 6

PH9 6

MCU_3V3_S 3

MCU_3V3_L 3MCU_5V0_L 3

DC_3V3_S 3

DC_3V3_L 3DC_5V0_L 3

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


C



4 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


C



4 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


C



4 16


P12

CON SKT 180

1SH1 SH2

SH5 SH6

23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 60

SH3 SH4

61 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100

101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120

SH7 SH8

SH9 SH10121 122123 124125 126127 128129 130131 132133 134135 136137 138139 140141 142143 144145 146147 148149 150151 152153 154155 156157 158159 160161 162163 164165 166167 168169 170171 172173 174175 176177 178179 180

SH11 SH12

P13

CON SKT 180

1SH1 SH2

SH5 SH6

23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 60

SH3 SH4

61 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100

101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120

SH7 SH8

SH9 SH10121 122123 124125 126127 128129 130131 132133 134135 136137 138139 140141 142143 144145 146147 148149 150151 152153 154155 156157 158159 160161 162163 164165 166167 168169 170171 172173 174175 176177 178179 180

SH11 SH12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TARGETRESETLED

Reset Switch(1.65 to 5.5v operation)

(MCU RESET)

Tri-State BufferedRESET signal toreset the MCU

Reset and External Clock In

Buffered RESET-out

Note:

The Reset pad on the MPC5748G is in the VDD_HV_A domain which can be run from either3.3V or 5V (selected by the VDD_HV_A and PER_HVA jumpers)

To maintian brightness on the LED's irrespective of the voltage setting, the LED's arepowered from constant 3.3V, grounded via the reset line.

Bi Directional resetline to/from MCU

Active reset drive (high / low)for any periperhals that need tobe reset when MCU is in reset

Reset fromDebugger

Reset Input / OutputPORSTConnect an external LVI to padwhen supplying external 1.25V sothat PORST is asserted untilexterbal 1.25V supply is atthreshold and stable

(2.5 to 5v operation)

SMA styleConnector

External Clock In (SMA)

(060350V)(0603

50V)

(060350V)

Reset is in theVDD_HVA domain.

MCU-RSTxJTAG-RSTx

RST-SWITCHx

RST-OUTx

RST-INxSYSTEM-RSTx

PORSTx

EXT-CLK

GND

GND

GND

3V3_SR

GND

GND

PER_HVA

3V3_SR

PER_HVA

GND

JTAG-RSTx6MCU-RSTx 4,6

RST-OUTx 10,12

PORSTx 4

EXT-CLK 4

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


Reset Circuitry & External Clock In

5 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



5 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



5 16


R2410.0K

J91 2

R214 270

R3110.0K

SW1 B3WN-60021 2

C30.1UF

VCC

GND

U4A

SN74LVC2G08DCT

1

27

84

R410.0K

P7

CON 1 SMA

1

24 35

R217270

TPV5

U4B

SN74LVC2G08DCT

5

63

C2200.1UF

U3

ADM6315-26D2ARTZR7

GND

1

RESET2

MR3 VCC

4

R216100

C2240.1UF

R1610.0K

DS1YELLOW LED

AC

TPH11

D1

LED RED

A C

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Debug Connectors (JTAG and NEXUS)

JTAG Standard 14-pin Connector

(RDY)

Place One CAPnext to eachconnector

ONCE Connector

(N/C)(TMS)

(JCOMP)

(GND)(GND)(GND)

(GND)

(TDI)(TDO)(TCLK)(EVTI)(RESET)(VREF)

TDITDOTCLK

(All JTAG reset pullups are on Reset Page)

(MSEO_0)(MSEO_1)

(MDO4)

(GND)

(GND)

(GND)

(GND)

(TMS)(TDI)(TDO)

(GND)

(GND)

(GND)

(GND)

(JCOMP)(RDY)(EVTI)(EVTO)

(GND)

(GND)

(MDO0)

(RST OUT)(RESET)

(GND)

(GND)

(GND)

(GND)

(MDO1)

(MDO2)(MDO3)

(MCKO)

(N/C)

(MDO5)(MDO6)

(MDO7)(MDO8)

(MDO9)(MDO10)

(MDO14)

(ARBREQ)(ARBGRT)

(MDO15)

(MDO13)(MDO12)(MDO11)

(GND)

(VREF)(TCK)

(CLKOUT)(TD/WT)

(DAI1)(DAI2)

Nexus

(bufferedreset TO MCU)

(bidirectionalMCU reset)

Note on EVTI:

EVTI is an optionalsignal. Although it issupported on the JTAGconnector, tools vendorsdo not normally use EVTIon non trace hardware.

EVTI is powered from VDD_HV_B whereas therest of the JTAG signalsare from VDD_HV_A. Inorder to use EVTI on theJTAG, connector,VDD_HV_A and HV_B shouldbe set to the samevoltage. Rather thanimpose this limitationfor all customers, azero ohm link has beenadded to allow EVTI tobe enabled on the JTAGconnector if required.

OptionalConfig

EVTI

TMS

NEXUS 50-pin Connector

NeusSpecificPullups all10K 0603

All of the signals used for JTAG (with theexception of EVTI, see note) are powered fromthe VDD_HV_A domain. All of the additionalsignals used for Nexus are powered fromVDD_HV_B.

If you are using Nexus, you need to ensure thatthe VDD_HV_A and VDD_HV_B domains are at thesame voltage as well as ensuring that theperipheral supplies PER_HVA and PER_HVB matchVDD_HV_A / B. See the MCU power page forconfiguration jumpers.

Voltage Domains:

EVTI

JCOMP

PH10

PC0PC1

PH10

PH9

DBUG-RSTx

PL9PL11

PL2PL3

PL4PL5

PL10PL6

PL7PL13

PL14PL15

PM0PM1

PM2PM7

PM10

PH9PH10PC0PC1JCOMP

PL8PL12DBUG-RSTx

PM8PM9

MCU-RSTx

JTAG-RSTx

MCU-RSTx

PL8

PM9PM8

PL12

PL9PL11PL2PL3PL4PL5PL10PL6PL7PL13PL14PL15PM0PM1PM2

PL12

PM7PM10PM9PM8

GND

GND GND

PER_HVA

PER_HVBPER_HVB

PH94

PC04PC14

JTAG-RSTx5

MCU-RSTx4,5

PL84

PH104

PL124

PL74

PL94PL114

PL24PL34

PL44PL54

PL104PL64

PL134

PL144PL154

PM04PM14

PM24PM74

PM104

PM94PM84

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


Debug Connectors (JTAG & Nexus)

6 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



6 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



6 16


R228

R247

R227

R2 0

DNP

R232

TPV11

R231

R230

R110.0K

R1510.0K

R236

R240

R226

R239

R235

P10

CON 2X25

13579

1113151719212325272931333537394143454749

2468101214161820222426283032343638404244464850

S1

S2

R238

P8

CON_2X7

1 23 4

657 89 10

11 1213 14

R3010.0K

R243

R19 0 DNP

R4110.0K

R242

R3 0

R246

C2047PF

DNP

R241

R237

C1747PF

DNP

R245

R225

R229

R4410.0K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(Enable)

CAN & LIN Physical

EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A

(LIN0_TX)(LIN0_RX)

(LIN1_RX)(LIN1_TX)

VDD - 5.0V input supply for CAN transceiver (4.5 to 5.5V)

VI/O - determines the signal level on MCU TX and RX pinsand can range from 2.8 to 5.5V

STB - High for Standby mode, pulled low for normal mode.

CAN1 Physical Interface

(CAN0_RX)(CAN0_TX)

(CAN1_RX)(CAN1_TX)

(TXD_0)

LIN MolexConnector

LIN1 Physical Interface

(040250V)

CAN0 Physical Interface

LIN MolexConnector

Master Mode Pullup EnableLIN0 Physical Interface

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(LEF = 20K Baud)

Total currentthrough resistors(LIN Bus at GND)= 12mA (0.144W)

Each resistor spec = 0.1W (0.2W total)

(Wake)

WAKE = GND ensures no spurious wakeups

(LEF = 20K Baud)

Total currentthrough resistors(LIN Bus at GND)= 12mA (0.144W)

Each resistor spec = 0.1W (0.2W total)

(Wake)(Enable)

EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A

(040250V)

Master Mode Pullup Enable

(060350V)

MC33662LEF LIN transceiver is newer version of 33661 offering:

- Full LIN compliance (33661 no longer compliant)- Improved ESD protection on LIN pin up to 15KV- Improved ESD on Wake and VSUP Pins- Other EMC and performance improvements

See freescale.com for more details

WAKE = GND ensures no spurious wakeups

BatteryReversepolarity &PulseProtection

BatteryReversepolarity &PulseProtection

All CAN and LIN signals arein power domain VDD_HV_A.

All interfaces will work at3.3V or 5.0V (PER_HVAjumper)

CAN termination resistorfootprint. Place onunderside of PCB

CAN termination resistorfootprint. Place onunderside of PCB

VDD - 5.0V input supply for CAN transceiver (4.5 to 5.5V)

VI/O - determines the signal level on MCU TX and RX pinsand can range from 2.8 to 5.5V

STB - High for Standby mode, pulled low for normal mode.

CAN0-CANLCAN0-S

PB0

LIN0-TX

PB1

PC10PC11

PB3PB2

PC7PC6

LIN0-RX

LIN0-LIN

CAN1_TX

CAN0_TX

CAN0_RX

LIN1-TX

LIN1-RX

LIN1-LIN

LIN0-VSUP

LIN1-VSUP

CAN0-CANH

CAN1-S

CAN1_RX CAN1-CANH

CAN1-CANL

PER_HVA

GND

GND

GNDGND

GND

GND

GNDGND

GND

GND

GNDGND

PER_HVA

GNDGND

GND

GND

PER_HVA5V0_SR

GND GND

PER_HVA5V0_SR

PB34PB24

PC74PC64

PC114

PB14PB04

PC104

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


CAN and LIN

7 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


CAN and LIN

7 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


CAN and LIN

7 16


R306 120DNP

C2560.1UF

D3 GF1AAC

U12

MC33901WEF

GN

D2

TXD1

RXD4

STB8

CANH7

CANL6

VDD

3

VIO

5

R59 4.70K

C2550.1UF

D201 GF1AA C

D200 GF1AA C

R25 2.0K

R249 2.0K

P14HDR_1X31

23

C2480.1UF

R221 2.0K

C2570.1UF

P9

CON PLUG 4

1234

C2341000pF

C2711uF

J121 23 4

J101 23 4

U10

MC33662LEF

RXD1

EN2

WAKE3

TXD4

GND5LIN6VSUP7INH8

R58 4.70K

J151 23 4

U6

MC33662LEF

RXD1

EN2

WAKE3

TXD4

GND5LIN6VSUP7INH8

C2491000pF

C2310.1UF

J131 2

C2540.1UF

TPV15

C2721uF

P15HDR_1X31

23

D2 GF1AAC

U11

MC33901WEF

GN

D2

TXD1

RXD4

STB8

CANH7

CANL6

VDD

3

VIO

5

J141 23 4

P11

CON PLUG 4

1234

J111 2

R248 2.0K

TPV16

R307 120DNP

C2731uF

C2701uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FTDI USB <-> Serial Interface- Self Powered mode. No power is taken from USB- Device efaults to Dual serial (RS232) mode ie RS232 on both A and B- Configurable I/O voltage on CHA / CHB via VDDIOA/B

Send Immediate / WakeupDisabled for CHB

Send Immediate / WakeupDisabled for CHA

Disable Receiver whenin USB suspend mode

USB RS232 (serial) Interface

(MCU_LIN2RX)(MCU_LIN2TX)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

FTDI Pin 40 (TXD)is Output fromFTDI Device,connect to MCU RXD

FTDI Pin 39 (RXD)is Input to FTDIdevice, connect toMCU TXD

All Signals are inpower domainVDD_HV_A.

FTDI interface willwork at 3.3V or 5.0V(PER_HVA jumper)

USB_N

BUS0BUS1BUS2BUS3BUS4BUS5

CLK_XTIN_6M

CLK_XTOUT_6M

USB_RNUSB_P USB_RP

FTDI_TXDFTDI_RXD PC8

PC9

5V0_SR

GND

GND

GND

GND

5V0_SR

GND

GND

5V0_SR

GND

GND

5V0_SR

GND

GND

PER_HVA

PER_HVA

PER_HVA

PC9 4PC8 4

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


USB RS232 Interface

8 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


USB RS232 Interface

8 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


USB RS232 Interface

8 16


C2610.033UF

R25510.0K

L201470OHMDNP

12

C2600.1UF

C2590.1UF

R252 10.0KR

661.

0MX16 MHZ

13

2

C2630.1UF

P18

HDR 2X3 DNP

1 23 4

65

12 3

4

+D-D

GV

P17

USB_TYPE_B

1

234

S1

S2

+ C2210UF

R253 10.0K

R69 27

C24

47PFDNP

C23

47PFDNP

R250 10.0KDNP

R251470

R68 27

C2580.1UF

R2564.70K

D2

D3D4

D1

D4BGX50A1

2

3

4

R254 10.0KJ16

1 23 4

C2620.1UF

R671.5K

U13

FT2232D

ADBUS024

ADBUS123

ADBUS222

ADBUS321

ADBUS420

ADBUS519

ADBUS617

ADBUS716

ACBUS015

ACBUS113

ACBUS212

ACBUS311

SI/WUA10

BCBUS030

BCBUS129

BCBUS228

BCBUS327

SI/WUB26

PWREN#41

3V3OUT6

USBDM8

USBDP7

RSTOUT#5

RESET#4

XTIN43

XTOUT44

EECS48

EESK1

EEDATA2

TEST47

AVC

C46

VCC

13

VCC

242

VCC

IOA

14

VCC

IOB

31

GN

D1

9

GN

D2

18

GN

D3

25

GN

D4

34

AGN

D45

BDBUS040

BDBUS139

BDBUS238

BDBUS337

BDBUS436

BDBUS535

BDBUS633

BDBUS732

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Adobe Acrobat Document

USB (Type A Host and Type AB OTG)

(10V0603lowESR)

(060350V)

Layout Note:Place caps &resistor asclose todevice aspossible

USB Power Switch

(USB1_DO)(USB1_D1)(USB1_D2)(USB1_D3)(USB1_D4)(USB1_D5)(USB1_D6)(USB1_D7)

(USB1_DIR)(USB1_STP)(USB1_NXT)

(USB0_DO)(USB0_D1)(USB0_D2)(USB0_D3)(USB0_D4)(USB0_D5)(USB0_D6)(USB0_D7)

(USB0_DIR)(USB0_STP)(USB0_NXT)

(Only available on BGA packages)

(Available on all packages)

(USB1_RST Active Low)

(060350V)

(12102KV)

USB Host, Type A

(35VTANT)

(35VTANT)

(12102KV)

(50V0402)

(16VTANT)

(35VTANT)

(040250v)

(16VTANT)

(Select 60MHz CLKOUTwith 24MHz XTAL)

(16VTANT)

(35VTANT)

(040250v)

(16VTANT)

(50V0402)

USB OTG Micro AB

(1/10W 0603)

(060350V)

(35VTANT) (0603

50V)(35VTANT)

(060350V)

(35VTANT)

(10V0603lowESR)

(10V0603lowESR)

(1/10W 0603)

(10V0603lowESR)

(USB0_RST Active Low)

(ID=GND for HOST mode)

(20K for HOST)

(Layout Note: Place SeriesTermination resistor closeto USB IC)

(Layout Note: Route DP and DM with90 Ohm Differential Pair. Keeptracks as short as possible)

(Layout Note: Route DP and DM with90 Ohm Differential Pair. Keeptracks as short as possible)

General Layout Note. Recommendation is to keep alltracks between MCU and USB PHI less than 3" Seeadditional SMSC Layout guidelines PDF to the right

(Layout Note: Place SeriesTermination resistor closeto USB IC)

(1K for OTG)

Layout Note:Place caps &resistor asclose todevice aspossible

Crystals areFOXSDLF/240F-20(20pF LoadCapacitance)

Crystals areFOXSDLF/240F-20(20pF LoadCapacitance)

USB Signalsare inpowerdomainVDD_HV_A

The USBinterfaceonly supports3.3Voperation.All I/Osignals mustbe 3.3V. IfVDD_HVA isset to 5V,USB MCU padsmust be leftas tri-state with nopullups.

USB_A_VDD1.8

USB_A_VDD3.3

PP15PP14PP13PP12PQ7PQ6PQ5PQ4

PQ2PQ0PQ3PQ1

USB_A_EN

USB_A_PWR

PI6

USB_B_EN

USB_B_EN

USB_B_DP

PI7

USB_A_EN

USB_A_VBUS

USB_A_DMUSB_A_DP

USB_B_PWR

USB_B_VBUS

USB_B_DPUSB_B_DM

USB_B_DM

USB_B_ID USB_B_ID

USB_A_DMUSB_A_5V

USB_B_5V

USB_A_DP

PG14PG15PE14PE15PG10PG11PH11PH12

PC3PI4PI5PC2

USB_B_VDD1.8

USB_B_VDD3.3

FLG_A

FLG_B

A_XOA_XI

B_XIB_XO

USB1_CLK

USB0_CLK

3V3_SRGND

5V0_SR

GND

5V0_SR

GND

GND

GND

GND GNDGND

GND

GND

GND GNDGND

GND

GND

GND

GND

GND

GND

3V3_SR

GND

5V0_SR

3V3_SR

GNDGNDGND

3V3_SR

3V3_SR

3V3_SR

GND

GND

PI64

PG154PE144PE154PG104PG114PH114PH124

PI44PI54PC24

PC34

PG144

PP144PP134PP124PQ74PQ64PQ54PQ44

PP154

PQ04PQ34PQ14

PQ24

PI74

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


USB Type A / Type AB

9 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



9 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



9 16


Y324MHZ

12

C16

33PF

R3310

R398.06K1%

+C23910UF

R36 20K

+

C51.0UF

C2141000pF

+C23010UF

+C24410UF

+

C212100UF

C13

33PF

TPV12

L3 26OHM1 2

C101000pF

C21000pf

Y424MHZ

12

R213100

+C20510UF

C191uF

+C24510UF

+

C91.0UF

C14

33PF

R271.0M

V D- D+ G

USB_TYPE_A_FEMALE

P5

S1

A1A2A3A4

S2

U7

USB83340

CPEN17

VBUS22

ID23

VBAT

_5V

21

DP18DM19

RESET27

NXT2

DIR31

STP29

CLKOUT1

VDD3V3_2020

VDD1V8_2828

XO25

REFCLK/XI26

VDD1V8_3030

RBIAS24

VDD

IO32

DATA713 DATA610 DATA5

9 DATA47 DATA36 DATA25 DATA14 DATA03

PAD

_GN

D33

SPK_L15 SPK_R16

REFSEL08

REFSEL111

REFSEL214

NC12

C2420.1UF

C2430.1UF

L4 26OHM1 2

R3210

R202100

C41000pF

U8

USB83340

CPEN17

VBUS22

ID23

VBAT

_5V

21

DP18DM19

RESET27

NXT2

DIR31

STP29

CLKOUT1

VDD3V3_2020

VDD1V8_2828

XO25

REFCLK/XI26

VDD1V8_3030

RBIAS24

VDD

IO32

DATA713 DATA610 DATA5

9 DATA47 DATA36 DATA25 DATA14 DATA03

PAD

_GN

D33

SPK_L15 SPK_R16

REFSEL08

REFSEL111

REFSEL214

NC12

U9

MIC2026-1YM

ENA1

FLGA2

FLGB3

ENB4

OUTB5

GND6

IN7

OUTA8

R4610.0K

C181uF

+C21610UF

P1

USB AB 5

VBU

S1

D-

2D

+3

ID4

GN

D5

SHELL16

SHELL27

SHELL38

SHELL49

R261.0M

+C24710UF

R37 1.0K

C2381uF

R4710.0K

R48 30

C2460.1UF

C15

33PF

R49 30

TPV13

C2061000pf

C2371uF

R388.06K1%

C11000pF

C2360.1UF

C2350.1UF

+

C8100UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Ethernet

Place Caps closeto connector

Series Termination Resistors:50 Ohms as per TI spec. Placeresistors as close to drivingsource as possible. Terminationrecommended for ALL MII signals

MCU OutputResistors Nextto MCU ondaughtercard

PHI OutputPlace Next toPHI

- Auto Negotiation Enable (All speeds / duplex supported) (AN_EN, AN0 and AN1 all Internal PullUP)

- Operating Mode (MII or RMII) (SNI_Mode Internal PullDown, MII_Mode control via jumper)

- LED Configuraiton (Mode1) (LED_CFG Internal PullUp)

- MDIX Enable (Auto MDIX Enabled) (MDIX_EN Internal PullUP)

- Physical Address (set to 0b00001) (PHYAD[0] Internal PullUp, PHYAD[1..4] Internal PullDown)

(MII_MODE)

Posn 1-2 for MII (default)Posn 2-3 for RMII

Pulse J1011F21PNL(Includes built intransformer)

Layout Note - Place Capsand Resistors close to PHI

(RMII Clock)

(RMII)

(RMII)(RMII)(RMII)(RMII)

(+MII)

(+MII)(+MII)

(+MII)

(RMII)(RMII)

(RMII)(RMII)

(+MII)(+MII)

(RMII)(+MII)

(RMII)(RMII)

(MII Clock)

(TANT)

Layout Note:Place 0.1uF cap closeto each pin. 10uFTANT as close to pin23 as possible

PFBOUTPFBIN2PFBIN1

50MHz Osc for RMII and 25MHz XTAL for MII

(TANT)

Reset Control:- Reset from MCU Reset Out (will reset with MCU)- Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in resetwhile reset config data can be driven onto pins to change mode etc.

Boot Configuration (using PHY internal Pulls)

MDIO Pullup

Layout Note:

MII Mode resistor (MII / RMII mode) and the MDIP ullup resistor should be placed as close aspossible to the PF15 / PF14 tracks to reduce the effect of a stub on the transmission line.

(TXD3)(TXD2)(TXD1)(TXD0)(TXEN)

(MDC)

(Termination on DC)(Termination on DC)(Termination on DC)(Termination on DC)(Termination on DC)

(Termination on DC)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(MDIO)

All Ethernet Signalsare in power domainVDD_HV_B

The Ethernet interface onlysupports 3.3Voperation. All I/Osignals must be 3.3V.If VDD_HVA is set to5V, Ethernet MCU padsmust be left astri-state with nopullups.

(50MHz OSCPower)

** See Layout Note(bottom right)

** Layout Note - Placeresistors as shownwith shared pad on PG1side of resistors

TXCLKPG1

PHY_50MHz

For RMII mode,remove resistorbetween PG1 andTXCLK and placebetween PG1 andPHY_50MHz

TDNTDP

RDN

LED_YLED_G

RBIAS

PA3PE12PA10PA11PF15PA9PA8PA7PE13

PG1

PF15

RDP

RST-OUTxRST-OUTx

X2

PHY_50MHz

PHY_25MHz

TXCLKPH2-RPH1-RPH0-R

RXDV

PFBOUTRXER

RXD1RXD0

CRS

PG13-RPG12-R

RXD3RXD2

COL

RXCLK

PG0-R

RMII_50MHZ

PFBOUT

PF14

PF14

PI11

CLKIN_X1

RMII_50MHZ

GND

3V3_SR

GNDGND

3V3_SR3V3_SR

GND

GND

GND

3V3_SR

GND

GND

3V3_SR

3V3_SR

GND

GND 3V3_SR

GND

GND

GND

3V3_SR

GND

3V3_SR

3V3_SR

PE134

RST-OUTx5,12

PG0-R4

PG14

PA74PA84PA94PF154PA114PA104PE124PA34

PF144

PI114

PG13-R4PG12-R4PH0-R4PH1-R4PH2-R4

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


Ethernet

10 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


Ethernet

10 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


Ethernet

10 16


R212.2K5%

R23349.91%

R220 1.5K

J51

2

3

J7

1

2

3

dp83848c

U5 10/100 single phy

RXCLK38

RSV

DPU

221

RSV

DPU

120

RSV

D5

12R

SVD

411

RSV

D3

10R

SVD

29

RSV

D1

8

RDN13RDP14

LEDACTCOL_ANEN28

IOVD

D33

_248

IOVD

D33

_132

IOG

ND

_247

IOG

ND

_135

DG

ND

36AV

DD

3322

AGN

D_2

15AG

ND

_119

TXD25

TXCLK1

LEDLINK_AN026

RXER_MDIXEN41

MDC31

RESET29

PWRDN_INT7

MDIO30

CRS_LEDCFG40

RXD3_PHYAD346

RXD2_PHYAD245

RXD1_PHYAD144

RXD0_PHYAD143

RXDV_MIIMODE39

TXEN2 TXD03

LEDSPEED_AN127

PFBIN237

TXD3_SNIMODE6

TXD14

RBIAS24

COL_PHYAD042

PFBIN118

PFBOUT23

X233 X134

TDN16TDP17

25MHZ_OUT25

C2000.1UF

C2280.1UF

J61 2

R5 50

C2250.1UF

Y225MHZ

21

R34 50

C2270.1UF

R28 50 C2330.1UF

L200120OHM

21

R21810.0K

+C24110UF

R42 50

R222270

C2320.1UF

R43 50

C2230.1UF

C211

33PF

C2290.1UF

R80 50 DNP

C110.1UF

R22449.91%

R219

2.2K 5%

R17 50

R24449.91%

R215 0

R223270

CLKOUT

VDD

GND

OE

50MHZ

Y1 42

31

+C240

10UF

C210

33PF

J81

2

3

C60.1UF

R20 50

P6 RJ45-8

TD+1

TD-2

CT_33

GND_44

GND_55

CT_66

RD+7

RD-8

YA9

YC10

GC

11

GA

12

GND1CG1

GND2CG2

R35 50

C2260.1UF

R184.87K

R292.2K

5%

R40 50

R23449.91%

R45 50

R308 0

TPV10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FlexRAY Physical Interface

FlexRAYdebugconnector

Decoupling Caps for BOTH IC's. Place next to power pins.

FlexRAY A

NormalEN STBN1

SleepGo to SleepRec Only 0

111

MODE

0 00

VBAT VBUF VCC VIO

(FR_A_TX)

(FR_A_RX)(FR_A_TX_EN)

(FR_B_TX)(FR_B_TX_EN)(FR_B_RX)

(FR_DBG0) (FR_DBG1)(FR_DBG2) (FR_DBG3)

FlexRAY B

(060350V)

(060350V)

(060350V)

(060350V)

Crimped lead - 279-9522Receptacle housing - 279-9156

Crimped lead - 279-9522Receptacle housing - 279-9156

(0603)

(0603)

(0603)

(0603)

(50V 0805)

(50V 0805)

Bus voltage +/- 12V (VBAT = 12v)Components spec'd for 12V operation

Bus voltage +/- 12V (VBAT = 12v)Components spec'd for 12V operation

All Signals are inpower domain VDD_HV_A.

FlexRAY interface willwork at 3.3V or 5.0V(PER_HVA jumper)

FRA-WAKE

FRA-INH1

PC5

FRA-JRXDPE2

FRA-BGE

PE3

FRA-JTXDFRA-JTXEN

FRA-BM FRA-DATA-BFRA-STBN

FRA-BP

FRB-INH2

PE4PC4

FRB-BGE

PE5

FRB-JTXDFRB-JTXENFRB-JRXD

FRB-BM FRB-DATA-BFRB-STBN

FRB-BP

FRB-EN

FRB-INH1

FRB-RXEN

FRB-DATA-A

FRB-ERRN

FRA-EN

FRB-WAKE

FRA-INH2

FRA-RXEN

FRA-DATA-A

FRA-ERRN

PC14PC12

PC15PC13

GND

GND

GND

GND

GND

PER_HVA 5V0_SR P12V

PER_HVA 5V0_SR P12V

GND

PER_HVA

P12V 5V0_SR PER_HVA

GND

GND

GND

PER_HVA

PC124PC144

PC154PC134

PC54PE24PE34

PE44PC44PE54

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



11 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



11 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



11 16


C20110PF

R200 10.0K

P4

DNP

1 23 4

J3

HDR 2X3

1 23 4

65

C2180.1UF

R20747.01%

TPV6

C2150.1UF

TPV9

+C209

10UF

U1

TJA1080TS/N

TRXD011

TRXD110

TXD5

TXEN6

BGE8

STBN9

EN3

WAKE15

INH21

INH12

BP18

BM17

RXD7

ERRN13

RXEN12

VIO

4

VCC

19

VBU

F20

VBAT

14G

ND

16

TPV3

R212 10.0K

R206 10.0K

TPV7

R20947.01%

C2130.1UF

R201 10.0K

R205 10.0K

+C217

10UF

TPV4

C20310PF

C2190.1UF

C20210PF

U2

TJA1080TS/N

TRXD011

TRXD110

TXD5

TXEN6

BGE8

STBN9

EN3

WAKE15

INH21

INH12

BP18

BM17

RXD7

ERRN13

RXEN12

VIO

4

VCC

19

VBU

F20

VBAT

14G

ND

16

TPV8

R203 10.0K

J11 23 45 67 8

R21047.01% C208

4700PFL2

DLW43SH

21

4 3

L1

DLW43SH

21

4 3

C2074700PF

R20847.01% P2

12

+C221

10UF

TPV2R211 10.0K

J21 23 45 67 8

+C222

10UF

R204 10.0K

J4

HDR 2X3

1 23 4

65

C20410PF

P312

TPV1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SAI Audio, AVB & TWRPI Connectors

(SAI0_DATA3)(SAI0_DATA2)(SAI0_DATA1)(SAI0_DATA0)(SAI0_BCLK)(SAI0_SYNC)(SAI0_MCLK)

(SAI1_DATA0)(SAI1_BCLK)

(SAI1_SYNC)(SAI1_MCLK)

(SAI2_DATA0)(SAI2_BCLK)(SAI2_SYNC)(SAI2_MCLK)

(I2C_SCL2)(I2C_SDA2)

(I2C_SDA3)(I2C_SCL3)(ENET0_TMR0)

Green - I2C ChannelsBlack - SAI Channels

Orange - ENET TMRx channels

(ENET1_TMR2)

(ENET0_TMR2)(GPIO Control)

Differences to RevCPin 17 was PH5, now PD13** (PH5 now routed to GPIO Matrix)Pin 27 was PH4, now PM4 (PH4 now routed to GPIO Matrix)Pin 45 was PH3, now PM3 (PH3 now routed to GPIO Matrix)

** Note PD13 is also routed to MLB header via DNP link

Pins used on this header are also at GPIO Matrix

PA12 - DSPI0_SIN (Also shared with TWRPI)PA13 - DSPI0_SOUT (Also shared with TWRPI)PA14 - DSPI0_SCK (Also shared with TWRPI)PA15 - DSPI0_SS0 (Also shared with TWRPI)

PG2 - DSPI3_SOUT (Also shared with User LED)PG3 - DSPI3_SS3 (Also shared with User LED)PG4 - DSPI3_SCLK (Also shared with User LED)PG5 - DSPI3_SIN (Also shared with User LED)

(DSPI0_SIN)(DSPI0_SOUT)(DSPI0_SCK)(DSPI0_SS0)(DSPI3_SOUT)(DSPI3_SS3)(DSPI3_SCK)(DSPI3_SIN)

I2C0_SCL

(DSPI0_SOUT)

(GPIO0/IRQ)(GPIO2)(GPIO4)

I2C0_SDA

(DSPI0_SIN)

(GPIO1)(GPIO3)

General Purpose TWRPI

TWRPI-ADC1

TWRPI-ID0

TWRPI-ADC0

TWRPI-ADC2

TWRPI-ID1

(ADC1_P[8])(ADC1_P[9])

(ADC1_P[10])

(ADC1_P[11])

(ADC1_P[12])

Note: PortsPD[4..8] areshared with theGPIO Matrix

(EIRQ31)Note: PortsPK[0..5] areshared with theGPIO Matrix

(DSPI0_SCK)(DSPI0_SS0)

RESET

SAI Audio and AVB

PF2PF3PF4PF5PF1PB10PF0

PJ2PJ3

PF7

PI14PJ1PJ0PI15

PE11PE10

PE9PE8

PF6

PA5

PD13

PM4

PM3

PA12PA13PA14PA15PG2PG3PG4PG5

PK0

PO0

PD6PD5

PD4

PK4

PA14

RST-OUTx

PA15PA13PA12

PK2PK3

PD5PD4

PD7

PD8

PO1

PK1

PO0

PK4PK1PK3

PD8

RST-OUTx

GND

3V3_SR

5V0_SR

GND

3V3_SR 3V3_SR

GND GND

5V0_SR 3V3_SR

GND GND

3V3_LR3V3_SR 3V3_SR

PF24PF34PF44PF54PF14PB104PF04

PE114

PJ34

PF74PE94PE84PI144PJ14PJ04

PJ24PE104

PI154

PF64

PA54

PD134,13,16

PM44,16

PM34,16

PA124,16PA134,16PA144,16PA154,16PG24,15,16PG34,15,16PG44,15,16PG54,15,16

PD74,16

PD64,16

PD84,16PD44,16PD54,16 PO0 4,16

PO1 4,16

PK0 4,16PK2 4,16

PK4 4,16PK1 4,16PK3 4,16

RST-OUTx5,10

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


SAI Audio, AVB & TWRPI Headers

12 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



12 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



12 16


R318 10.0KR31510.0K

R31610.0K R317 10.0K

P24

HDR_2X25

1 23 4

657 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

P25

HDR_10X2DNP

1 23 4

657 89 10

11 1213 1415 1617 1819 20

P27

CON_2X10

1 23 4

657 89 10

11 1213 1415 1617 1819 20

P26

CON_2X10

1 23 4

657 89 10

11 1213 1415 1617 1819 20

R314 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(MCK_IN)

(ID1)(MLBSIG)

(PWROFF)

Debug - Not RQD

(ID3)

(PS1)

(ID4)

(RSVD)

(STATUS)

(ID0)

(PS0)

47 Ohm seriesterminationalready onSMSCdaughtercard

Place resistors asclose as possible toMLB tracks tominimise stub lengths

(MLBCLK)

(RSOUT)

(MLBCP)

Parallel 100 ohm LVDS termination and Pullups/ Pulldopwns (DNP'd)are already on MLBdaughtercard.

(MLBSP)

(ERR/BOOT)

(MLBCN)

(MLBSN)

(RST)

(PD[15] Shared with MLB_DAT for 3-pin mode)

(PB[15] Shared with MLB_SIG for 3-pin mode)

(PI[8] Shared with MLB_CLK for 3-pin mode)

(12v)(3.3v Linear)

(3.3v)(3.3v)

(MLB_PWROFF)

(RSVD)

(SR0)

(RMCK)(SX0)

(I2C1_SDA)(SDA)

(RSVD)(RSVD)

(I2C1_SCL)(INT)

(MLBDP)

(SCLK)

(TDO/DINT)(TCK/DSCL)

(TDI/DSDA)(TMS)

(MLBDN)(ID2)(MLBDAT)

MLB (SMSC) Daughtercard Connector

Seriesterminationon MCUdaughtercard

Parallel terminationon MCUdaughtercard

CARD INTERRUPTING MCU (WKPU21)

Controls INIC Mode

Layout Note: MLB track lengths should be < 80mm(from MCU through daughter card to connector)

All MLB Signals are inpower domain VDD_HV_C.

The MLB interface onlysupports 3.3V operation.All I/O signals must be3.3V. If VDD_HVC is setto 5V, MLB MCU pads mustbe left as tri-state with no pullups.

PE1PE0

MLB_SN

MLB_CNMLB_CP

MLB_DPMLB_DN

MLB_SP

MLB_RSTOUT

MLB_CLK

MLB_MCKINPH6

MLB_SIG

MLB_DATMLB_DAT

MLB_SIG

MLB_SN

MLB_SP

MLB_DN

MLB_DP

MLB_CN

MLB_CP

MLB_CLK

PH7

PG9

PA6

MLB_PS1PI13MLB_STATUSMLB_PS0

PD13PI12

3V3_LR

GND

GND

GND

3V3_SR

P12V

3V3_SR

PH74

MLB_DAT4

MLB_SIG4

MLB_CLK4

MLB_SN4

MLB_SP4

MLB_DN4

MLB_DP4

MLB_CN4

MLB_CP4

PG94

PI134,16

PH6 4

PE1 4PE0 4

PA6 4

PD13 4,12,16PI12 4,16

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


MLB SMSC Daughtercard Connector

13 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



13 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



13 16


R62 0 DNP

R511.0K

R551.0K

R5247K

R53619.01%

R57619.01%

R50100DNP

R6510.0K

R5447K

R6410.0K

C2127PFDNP

R6310.0K

R60 0 DNP

TPV14

P16

QSH-020-01-L-D-DP-A

13

57

911

1315

1719

2123

2527

2931

3335

3739

24

68

1012

1416

1820

2224

2628

3032

3436

3840

4142

4344

TPV17

R61 0 DNP

R5647K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SD Connector

(SDHC_CLK)(SDHC_CMD)

(SDHC_DATA0)(SDHC_DATA1)(SDHC_DATA2)(SDHC_DATA3)

(35VTANT)

Amphenol 101-00565-64 SD/ MMC socket with carddetection switch.

The SD card specification details an operating voltage ofbetween 2.7 and 3.6V. If using the SD card, it can ONLY beused when VDD_HV_A (and PER_HVA) jumpers are set to 3.3V.Inserting an SD card with VDD_HV_A / PER_HVA set to 5V willresult in card damage.

Card Detect: Grounded when Card Inserted, Pulled high when card removedWrite Protect: Grounded when NOT protected, Pulled high when protected (or card removed)

(SDHC_CD) WKPU19(SDHC_WP)

Caution

(060350V)

PE6PE7

PI1

PI3PI2

SDHC1_CLKSD_DetectPA0SD_WPPH8

PI0

GND

GND

GND

3V3_SR

PE74

PH84PA04

PE64

PI34PI24PI14PI04

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


SD Card

14 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


SD Card

14 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


SD Card

14 16


R1210.0KDNP

R610.0K

R1010.0KDNP

R910.0KDNP

R22 0

R710.0K

C120.1UF

+C710UF

P200

MMC_SD_CARD

WP_SW1

CD_SW2

DAT13 DAT04

DAT75

GND/VSS26DAT6

7

CLK8

VCC/VDD9

VSS110DAT5

11

CMD12

DAT413 DAT314 DAT215

GND1S1

GND2S2

GND3S3

GND4S4

R1110.0KDNP

R810.0KDNP

R1310.0KDNP

R23 0R14 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

The LED's, Hex switches and push-button switches areconnected to MCU pads vvia zero ohm links. If desiredthese can be removed and direct connection made to theLED or switch. All of the ports used for LED's /Switches are also bonded out to the GPIO matrix

Hex Encoded Switch (Active High)

Switches are hard wired to 3.3V rather than 5V so it's not possible to drive 5V into a 3.3V pad (which would cause damage)Similarly, the LED's are active low with 3.3v supply so can be safely coupled to pads on either 3.3V or 5V domainsThe ADC input is limited to 3.3V, again to prevent driving 5V into a 3.3V pad which would cause damage

PG[2..5] share eMIOS1UC[11..14] with PWMfunctionality

(eMIOS H / X)(eMIOS G / X)(eMIOS G / Y)(eMIOS G)

User Pushbutton Switches (Active High)

User Peripherals, Audio Controls and GPIO

LED's are SMD (1206) Yellow

User LED's (Active Low)

OMRON B3WN-6002 Pushbutton Switch

Since the Hex switch alwayshas an active output, thejumper is to allow the switchto be powered off

ADC Input Pot and Test Point

(Note - This is run from linear 3.3v regulator toprovide a stable input voltage)

(ADC1_P[0])

(0603 50V)

Note - PA1 is also the NMI pin!

Note that LED2 and LED4 (PG3and PG5) can be controlled inLPU_RUN mode (and also have padkeepers in LPU_STANDBY)

PB_SW1PB_SW2

USR_LED4

PB_SW3PB_SW4

USR_LED2USR_LED1

USR_LED3

PA1PA2PF9PF11

HEX_SW1

HEX_SW2

HEX_SW3

PD0

PD1

PD2

PD3HEX_SW4

PG2PG3PG4PG5

PB4

GND

3V3_SR

3V3_SR

3V3_SR

GND

3V3_LR

GND

GND

PG24,12,16PG34,12,16PG44,12,16PG54,12,16

PA2 4,16PF9 4,16PF11 4,16

PD1 4,16

PD2 4,16

PD3 4,16

PD0 4,16

PA1 4,16

PB4 4

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



15 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



15 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B



15 16


R277 0

DS3AC

R257 270

R286

100

DS8AC R269 270

R275 0

R278 10.0K

R262 0

R258 0

C25 0.1UF

DNP

R290 10.0K

SW3

1 2

RV1 2K13

2

R287 0R289 0

P22HDR 1X4DNP

1 2 3 4

R261 270

P20HDR 1X4DNP

1 2 3 4

DS7AC

R301 10.0K

R304 0

R276 10.0K

DS2AC

R282 0

R303 10.0K

TP18

1

R281 10.0K

R280 0

P19HDR 1X4DNP

1 2 3 4

R260 0

R259 270

SW6

1 2

R270 0

SW4

1 20

351

246

789A

B C DE

F

SW2

DRS4016

C1

2

8

4

R302 0

R288 10.0K

J2612

SW7

1 2

R279 10.0K

J1712

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

All pads are DNP (Do Not Populate) 0.1" pitch headers placed on a 0.1" gridGPIO Pin MatrixPORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH

PORTQ

Layout Notes: Pads must be placed in a 13 x 16 matrix pattern, 2.54 mm pitch - 13 wide (one column for each port EXCLUDING those with no available pads ie C, E, H, Q) - 16 tall (1 row for each port number from 0 to 15). - GND pad at bottom of each colum - After production, pads should be through hole (not solder filled)

No spare pinson PortQ

No spare pinson PortE

PORTI PORTJ PORTK PORTL PORTM PORTN PORTO PORTP

No spare pinson PortE

Busses are not usedon ports as it makesit harder to seewhich pins are sharedwith other functions

14 GND Pads(one atbottom ofeach colum)

PD[0..3] shared withHex Switch

PD[4..8] shared with TWRPI connector withpullup on PD[7], PD[8]

PA[1,2] shared with user switches

PA[12..15] shared with SAI Audio and TWRPI

PD[13] shared with SAI Audio and MLBheaders

PI[12,13] shared withMLB header

PK[0..4] shared withTWRPI header

PF[9,11] shared withuser switches

PG[2..5] shared withuser LED's, SAI andTWRPI headers

PM[3..4] shared withSAI Audio header

PO[0..1] shared withTWRPI header

PK0PK1

PK3PK2

PK4

PK7PK8PK9

PK11PK10

PK12PK13PK14PK15

PL0PL1

PI9

PI10

PI12

PI13

PJ4

PJ9

PJ11

PJ10

PJ12

PJ15

PK0

PK1

PK3

PK2

PK4

PK7

PK8

PK9

PK11

PK10

PK12

PK13

PK14

PK15

PL0

PL1

PM3

PM4

PM5

PM6

PM11

PM12

PM13

PM14

PM15

PN0

PN1

PN3

PN2

PN4

PN5

PN7

PN6

PN8

PN9

PN11

PN10

PN12

PN15

PO0

PO1

PO3

PO2

PO4

PO5

PO7

PO6

PO8

PO9

PO11

PO10

PO12

PO13

PO14

PO15

PP0

PP1

PP3

PP2

PP4

PP5

PP7

PP6

PP8

PP9

PP11

PP10

PA1

PA2

PA4

PA12

PA13

PA14

PA15

PB5

PB7

PB6

PB11

PB12

PD0

PD1

PD3

PD2

PD4

PD5

PD7

PD6

PD8

PD9

PD11

PD10

PD12

PD13

PF8

PF9

PF11

PF10

PF12

PF13

PG3

PG2

PG4

PG5

PG7

PG6

PG8

PA1PA2PA4

PG3PG2

PG4PG5

PG7PG6

PG8

PA12PA13PA14PA15

PI9PI10

PI12PI13

PB5

PB7PB6

PB11PB12

PF8PF9

PF11PF10

PF12PF13

PJ4

PJ9

PJ11PJ10

PJ12

PJ15

PN13

PN14

PJ13

PJ13PJ14

PJ14

PK5

PK6

PK5PK6

PD0PD1

PD3PD2

PD4PD5

PD7PD6

PD8PD9

PD11PD10

PD12PD13

PM3PM4PM5PM6PM11PM12PM13PM14PM15

PN0PN1

PN3PN2

PN4PN5

PN7PN6

PN8PN9

PN11PN10

PN12

PN15

PN13PN14

PO0PO1

PO3PO2

PO4PO5

PO7PO6

PO8PO9

PO11PO10

PO12PO13PO14PO15

PP0PP1

PP3PP2

PP4PP5

PP7PP6

PP8PP9

PP11PP10

PJ5

PJ6

PJ7

PJ8

PJ5PJ6PJ7PJ8

PH15

PH14

PH13

PH13PH14PH15

PH3PH4PH5

PH5

PH4

PH3

GND

PJ44

PJ94PJ104PJ114PJ124

PJ154

PK04,12PK14,12PK24,12PK34,12PK44,12

PK74PK84PK94PK104PK114PK124PK134PK144PK154

PL04PL14

PA14,15PA24,15PA44PA124,12PA134,12PA144,12PA154,12

PB54PB64PB74PB114PB124

PI94PI104

PI124,13PI134,13

PJ134PJ144

PK54PK64

PD04,15PD14,15PD24,15PD34,15PD44,12PD54,12PD64,12PD74,12PD84,12PD94PD104PD114PD124PD134,12,13

PJ54PJ64PJ74PJ84

PG2 4,12,15PG3 4,12,15PG4 4,12,15PG5 4,12,15PG6 4PG7 4PG8 4

PF8 4PF9 4,15PF10 4PF11 4,15PF12 4PF13 4

PM3 4,12PM4 4,12PM5 4PM6 4PM11 4PM12 4PM13 4PM14 4PM15 4

PN0 4PN1 4PN2 4PN3 4PN4 4PN5 4PN6 4PN7 4PN8 4PN9 4PN10 4PN11 4PN12 4PN13 4PN14 4PN15 4

PO0 4,12PO1 4,12PO2 4PO3 4PO4 4PO5 4PO6 4PO7 4PO8 4PO9 4PO10 4PO11 4PO12 4PO13 4PO14 4PO15 4

PP0 4PP1 4PP2 4PP3 4PP4 4PP5 4PP6 4PP7 4PP8 4PP9 4PP10 4PP11 4

PH13 4PH14 4PH15 4

PH3 4PH4 4PH5 4

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


GPIO Pin Matrix

16 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


GPIO Pin Matrix

16 16



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 D1


B


GPIO Pin Matrix

16 16


TPH10

1

IOM921

IOM401

IOM1181

IOM1011

IOM11

IOM721

IOM451

IOM561

IOM181

IOM441

TPH7

1

IOM1111

TPH4

1IOM17

1

IOM701

IOM761

IOM771

IOM391

IOM1021

IOM1311

IOM841

IOM331

IOM71

IOM1241

IOM971

IOM151

IOM961

IOM131

IOM291

IOM991

TPH15

1

IOM191

IOM501

IOM101

IOM811

TPH121

IOM581

IOM91

IOM1261

IOM541

IOM881

IOM1281

IOM981

IOM431

IOM261

IOM521

IOM1051

IOM651

IOM241

IOM1041

TPH9

1

IOM461

IOM671

IOM481

IOM911

IOM61

IOM211

IOM891

IOM1231

IOM51

TPH6

1

IOM1031

IOM731

IOM281

TPH3

1

IOM1091

IOM621

IOM631

IOM1151

IOM411

IOM41

IOM531

IOM851

IOM1191

IOM1061

IOM901

IOM321

IOM951

IOM161

IOM341

IOM831

IOM601

IOM1081

IOM511

IOM141

IOM821

IOM871

TPH14

1

IOM81

IOM1161

IOM271

IOM381

IOM801

IOM351

TPH11

1

IOM1211

IOM491

IOM1101

TPH8

1

IOM1291

IOM311

IOM21

IOM1121

IOM781

IOM791

IOM1071

IOM251

IOM691

IOM751

IOM1301

IOM931

IOM941

IOM1321

IOM421

IOM371

IOM1141

IOM591

TPH5

1

IOM301

IOM1251

IOM201

IOM471

IOM641

IOM121

TPH2

1

IOM31

IOM1271

IOM1001

IOM1171

IOM1131

IOM361

IOM711

IOM111

IOM611

IOM681

IOM1221

IOM661

IOM571

TPH13

1

IOM551

IOM741

IOM231

IOM861

IOM221

IOM1201

324 BGA DC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

X5

Freescale AISG Applications, East Kilbride

X2X3X4

Revision InformationDesigner CommentsRev Date

GPIO - MPC5748G GPIO pins 1 of 2

Clocks

Sheet 8

Sheet 2Sheet 3Sheet 4Sheet 5Sheet 6Sheet 7


Table Of Contents:

MPC5748G Customer EVB 324 BGA Daughter Card (MPC574XG-324DS)

X1Power - MPC5748G power pins footprintPower - MPC5748G Decoupling Capacitors

Daughtercard ConnectorsBus Termination

28 Feb 2013 Alasdair Robertson Initial release sent for review

These schematics are provided for reference purposes only. As such,Freescale does not make any warranty, implied or otherwise, as to thesuitability of circuit design or component selection (type or value) used inthese schematics for hardware design using the Freescale MPC5748G familyof Microprocessors. Customers using any part of these schematics as abasis for hardware design, do so at their own risk and Freescale does notassume any liability for such a hardware design.



Caution:

Notes:- All components and board processes are to be ROHS compliant- All small capacitors are 0402 unless otherwise stated- All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated- All jumpers are denoted Jx. Jumpers are 2mm pitch- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2. 2 Pin jumpers generally have the "source" on pin 1.- All switches are denoted SWx- All test points are denoted TPx- Test point Vias are denoted TPVx

Alasdair RobertsonVersion sent to Pre Layout, incorporating fixes from reviewFinal Review11 Mar 2013

13 Mar 2013 Alasdair Robertson15 Mar 2013 Alasdair Robertson Component consolodation, Few minor changes. Sent to Layout

3 Different test points used in design:

TPVx - Through Hole Pad small

TPHx - Through Hile Pad Large (for standard 0.1" header).

TPX - Surface Mount Wire Loop

Alasdair Robertson Post Layout (Back Annotated). Matches PCB RevA

Changes made during layout to Daughtercard ConnectorsAlasdair Robertson

A

29 Mar 2013Alasdair Robertson CIS CAD Database update & SCH Back-Annotate15 Apr 2013X6

15 Apr 2015A1 18 Aug 2015 Alasdair Robertson Tidy up Schematics for UM (RevA PCB)

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27900 PDF: SPF-27900 A1

MPC5748G 324 BGA Daughter Card

B

Tuesday, August 18, 2015


A. Robertson

A. Robertson

A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27900 PDF: SPF-27900 A1


B



A. Robertson

A. Robertson

A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27900 PDF: SPF-27900 A1


B



A. Robertson

A. Robertson

A. Robertson

1 8


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Individual MCUsupply controljumpers

3v3

Default Configuraiton:- ALL MCU supply voltages are set to 3.3V (ADC0, ADC1, VDD_HV_A,VDD_HV_B, VDD_HV_C, VBallast)- VDD_HV_FLA = External 3.3V supplied (jumper fitted)- VDD_LV Supplied from ballast transistor

This is not necessarily the same as the default shown in the RM. AllVDD_HV_x domains have at least one peripheral that only functions at3.3V. Therefore the default is to run these from 3.3V. The analogue pinscan only be driven to the same voltage as the VDD_HV_x domain they aresituated in (ie max 3.3V) so makes sense for the analogue supply andreference to be 3.3V

Ground Links(0 OhmResistors)

DAC ExternalRef VoltageSelect

3v3 5v0 5v0 5v0 5v0 5v03v3 3v3 3v33v3

3v3 5v0

(Current Limit Resistor toprotecxt against case whenother MCU supplies aredisconnected and externalreference supply is live)

MPC5748G MCU Power ConnectionsCaution:

- If VDD_HV_A is driven from 5V, the VDD_HV_FLA pinmust not be supplied from 3.3V (remove the HVA_FLAjumper)

- Don't attempt to over drive an analogue pad to 5Vwhen the digital VDD_HV_x supply is set to 3.3V. Thiswill trigger the ESD protectrion on that pad. Forexample if VDD_HV_A is set to 3.3V and the analoguesupplies are set to 5V, you cannot drive 5V into apad in the VDD_HV_A domainFrom MCU

supplyjumpers onmain board

MCU_3V3_S

MCU_5V0_S

MCU_1V25_L

MCU_3V3_L

MCU_5V0_L

HVB

_CAP

HVC

_CAP

HVF

LA_C

AP

LV_C

AP

ADC

0_C

AP

ADC

1_C

AP

ADC

1REF

_CAP

ADC0_GND ADC1_GND GND

HVA

_CAP

GNDADC0_GND GNDADC1_GND

E_C

AP

B_C

AP

LVD

EC_C

AP

HVA

_CAP

GND GND

MCU_1V25_L8

MCU_5V0_S8

MCU_3V3_S8

MCU_5V0_L8

MCU_3V3_L8

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G MCU Power

2 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G MCU Power

2 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G MCU Power

2 8


J11

1

2

3

Q20MJD31CT4

34

1

J3

1

2

3

J10

1

2

3

R10 0

J7

1

2

3

TPH21

J5

1

2

3

TPH3

1

TPH1

1

J6

1

2

3

J4

1

2

3

R361.0K

1.25v Core & External BallastAnalogue MPC5748G 6M 324BGAPackage 2of3 Power Pins

Flash

DAC Ref

U1B

MPC5748G + OTB-324R-1.0-019-00

VRC

_CTR

LK2

VSS_

LV_F

6F6

VSS_

LV_J

7J7

VSS_

LV_J

8J8

VSS_

LV_J

9J9

VSS_

LV_K

7K7

VSS_

LV_K

8K8

VSS_

LV_K

9K9

VSS_

LV_K

10K1

0

VSS_

LV_L

7L7

VSS_

LV_L

8L8

VSS_

LV_L

9L9

VSS_

LV_L

10L1

0

VSS_

LV_M

7M

7

VSS_

LV_M

8M

8

VSS_

LV_M

9M

9

VSS_

LV_M

10M

10

VDD

_LV_

D8

D8

VDD

_LV_

F5F5

VDD

_LV_

K3K3

VDD

_LV_

K11

K11

VDD

_LV_

K12

K12

VDD

_LV_

L11

L11

VDD

_LV_

L12

L12

VDD

_LV_

M11

M11

VDD

_LV_

M12

M12

VDD

_HV_

A_C

2C

2

VDD

_HV_

A_C

9C

9

VDD

_HV_

A_R

7R

7VD

D_H

V_A_

E18

E18

VDD

_HV_

A_K1

7K1

7

VDD

_HV_

A_U

8U

8

VDD

_HV_

B_J1

5J1

5

VDD

_HV_

B_K1

3K1

3

VDD

_HV_

CL1

4

VSS_

HV_

ADC

0U

14VD

D_H

V_AD

C0

V14

VDD

_HV_

ADC

1V1

6VS

S_H

V_AD

C1

V17

VDD

_HV_

FLA

J2

VDD

_HV_

ADC

1_R

EFV1

5

VSS_

HV_

H7

H7

VSS_

HV_

H8

H8

VSS_

HV_

H9

H9

VSS_

HV_

H10

H10

VSS_

HV_

H11

H11

VSS_

HV_

H12

H12

VSS_

HV_

J10

J10

VSS_

HV_

J11

J11

VSS_

HV_

J12

J12

VSS_

HV_

K14

K14

VSS_

HV_

K16

K16

VSS_

HV_

V8V8

VIN

1_C

MP_

REF

J3

VDD

_LP_

DEC

L2

VSS_

HV_

VPP

K1

R9 0

R7 0

J8

12

R350

J9

1

2

3

R24 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Capacitor Types:

470pF - Ceramic COG, 50v 5% 04021000pF - Ceramic COG, 50V 5% 04024700pF - Ceramic X7R, 50V 10% 0402

0.01uF - Ceramic X7R, 50V 10% 04020.1uF - Ceramic X7R, 16V 10% 04020.68uF - Ceramic X7R 16V 10% 0805 (Murata GCM219R71C684KA37 )1.0uF - Ceraminc X7R, 10V 10% 0603 (Taiyo Yuden LMK107B7105KA-T)2.2uF - Ceraminc X7R, 10V, 10%, 0603 (Taiyo Yuden LMK107B7225KA-TR) 4.7uF - TANT, 12.5V 20% ESR=0.08R 734310uF - TANT, 35V 10% ESR=0.125R CC7343-31

4.7uF Alternative (150-78844)- Polymer ALU, 16V 20% ESR=0.08R 7343-18

Place small Caps as close as possible to MCU pins

ADC

Place small caps close to each MCU pin

VDD_HVA VDD_HVB VDD_HVC

VDD_LV

See caps below for Bypass Transistor bulk storage (some on VDD1V2 rail)

VDD_LV (1.25V) Decoupling. Place one of the non DNP caps each side of the deviceas close as possible to pin. Distribute other (DNP) caps around rest of pins

Ballast Transistor

Flash

MPC5748G MCU Decoupling and bulk storage

LP Internal Reg Cap

Placeclose totransistor

Place one 0.68uF cap footprinteach side of package

Place 10uF cap to west side of package

(low ESR)

(lowESR)

(lowESR)

(Murata GCM219R71C684KA37)

(lowESR)

(lowESR)

(lowESR) (low

ESR)(low ESR)

2.2uF capsare DNP.Place closeto emitter One of these is DNP. May replace 2 caps with

0.47uF to keep overall capacitance within limits

ADC0_CAP

ADC0_GND

ADC1REF_CAP

ADC1_GND

ADC1_CAP

ADC1_GND

GND

HVA_CAP

GND

HVB_CAP

GND

HVC_CAP

LV_CAP

GND

HVFLA_CAP

GND

LV_CAPB_CAP E_CAP

GND

LVDEC_CAP

GND

E_CAP

GND

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G MCU Decoupling

3 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B



3 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B



3 8


C510.1UFDNP

C260.1UF

C421000pF

C300.1UF

C48

1000pF

C610.68uF

C40470pF

C240.1UF

C500.1UF

C591.0 UF

C440.1UF

C250.1UFDNP

C320.1UF

C342.2UFLMK107B7225KA-T

C530.1UF

C290.68uF

C460.1UFDNP

C431uFLMK107B7105KA-T

C350.1UF

C102.2UFDNP

C28470pF

C331000pF

C521000pF

C491000pF

C230.1UF

C200.68uFDNP

C570.1UF

C390.1UF

+ C410UFDNP

C551000pF

C581.0 UF

C560.1UF

+ C110UF

C540.1UF

C36

1000pF

C471000pF

C92.2UFDNP

+C210UFDNP

C601.0 UF

C8 4700pF

C380.1UF

+C310UFDNP

C410.1UF

C310.68uF

C27470pF

C210.1UFDNP

C22470pF

+ C510UFDNP

C371000pF

C450.1UFDNP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MPC5748G GPIO 1 of 2

Key to text colours:Purple - Comms Physical Interfaces

Blue - Debug (JTAG & Nexus)

(LIN0_RX)(LIN0_TX)

(LIN1_TX)(LIN1_RX)

(XTAL32)(EXTAL32)

(FR_A_TX)

(FR_A_TX_EN)(FR_A_RX)

(FR_B_TX_EN)

(FR_B_RX)(FR_B_TX)

(USB1_CLK)

(USB1_D0)(USB1_D1)

(USB1_D2)(USB1_D3)

(USB1_D4)(USB1_D5)

(USB1_D6)(USB1_D7)

(USB1_DIR)

Orange - Other Peripherals and I/O

(RMII_RXD0)(RMII_RXD1)(MII_RXD2)

(MII_RXD3)(MII_CRS)

(RMII_TXD0)(RMII_TXD1)

(MII_TXD2)(MII_TXD3)

(RMII_TXEN)

(RMII_MDC)(RMII_TXCLK)

(RMII_RXDV)(RMII_MDIO)

(RMII_RXER)(MII_COL)

(MII_RXCLK)

(FR_DBG0)(FR_DBG1)(FR_DBG2)(FR_DBG3)

(SD_CMD)(SD_CLK)

(SD_WP)

(SAI0_D0)(SAI0_D1)(SAI0_D2)(SAI0_D3)(SAI0_BCLK)(SAI0_MCLK)

(SAI0_SYNC)


(TDI)(TDO)

(TCK)(TMS)

Black - Clock, Reset and Control

(MLB_DN)

(MLB_DP)

(MLB_SN)

(MLB_SP / DAT)

(MLB_CN / SIG)

(SAI_I2C2_SCL)(SAI_I2C2_SDA)

(SAI_I2C3_SDA)(SAI_I2C3_SCL)

(MLB_I2C1_SCL)(MLB_I2C1_SDA)

Green - I/O Matrix (dedicated)

(CMP1_8 / IO)

(CMP1_10 / IO)

(CMP1_11 /IO)

(CMP1_12 / IO)

(CMP1_13 / IO)

(CMP1_14 / IO)(CMP1_15 / IO)

(CLKOUT1 GPIO)

(GPIO)

(GPIO)

(HEX1 & GPIO)(HEX2 & GPIO)(HEX3 & GPIO)(HEX4 & GPIO)

(SW1 & GPIO**)(SW2 & GPIO)

(LED1 & GPIO)(LED2 & GPIO)(LED3 & GPIO)(LED4 & GPIO)

(MLB_RST)(MLB_PWR)

(MLB_IRQ - WKPU21)

** PA1 is also NMI. Routedto I/O Matrix

RED - I/O Matrix and other functions (eg LED)

(CLKOUT0 GPIO)

(eMIOS1_UC_5H)(eMIOS1_UC_6H)(eMIOS1_UC_7H)

(ADC_POT)(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(CAN0_TX)(CAN0_RX)

(SW4 & GPIO)

(CAN1_RX)(CAN1_TX)

(SW3 & GPIO)

(RS232_RX)(RS232_TX)

(SD_CD - WKPU19)

(GPIO)(GPIO)(GPIO)

(eMIOS E1UC_11_H)(eMIOS E1UC_12_H)(eMIOS E1UC_13_H)(eMIOS E1UC_14_H)

(WKPU2 / NMI0)(WKPU3)

WKPU22

WKPU15

(SAI_GPIO)(MLB_GPIO)

(GPIO & MLB_ST)

PA0PA1

PA3PA2

PA4PA5

PA7PA6

PA8PA9

PA11PA10

PA12PA13

PA15PA14

PB0PB1

PB3PB2

PB4PB5

PB7PB6

PB8PB9

PB11PB10

PB12PB13

PB15PB14

PC0PC1

PC3PC2

PC4PC5

PC7PC6

PC8PC9

PC11PC10

PC12PC13

PC15PC14

PD0PD1

PD3PD2

PD4PD5

PD7PD6

PD8PD9

PD11PD10

PD12PD13

PD15PD14

PE0PE1

PE3PE2

PE4PE5

PE7PE6

PE8PE9

PE11PE10

PE12PE13

PE15PE14

PF0PF1

PF3PF2

PF4PF5

PF7PF6

PF8PF9

PF11PF10

PF12PF13

PF15PF14

PG0PG1

PG3PG2

PG4PG5

PG7PG6

PG8PG9

PG11PG10

PG12PG13

PG15PG14

PH0PH1

PH3PH2

PH4PH5

PH7PH6

PH8PH9

PH11PH10

PH12PH13

PH15PH14

MCU-EXTALMCU-XTAL

PORSTxMCU-RSTx

PH0 7

PORSTx8MCU-RSTx8

MCU-EXTAL6MCU-XTAL6

PB08PB18PB28PB38



PA118PA128PA138PA148PA158


PA58


PB58PB48

PC118PC128PC138PC148PC158


PC58PC48

PC08PC18PC28PC38

PD118PD128PD138PD147PD157


PD58PD48

PD08PD18PD28PD38

PH1 7PH2 7PH3 8PH4 8PH5 8PH6 8PH7 8PH8 8PH9 8PH10 8PH11 8PH12 8PH13 8PH14 8PH15 8

PG0 7PG1 8PG2 8PG3 8PG4 8PG5 8PG6 8PG7 8PG8 8PG9 8PG10 8PG11 8PG12 7PG13 7PG14 8PG15 8

PF0 8PF1 8PF2 8PF3 8PF4 8PF5 8PF6 8PF7 8PF8 8PF9 8PF10 8PF11 8PF12 8PF13 8PF14 8PF15 8

PE0 8PE1 8PE2 8PE3 8PE4 8PE5 8PE6 8PE7 8PE8 8PE9 8PE10 8PE11 8PE12 8PE13 8PE14 8PE15 8

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G GPIO 1of2

4 8


MPC5748G 324 BGAPackage 1of3 GPIO Pins1

U1A

MPC5748G + OTB-324R-1.0-019-00

PB0N1

PB1N2

PB2G9

PB3G8

PB4N11

PB5R14

PB6N12

PB7P14

PB8/XTAL32V10

PB9/EXTAL32V9

PB10P9

PB11P13

PB12N13

PB13T18

PB14R17

PB15R18

PC0F9

PC1F10

PC2C13

PC3D11

PC4B12

PC5A11

PC6R3

PC7U2

PC8D5

PC9D4

PC10M5

PC11M4

PC12D6

PC13E6

PC14B2

PC15C3

PD0R12

PD1T13

PD2T14

PD3R13

PD4P11

PD5T15

PD6U15

PD7R15

PD8P12

PD9N15

PD10P15

PD11V18

PD12N16

PD13N14

PD14T17

PD15P17

PE0H3

PE1H2

PE2A12

PE3D10

PE4B11

PE5A10

PE6F8

PE7D7

PE8K5

PE9K4

PE10H1

PE11J1

PE12C18

PE13G17

PE14C15

PE15E12

PF0N9

PF1R9

PF2P10

PF3U10

PF4N10

PF5V12

PF6T11

PF7R10

PF8T2

PF9T1

PF10R5

PF11P5

PF12N5

PF13N6

PF14G18

PF15H17

PG0H18

PG1J16

PG2J4

PG3J5

PG4G2

PG5F2

PG6M2

PG7M1

PG8M3

PG9L3

PG10D14

PG11D13

PG12L18

PG13M18

PG14F12

PG15C16

PH0L17

PH1K18

PH2J18

PH3J17

PH4C10

PH5B10

PH6A9

PH7D9

PH8E8

PH9E9

PH10E10

PH11C14

PH12D12

PH13F3

PH14E2

PH15G4

RESETL1

PORSTC12

XTALV6

EXTALV7

PA0L5

PA1K6

PA2J6

PA3M17

PA4P6

PA5A14

PA6A13

PA7F17

PA8F18

PA9E17

PA10D18

PA11D17

PA12N8

PA13P7

PA14T3

PA15N7

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


(USB1_NXT)(USB1_STP)

(USB0_CLK)

(USB0_D0)(USB0_D1)(USB0_D2)(USB0_D3)

(USB0_D4)(USB0_D5)(USB0_D6)(USB0_D7)(USB0_NXT)(USB0_DIR)

(USB0_STP)

(SD_D3)(SD_D2)(SD_D1)(SD_D0)

(SAI1_D0)(SAI1_BCLK)

(SAI2_D0)

(SAI2_BCLK)

(SAI2_MCLK)

(SAI2_SYNC)

(MDO0)(MDO1)(MDO2)(MDO3)(MDO4)(MDO5)

(MDO6)(MDO7)(MDO8)

(MDO9)(MDO10)(MDO11)

(MDO12)(MDO13)(MDO14)(MDO15)

(EVTI)(MSEO0)

(MSEO1)(MCKO)

(EVTO)

(MLB_CP / CLK)(GPIO)(GPIO)

(GPIO)

(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)




(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)


(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)



Purple - Comms Physical InterfacesKey to text colours:





(USB1_RST)(USB0_RST)

(ENET_RST)(GPIO & MLB_PS0)(GPIO & MLB_PS1)

PI0PI1

PI3PI2

PI4PI5

PI7PI6

PI8PI9

PI11PI10

PI12PI13

PI15PI14

PJ0PJ1

PJ3PJ2

PJ4

PJ7PJ6

PJ8PJ9

PJ11PJ10

PJ12PJ13

PJ15PJ14

PK0PK1

PK3PK2

PK4PK5

PK7PK6

PK8PK9

PK11PK10

PK12PK13PK14

PL0PL1

PL3PL4PL5

PL7PL6

PL8PL9

PL11PL10

PL12PL13

PL15PL14

PM0PM1

PM3PM2

PM4PM5

PM7PM6

PM8PM9

PM11PM10

PM12PM13

PM15PM14

PN0PN1

PN3PN2

PN4PN5

PN7PN6

PN8PN9

PN11PN10

PN12PN13

PN15PN14

PO0PO1

PO3PO2

PO4PO5

PO7PO6

PO8PO9

PO11PO10

PO12PO13

PO15PO14

PP0PP1

PP3PP2

PP4PP5

PP7PP6

PP8PP9

PP11PP10

PP12PP13

PP15PP14

PK15

PL2

PQ1

PQ3PQ2

PQ4PQ5PQ6

PJ5

PQ7

PQ0

PI118PI128PI138PI148PI158


PI58


PJ118PJ128PJ138PJ148PJ158


PJ58


PK118PK128PK138PK148PK158


PK58


PL118PL128PL138PL148PL158


PL58


PM0 8PM1 8PM2 8PM3 8PM4 8PM5 8PM6 8PM7 8PM8 8PM9 8PM10 8PM11 8PM12 8PM13 8PM14 8PM15 8

PN0 8PN1 8PN2 8PN3 8PN4 8PN5 8PN6 8PN7 8PN8 8PN9 8PN10 8PN11 8PN12 8PN13 8PN14 8PN15 8

PO0 8PO1 8PO2 8PO3 8PO4 8PO5 8PO6 8PO7 8PO8 8PO9 8PO10 8PO11 8PO12 8PO13 8PO14 8PO15 8

PP0 8PP1 8PP2 8PP3 8PP4 8PP5 8PP6 8PP7 8PP8 8PP9 8PP10 8PP11 8PP12 8PP13 8PP14 8PP15 8

PQ48PQ58PQ68PQ78

PQ08PQ18PQ28PQ38

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


MPC5748G GPIO 2of2

5 8



U1C

MPC5748G + OTB-324R-1.0-019-00

PI0C6

PI1E7

PI2C7

PI3C8

PI4A18

PI5E11

PI6H4

PI7G3

PI8P18

PI9T12

PI10U12

PI11N18

PI12N17

PI13M16

PI14R16

PI15P16

PJ0U18

PJ1V13

PJ2R11

PJ3U11

PJ4A1

PJ5T16

PJ6U16

PJ7U17

PJ8U13

PJ9V5

PJ10V4

PJ11U3

PJ12V3

PJ13T6

PJ14R6

PJ15U4

PK0T4

PK1N3

PK2N4

PK3P1

PK4P2

PK5P3

PK6P4

PK7R1

PK8R2

PK9B7

PK10A6

PK11B6

PK12A5

PK13B5

PK14C5

PK15A4

PL0B4

PL1L15

PL2E15

PL3E14

PL4F13

PL5F14

PL6F15

PL7G13

PL8D15

PL9E13

PL10G12

PL11E16

PL12D16

PL13F16

PL14G16

PL15G15

PM0G14

PM1H13

PM2H15

PM3L13

PM4K15

PM5M14

PM6L16

PM7H16

PM8J13

PM9H14

PM10J14

PM11G10

PM12G11

PM13M13

PM14M15

PM15T10

PN0T9

PN1V11

PN2U9

PN3T8

PN4U7

PN5R8

PN6P8

PN7U6

PN8U5

PN9T5

PN10T7

PN11V2

PN12V1

PN13U1

PN14R4

PN15L4

PO0G1

PO1F1

PO2M6

PO3L6

PO4E1

PO5H6

PO6H5

PO7D1

PO8D2

PO9E3

PO10D3

PO11C1

PO12B1

PO13E4

PO14F4

PO15G6

PP0G5

PP1B3

PP2C4

PP3F7

PP4E5

PP5G7

PP6A2

PP7A3

PP8B8

PP9A7

PP10A8

PP11B9

PP12B17

PP13B16

PP14C17

PP15B18

PQ0C11

PQ1B13

PQ2B14

PQ3F11

PQ4A15

PQ5A16

PQ6B15

PQ7A17

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Oscillators and External Clock

(XTAL32)

(EXTAL32)

NX8045GB-40.000M-STD-CSJ-1 XTAL(Optimised for Automotive, 8pF Load capacitance)

FC-255 32.7680K-A3(Load Capacitance 7pF)

(From SMA connector on main board)

Clocks

EXTAL

MCU-XTAL

PB8

MCU-EXTALXTAL

PB9

EXT-CLK

GND

GND

GNDMCU-XTAL4

PB84

PB94

MCU-EXTAL4

EXT-CLK8

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B


Clocks

6 8


R331.0MDNP

J2

1

2

3Y2032.768KHZ

12

C62 12PF

Y140.0MHZ

12

C7 12PF

C6 12PF

R34 0

DNP

C63 12PF

R81.0MDNP

J11

2

3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A




Place resistors as close as possible to MCU

R1 Fitted by defaultfor LVDS 6-pin signals

Remove R1 andfit R2 toenable 3-pinsignals

Layout Note - Place resistors as shown withshared pad (as close to MCU as possible)


From MCU To Daughtercard

MLB Termination

Ethernet Termination

High Speed Signal Termination

PB14

PD15

PB13

PD14

PI8

MLB_SN

MLB_SP

MLB_DN

MLB_DP

MLB_CN

MLB_CP

PB15

MLB_CLKMLB_SIGMLB_DAT

PH2PH1

PG12PH0

PG13

PH2-RPH1-RPH0-R

PG13-RPG12-R

PG0-RPG0

PI85

PB144

PD154

PB154

PB134

PD144

MLB_DAT 8MLB_SIG 8MLB_CLK 8

MLB_SN 8

MLB_SP 8

MLB_DN 8

MLB_DP 8

MLB_CN 8

MLB_CP 8

PG134PG124PH04PH14PH24

PG13-R 8PG12-R 8PH0-R 8PH1-R 8PH2-R 8

PG0-R 8PG04

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B



7 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B



7 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


B



7 8


R20100DNP

R27 100 1%R26 0

R28 0

R32 0R31 105.0 1%

R25100DNP

R22 105.0 1%

R30 0

R2 50R3 50

R21 0

R23 0

R5 50

R29100DNP

R4 50

R1 50

R6 50

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Daughter Card Connectors (Plugs)

Notes:

- there was no neat way to fit these connectors onto a B sized sheet so unfortunately the sheet sizehas been increased to C so will need to be printed on larger paper.

- The Crystal Signals are NOT routed via the daughtercard connectors- The Specific MCU power pins are not routed via the daughter card however the jumpered MCU supplylines are brought up from the main board (see the top pins of the connector on the left)

- The connector schematic symbols have been horizontally mirrored so they match the main EVB connector.This has no bearing on the PCB placement or footprint. Pin1 on the recepticle mates with pin 1 on theplug.

(GND)

(GND) (GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

Plug

(GND)

(GND)(GND)

(GND)(GND)

(GND)

(GND)(GND)

(GND) (GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

Connectors on Main board (Shown for reference)

Plug

PB3

PA12

PF0PF1PN2

PN5

PH8

PH7

PP8

PH6

PP3PE7PK9

PC12PK11

PP4

PA13PN4

PC8 PK14PK13 PK12

PC9PP2 PL0PK15PC15 PP1PP7

PC14PP6 PJ4

PO12PO7PO10

PJ14PN7PF10PN8

PO4 PH14PO9 PO13

PO1PG5PH13PO14

PO0

PJ15

PG4PI7 PH15PP0 PO15

PE10PE1 PE0PI6 PO6PO5PE11 PG2

PC7PN12PJ12

PG3 PA2PE9

PE8 PA1MCU-RSTx

PF8

PK7PC6

PG9 PN15

PF13PK4PK6

PA0 PO3

PN14PK8

PG7 PG6PG8 PC11PC10 PO2

PB0

PB10PN0

PN6PN3PA15PN10

PA4PJ13

PN9PJ9

PB1 PK1PK2 PF12

PK3PK5PF11

PF9PA14PN13

PN11PJ11PJ10PK0


PB2

PP11

EXT-CLK

PO11PO8

MCU_5V0_S

MCU_1V25_L

MCU_3V3_S

MCU_3V3_LMCU_5V0_L

DC_5V0_S

DC_P12VDC_1V25_L

DC_3V3_S

DC_5V0_LDC_3V3_L

PF3PF7PF4

PL10

PE5

PG14

PM12

PQ0PI5

PC5

PQ3

PE4PC3

PC2

PL15

PM2PM1

PC0

PA8

PH2-RPG0-RPF14

PA9PA10

PA7

PG1PF15PE13

PA11PE12

PL14

PM7PM9

PL11 PL5

PH1-RPH0-RPA3

PG12-RPG13-R

PH9

PI13

PM11

PM4PL1

PM5

PM3

PM14

PC1

PM13

PH10

PB12

PE3PH4 PH5

PL4

PE15

PL9

PL3

PH12

PG11

PG10

PL8

PORSTx

PH11

PE14

PG15

PC4

PQ1

PQ2

PQ6

PP13PP12

PE2

PA6

PA5

PQ4

PQ5PQ7 PI4PP15 PP14

PF5PI9PD8

PJ3PJ2PB4

PM15PF2

PD7PJ5PJ0

PD5PB5

PJ1PD1PB11

MLB_DNMLB_DP

PI10PD0PB6

PN1PF6PD4


PJ8PD3

MLB_DATMLB_CPMLB_CN

MLB_CLKMLB_SIG

MLB_SNMLB_SP

PL12 PL2

PL13PL6PM0

PM10

PL7

PM8PH3

PM6

PI11PI12PD12PD9PD13

PI15PD10PB7

GND GNDGND GND

PN5 5PA12 4PN2 5PF1 4PF0 4

PN4 5PA13 4

PN8 5PF10 4PN7 5PJ14 5

PJ15 5

PC7 4PN12 5PJ12 5

PF8 4

PK7 5PC6 4

PF134PK45PK65PK85PN145

PH7 4PH6 4PB3 4

PP8 5PH8 4

PP3 5PE7 4PK9 5

PC12 4PK11 5

PP4 5PK14 5PK12 5PC9 4PL0 5

PP1 5

PC14 4PJ4 5

PH14 4PO13 5

PO1 5PH13 4PG4 4PH15 4PO15 5PE10 4PE0 4PO6 5

PG2 4PA2 4PE9 4PA1 4MCU-RSTx 4PN15 5PO3 5

PG6 4PC11 4PO2 5

PB0 4PK1 5PF12 4

PK3 5PK5 5PF11 4

PC84PK135

PP25PK155PC154PP75

PP65

PO125PO75PO105PO45PO95

PG54PO145PO05PI75PP05

PE14PI65PO55PE114PG34

PE84

PG94PA04

PG74PG84PC104

PB14PK25

PF94PA144PN135

PN115PJ115PJ105PK05PJ95PN95

PJ135

PE64PI35PP105

PA44

PP55PI15PI25

PN105

PP95PC134PI05

PA154

PK105

PN35

PB24

PP115

PN65

PN05PB104

EXT-CLK6

PO11 5PO8 5

MCU_5V0_S2

MCU_1V25_L2

MCU_3V3_S 2


PF4 4PF7 4PF3 4

PL155PM15PM25

PC0 4

PL14 5PM9 5PM7 5

PH9 4

MLB_DN 7MLB_DP 7

PC1 4PE3 4PH5 4

PQ3 5PC3 4PE4 4

PL10 5PE15 4PORSTx 4PE2 4PL4 5PG11 4PQ1 5

PG10 4PQ2 5PL8 5PQ6 5

PP13 5PP12 5PI4 5PP14 5

PL2 5PL5 5PL13 5PM0 5

PA10 4PA9 4PA8 4PF14 4PG0-R 7PH2-R 7

PG12-R 7PG13-R 7

PM10 5PM4 5PL1 5

PM5 5PI13 5PB12 4PD9 4PI12 5PB7 4PI15 5

MLB_CN 7MLB_CP 7

PI14 5PJ7 5PD11 4PJ6 5PD6 4PD2 4PD3 4PJ8 5

PB6 4PD0 4PI10 5

PD4 4PF6 4PN1 5

PM115PH104PH44PE54PM125PI55PQ05PC54

PG144PH124PC44

PL95PC24PA64PL35PH114PA54PE144PQ45PG154PQ55PQ75PP155

PL125PL115PL65PL75

PE124PA114


PM85PH34PM35PM65PM135PM145

PD134PD124PI115PD104


MLB_SN7MLB_SP7

PD74PJ55PJ05

PD54PB54PB114PD14PJ15

PD84PI95PF54PB44PJ25PJ35

PF24PM155

Drawing Title:


Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


C



8 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


C



8 8



Date: Sheet of

Page Title:


SCH-27900 PDF: SPF-27900 A1


C



8 8


TPV1

TPV2 TPV6TPV5

P21

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12

TPV3

TPV4

P20

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12

256 BGA DC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AFreescale AISG Applications, East Kilbride

A

X2X3X4



Clocks

Sheet 8



Table Of Contents:

MPC5748G Customer EVB 256BGA [6M/3M] Daughter Card (X-MPC574XG-256DS)



11 Mar 2013 Alasdair Robertson Initial release sent for review based on X-MPC574XG-324DS X2




Caution:


13 Mar 2013 Alasdair Robertson15 Mar 2013 Component consolodation, Few minor changes. Sent to LayoutAlasdair Robertson

Version sent to Pre Layout, incorporating fixes from review

29 Mar 2013 Alasdair Robertson Changes made during layout to Daughtercard Connectors

Alasdair Robertson Post Layout (Back Annotated). Matches PCB RevA15 Apr 2013 Alasdair Robertson LAY RefDes Re-Sequence & SCH Back-AnnotateX515 Apr 2013

Changes on MCU Power to validate MPC5746Jesus Sanchez16 Mar 2014X1SCH-27899 change to SCH-28341

A 18 Apr 2014 Jesus Sanchez Post Layout. RevA.A1 Alasdair Robertson Tidy up Schematics for UM (RevA PCB)18 Aug 2015

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-28341 PDF: SPF-28341 A


B



A. Robertson / J. Sanchez


A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-28341 PDF: SPF-28341 A


B





A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-28341 PDF: SPF-28341 A


B





A. Robertson

1 8


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


3v3




DAC ExternalRef VoltageSelect

3v3 5v0 5v0 5v0 5v0 5v03v3 3v3 3v33v3

3v3

5v0

(Current Limit Resistor toprotecxt against case whenother MCU supplies aredisconnected and externalreference supply is live)



- Don't attempt to over drive an analogue pad to 5Vwhen the digital VDD_HV_x supply is set to 3.3V. Thiswill trigger the ESD protectrion on that pad. Forexample if VDD_HV_A is set to 3.3V and the analoguesupplies are set to 5V, you cannot drive 5V into apad in the VDD_HV_A domain

Differences to 324BGA

- 1 more VDD_HV_A on 256BGA- 1 fewer VDD_HV_B- 1 fewer VDD_LV- 2 more VSS_HV- 1 fewer VSS_LV

From MCUsupplyjumpers onmain board

MCU_3V3_S

MCU_5V0_S

MCU_1V25_L

MCU_3V3_L

MCU_5V0_L

HVB

_CAP

HVC

_CAP

HVF

LA_C

AP

LV_C

AP

ADC

0_C

AP

ADC

1_C

AP

ADC

1REF

_CAP


HVA

_CAP


E_C

AP

B_C

AP

LVD

EC_C

AP

HVA

_CAP

GND

GND

HVA_CAP

GND

GND

GND

GND

MCU_1V25_L8

MCU_5V0_S8

MCU_3V3_S8

MCU_5V0_L8

MCU_3V3_L8

Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G MCU Power

2 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G MCU Power

2 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G MCU Power

2 8


TP12TP10

1

C631.0 UFDNP

J11

1

2

3

J12

12

R371.0DNP

TP11

Q20MJD31CT4

34

1

J3

1

2

3

R3910KDNP

J10

1

2

3

TP2

R10 0

R361.0K

1.25v Core & External BallastAnalogue MPC5748G 256 BGAPackage 2of3 Power Pins

Flash

DAC Ref

U1B

PPC5748GSK0MMJ6 + OTB-256(324R)-1.0-006-00

VRC

_CTR

LJ2

VSS_

LV_E

6E6

VSS_

LV_H

6H

6

VSS_

LV_H

7H

7

VSS_

LV_H

15H

15

VSS_

LV_J

6J6

VSS_

LV_J

7J7

VSS_

LV_J

8J8

VSS_

LV_K

6K6

VSS_

LV_K

7K7

VSS_

LV_K

8K8

VSS_

LV_K

9K9

VSS_

LV_L

6L6

VSS_

LV_L

7L7

VSS_

LV_L

8L8

VSS_

LV_L

9L9

VDD

_LV_

D8

D8

VDD

_LV_

E5E5

VDD

_LV_

H14

H14

VDD

_LV_

J3J3

VDD

_LV_

K10

K10

VDD

_LV_

K11

K11

VDD

_LV_

L10

L10

VDD

_LV_

L11

L11

VDD

_HV_

A_C

2C

2

VDD

_HV_

A_C

9C

9

VDD

_HV_

A_N

6N

6VD

D_H

V_A_

E16

E16

VDD

_HV_

A_H

13H

13

VDD

_HV_

A_N

9N

9

VDD

_HV_

B_G

13G

13

VDD

_HV_

C_M

10M

10

VSS_

HV_

ADC

0T1

5VD

D_H

V_AD

C0

R15

VDD

_HV_

ADC

1L1

6VS

S_H

V_AD

C1

M16

VDD

_HV_

FLA_

H2

H2

VDD

_HV_

ADC

1_R

EFM

11

VSS_

HV_

G6

G6

VSS_

HV_

G7

G7

VSS_

HV_

G8

G8

VSS_

HV_

G9

G9

VSS_

HV_

G10

G10

VSS_

HV_

G11

G11

VSS_

HV_

H8

H8

VSS_

HV_

H9

H9

VSS_

HV_

H10

H10

VSS_

HV_

H11

H11

VSS_

HV_

J9J9

VSS_

HV_

J10

J10

VIN

1_C

MP_

REF

M9

VDD

_LP_

DEC

K2

VSS_

HV_

VPP

J1

VDD

_HV_

A_R

9R

9

VSS_

HV_

J11

J11

VSS_

HV_

T9T9

TP1

J7

1

2

3

TPH2

1

J5

1

2

3

R3810K

TPH3

1

TPH1

1

J13

1

2

3

J6

1

2

3

J4

1

2

3

R9 0

TP3

R7 0

J8

12

R350

J9

1

2

3

TP14TP13

R240

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Capacitor Types:





ADC


VDD_HVA VDD_HVB VDD_HVC

VDD_LV


VDD_LV (1.25V) Decoupling. Place one of the non DNP caps each side of the deviceas close as possible to pin. Distribute other (DNP) caps around rest of pins

Ballast Transistor

Flash


LP Internal Reg Cap




(low ESR)

(lowESR)

(lowESR)


(lowESR)

(lowESR)

(lowESR) (low

ESR)(low ESR)




- 1 more VDD_HV_A capacitor pair- 1 fewer VDD_HV_B capacitor pair- 1 fewer VDD_LV capacitor (one of DNP caps)

ADC0_CAP

ADC0_GND

ADC1REF_CAP

ADC1_GND

ADC1_CAP

ADC1_GND

GND

HVA_CAP

GND

HVB_CAP

GND

HVC_CAP

LV_CAP

GND

HVFLA_CAP

GND

LV_CAPB_CAP E_CAP

GND

LVDEC_CAP

GND

E_CAP

GND

Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B



3 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B



3 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B



3 8


C300.1UF

C421000pF

C260.1UF

C500.1UFDNP

C240.1UF

C33470pF

C600.68uF

C47

1000pF

C440.1UF

C581.0 UF

C490.1UF


C320.1UF


C250.1UFDNP

C290.68uF

C410.1UF

C520.1UF

C28470pF

C102.2UFDNP

C511000pF

C560.1UF

C200.68uFDNP

C230.1UF

C481000pF

+ C410UFDNP

C390.1UF

C550.1UF

C571.0 UF

C541000pF

C92.2UFDNP

C461000pF

C36

1000pF

C530.1UF

+ C110UF

+C210UFDNP

C380.1UF

C8 4700pF

C591.0 UF

C40470pF

C210.1UFDNP

C27470pF

C310.68uF

C350.1UF

+C310UFDNP

C450.1UFDNP

C371000pF

+ C510UFDNP

C22470pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A




(LIN0_RX)(LIN0_TX)

(LIN1_TX)(LIN1_RX)

(XTAL32)(EXTAL32)

(FR_A_TX)


(FR_B_TX_EN)

(FR_B_RX)(FR_B_TX)

(USB1_CLK)

(USB1_D0)(USB1_D1)

(USB1_D2)(USB1_D3)

(USB1_D4)(USB1_D5)

(USB1_D6)(USB1_D7)

(USB1_DIR)



(MII_RXD3)(MII_CRS)



(RMII_TXEN)




(MII_RXCLK)


(SD_CMD)(SD_CLK)

(SD_WP)


(SAI0_SYNC)


(TDI)(TDO)

(TCK)(TMS)


(MLB_DN)

(MLB_DP)

(MLB_SN)

(MLB_SP / DAT)

(MLB_CN / SIG)





(CMP1_8 / IO)

(CMP1_10 / IO)

(CMP1_11 /IO)

(CMP1_12 / IO)

(CMP1_13 / IO)

(CMP1_14 / IO)(CMP1_15 / IO)

(CLKOUT1 GPIO)

(GPIO)

(GPIO)




(MLB_RST)(MLB_PWR)

(MLB_IRQ - WKPU21)

** PA1 is also NMI. Routed to I/O Matrix


(CLKOUT0 GPIO)



(GPIO)(GPIO)


(GPIO)

(CAN0_TX)(CAN0_RX)

(SW4 & GPIO)

(CAN1_RX)(CAN1_TX)

(SW3 & GPIO)


(SD_CD - WKPU19)

(GPIO)(GPIO)(GPIO)



WKPU22

WKPU15


(none on this page)


(GPIO & MLB_ST)

PA0PA1

PA3PA2

PA4

PB3PB4

PC3PC4

PD3PD4

PE0PE1

PE3PE2

PE4PE5

PE7PE6

PE8PE9

PE11PE10

PE12PE13

PE15PE14

PF0PF1

PF3PF2

PF4PF5

PF7PF6

PF8PF9

PF11PF10

PF12PF13

PF15PF14

PG0PG1

PG3PG2

PG4PG5

PG7PG6

PG8PG9

PG11PG10

PG12PG13

PG15PG14

PH0PH1

PH3PH2

PH4PH5

PH7PH6

PH8PH9

PH11PH10

PH12PH13

PH15PH14

MCU-EXTAL

PA5

PA7PA8

PA6

PA10

PA13PA12PA11

PA9

PA14PA15

PB1PB0

PB8

PB11PB10PB9

PB2

PB5

PB7PB6

PB12

PB14PB13

PB15

PC0

PD6

PC12

PC14PC15

PC9

PD8

PC5

PC10

PD2

PC11

PD0

PC6PC7

PC1

PD7

PD5

PC8

PD11

PD9

PC13

PC2

PD1

PD10

PD14PD15

PD13PD12

MCU-RSTxPORSTx

MCU-XTAL

PH0 7

PORSTx8MCU-RSTx8

MCU-EXTAL6MCU-XTAL6

PB08PB18PB28PB38





PA58


PB58PB48



PC58PC48

PC08PC18PC28PC38



PD58PD48

PD08PD18PD28PD38





Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G GPIO 1of2

4 8



U1A

PPC5748GSK0MMJ6 + OTB-256(324R)-1.0-006-00

RESETK1

PORSTC8

XTALT7

EXTALT8

PA0G4

PA1F3

PA2F1

PA3G16

PA4T2

PA5C10

PA6D11

PA7C15

PA8B16

PA9B15

PA10A15

PA11B14

PA12P6

PA13R5

PA14P4

PA15R2

PB0L3

PB1M2

PB2A2

PB3D4

PB4T16

PB5N13

PB6N14

PB7R16

PB8T11

PB9T10

PB10N7

PB11M13

PB12L14

PB13L15

PB14K15

PB15K16

PC0B10

PC1D9

PC2B11

PC3C11

PC4A9

PC5B9

PC6N3

PC7N4

PC8B3

PC9C3

PC10L1

PC11K4

PC12B4

PC13A3

PC14B2

PC15A1

PD0R12

PD1T13

PD2N11

PD3R13

PD4P12

PD5T14

PD6R14

PD7P13

PD8P14

PD9N16

PD10M14

PD11M15

PD12L13

PD13K14

PD14K13

PD15J13

PE0G2

PE1F4

PE2A7

PE3A10

PE4A8

PE5B8

PE6B6

PE7A5

PE8G1

PE9H1

PE10G3

PE11H3

PE12C14

PE13C16

PE14A14

PE15C12

PF0P7

PF1T6

PF2R6

PF3R7

PF4R8

PF5P8

PF6N8

PF7P9

PF8N2

PF9M4

PF10P2

PF11R1

PF12P1

PF13P3

PF14D14

PF15D15

PG0E13

PG1E14

PG2E4

PG3E1

PG4F2

PG5D1

PG6M1

PG7L2

PG8K3

PG9J4

PG10B13

PG11A16

PG12F15

PG13F16

PG14C13

PG15D13

PH0E15

PH1F13

PH2D16

PH3F14

PH4D7

PH5B7

PH6C7

PH7C6

PH8A6

PH9A11

PH10D10

PH11A13

PH12B12

PH13B1

PH14C1

PH15E3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A



(USB0_CLK)

(USB0_D0)(USB0_D1)(USB0_D2)(USB0_D3)

(USB0_D4)(USB0_D5)(USB0_D6)(USB0_D7)(USB0_NXT)(USB0_DIR)

(USB0_STP)



(SAI2_D0)

(SAI2_BCLK)

(SAI2_MCLK)

(SAI2_SYNC)

(MLB_CP / CLK)(GPIO)(GPIO)

(GPIO)

(GPIO)


(GPIO)(GPIO)




(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)



(ENET_RST)








- 14 fewer pins on Port L- 12 fewer pins on Port M- 16 fewer pins on Port N- 14 fewer pins on Port O- 12 fewer pins on Port P

(And corresponding changesto daughtercard connectors)

(GPIO & MLB_PS0)(GPIO & MLB_PS1)

PI0PI1

PI3PI2

PI4PI5

PI7PI6

PI8PI9

PI11PI10

PI12PI13

PI15PI14

PJ0PJ1

PJ3PJ2

PJ4

PJ7PJ6

PJ8PJ9

PJ11PJ10

PJ12PJ13

PJ15PJ14

PK0PK1

PK3PK2

PK4PK5

PK7PK6

PK8PK9

PK11PK10

PK12PK13PK14

PL0PL1

PM3PM4PM5

PM14

PO0PO1

PP12PP13

PP15PP14

PK15

PQ1

PQ3PQ2

PQ4PQ5PQ6

PJ5

PQ7

PQ0



PI58




PJ58




PK58


PL08PL18

PM3 8PM4 8PM5 8

PM14 8

PO0 8PO1 8

PP12 8PP13 8PP14 8PP15 8

PQ48PQ58PQ68PQ78

PQ08PQ18PQ28PQ38

Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


MPC5748G GPIO 2of2

5 8



U1C

PPC5748GSK0MMJ6 + OTB-256(324R)-1.0-006-00

PI0C5

PI1A4

PI2D6

PI3B5

PI4A12

PI5D12

PI6D2

PI7E2

PI8J14

PI9J15

PI10J16

PI11H16

PI12G15

PI13G14

PI14T12

PI15P11

PJ0R11

PJ1N10

PJ2R10

PJ3P10

PJ4D3

PJ5N12

PJ6N15

PJ7P16

PJ8P15

PJ9P5

PJ10T5

PJ11R3

PJ12T1

PJ13N5

PJ14T4

PJ15R4

PK0T3

PK1H4

PK2L4

PK3N1

PK4M3

PK5M5

PK6M6

PK7M7

PK8M8

PK9E8

PK10E7

PK11F8

PK12G12

PK13H12

PK14J12

PK15D5

PL0C4

PL1F7

PM3K12

PM4L12

PM5F9

PM14M12

PO0K5

PO1L5

PP12E12

PP13F12

PP14E11

PP15F11

PQ0J5

PQ1H5

PQ2G5

PQ3F5

PQ4F6

PQ5E9

PQ6F10

PQ7E10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


(XTAL32)

(EXTAL32)




Clocks

EXTAL

MCU-XTAL

PB8

MCU-EXTALXTAL

PB9

EXT-CLK

GND

GND

GNDMCU-XTAL4

PB84

PB94

MCU-EXTAL4

EXT-CLK8

Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B


Clocks

6 8


J2

1

2

3

R81.0MDNP

C61 12PF

Y2032.768KHZ

12

C7 12PF

Y140.0MHZ

12

R331.0MDNP

R34 0

DNP

C6 12PF

C62 12PF

J11

2

3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A










MLB Termination



PB14

PD15

PB13

PD14

PI8

MLB_SN

MLB_SP

MLB_DN

MLB_DP

MLB_CN

MLB_CP

PB15


PH2PH1

PG12PH0

PG13

PH2-RPH1-RPH0-R

PG13-RPG12-R

PG0-RPG0

PI85

PB144

PB154

PB134


MLB_SN 8

MLB_SP 8

MLB_DN 8

MLB_DP 8

MLB_CN 8

MLB_CP 8



PG0-R 8PG04

PD154

PD144

Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B



7 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B



7 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


B



7 8


R20100DNP

R26 0R27 100 1%

R28 0

R32 0

R25100DNP

R31 105.0 1%

R22 105.0 1%

R1 50

R30 0

R21 0

R3 50

R6 50

R23 0

R2 50

R5 50

R29100DNP

R4 50

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


Notes:

- there was no neat way to fit these connectors onto a B sized sheet so unfortunately the sheetsize has been increased to C so will need to be printed on larger paper.

- The Crystal Signals are NOT routed via the daughtercard connectors- The Specific MCU power pins are not routed via the daughter card however the jumpered MCUsupply lines are brought up from the main board (see the top pins of the connector on the left)

- The connector schematic symbols have been horizontally mirrored so they match the main EVBconnector. This has no bearing on the PCB placement or footprint. Pin1 on the recepticle mateswith pin 1 on the plug.


(PO12)

(PO3)

(PO2)

(PO7)

(PN12)

(PO10)

(PN8)

(PO4)

(PN7)

(PO9)

(PN4)

(PO14)

(PN5)

(PP0)

(PN2)

(PO5)

(PN14)

(PN13)

(PN11)

(PN9)

(PN10)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

Plug

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(PN3)(PN6)

(PN0)

(PP8)(PP11)

(PP3)(PP10)

(PP4)

(PP5)

(PO11)

(PP2)

(PO8)

(PP7)

(PO13)

(PP6)

(PO15)

(PP1)

(PO6)

(PP9)

(PN15)

(PL11)(PL6)(PL7)

(PL15)(PM1)(PM2)

(PL4)

(PL8)

(PL10)

(PL5)(PL13)(PM0)

(PL14)(PM9)(PM7)

(PM10)(PM8)

(PM6)(PM13)

(PN1)

(PM11)

(PL2)

(PM15)

(PM12)

(PL9)

(PL3)

(PL12)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

Plug

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)(GND)

PC8PK13

PK15

PG5

PO0PI7

PE1PI6

PE11PG3

PE8

PG9

PF13

PA0

PK8

MCU_5V0_S

MCU_1V25_L

PG8

PB10

PA15

PA4PJ13

PJ9

PK2

PF9PA14

PJ11PJ10PK0

PI3

PI1PI2

PC13PI0PK10

PB2

EXT-CLK

PB3

PA12

PF0

PH8

PH7PH6

PE7PK9

PC12

PA13

PK14

PC9PL0

PC14PJ4

PH14

PO1PH13

PJ15

PH15

PE10PE0

PG2

PC7

PJ12

PA2PE9PA1MCU-RSTx

PF8

PK7PC6

PG6PC11

PB0

PF12

PK3PK5PF11

MCU_3V3_S

PE6

PK11

PK12

PC15

PG4

PG7

PC10

PB1 PK1

PK4PK6

PF10

PJ14

PF1

MCU_3V3_LMCU_5V0_L

PC0PE5

PG14

PQ0PI5

PC5

PC2

PA7

PG1PF15PE13

PA11PE12

PH1-RPH0-RPA3

PM3

PM14

PH10PH4

PH12

PH11

PE14

PG15

PC4

PA6

PA5

PQ4

PQ5PQ7PP15

PF5PI9PD8

PJ3PJ2PB4

PF2

PD7PJ5PJ0

PD5PB5

PJ1PD1PB11

MLB_DAT

MLB_CLKMLB_SIG

MLB_SNMLB_SP

PH3

PI11PD12PD13

PD10

DC_5V0_S

DC_P12VDC_1V25_L

PF3PF7PF4

PQ3

PE4PC3

PA8

PH2-RPG0-RPF14

PA9PA10

PG12-RPG13-R

PI13

PM4PL1

PM5

PC1

PB12

PE3PH5

PE15

PG11

PG10

PORSTx

PQ1

PQ2

PQ6

PP13PP12

PE2

PI4PP14

MLB_DNMLB_DP

PI10PD0PB6

PF6PD4


PJ8PD3

MLB_CPMLB_CN

PI12PD9

PI15PB7

DC_3V3_S

DC_5V0_LDC_3V3_L

PH9

GND GNDGND GND

PB24PH7 4PH6 4PB3 4PH8 4

PE7 4PK9 5

PC12 4PK11 5

PK14 5PK12 5PC9 4PL0 5

PC14 4PJ4 5

PH14 4

PO1 5PH13 4PG4 4PH15 4

PE10 4PE0 4

PG2 4PA2 4PE9 4PA1 4MCU-RSTx 4

MCU_5V0_S2

MCU_1V25_L2

MCU_3V3_S 2


PG6 4PC11 4

PB0 4PK1 5PF12 4

PK3 5PK5 5PF11 4

PK7 5PC6 4PF8 4

PC7 4

PJ12 5

PJ15 5

PF10 4

PJ14 5

PA13 4

PA12 4

PF1 4PF0 4

PE64PI35

PI15PI25

PC134PI05PK105PC84PK135

PK155PC154

PG54

PO05PI75

PE14PI65

PE114PG34

PE84

PG94PA04

PG74PG84PC104

PB14PK25

PF134PK45PK65PK85

PF94PA144

PJ115PJ105PK05PJ95

PJ135PA44

PA154

PB104

EXT-CLK6

PD2 4PD3 4PJ8 5

PB6 4PD0 4PI10 5

PD4 4PF6 4

PF4 4PF7 4PF3 4

PH104PH44PE54

PI55PQ05PC54

PG144PH124PC44

PC24PA64

PH114PA54PE144PQ45PG154PQ55PQ75PP155

PE124PA114


PH34PM35

PM145

PD134PD124PI115PD104


MLB_SN7MLB_SP7

PD74PJ55PJ05

PD54PB54PB114PD14PJ15

PD84PI95PF54PB44PJ25PJ35

PF24

PC0 4

PC1 4PE3 4PH5 4

PQ3 5PC3 4PE4 4

PE15 4PORSTx 4PE2 4

PG11 4PQ1 5

PG10 4PQ2 5

PQ6 5

PP13 5PP12 5PI4 5PP14 5

PA10 4PA9 4PA8 4PF14 4PG0-R 7PH2-R 7

PG12-R 7PG13-R 7

PH9 4

PM4 5PL1 5

PM5 5PI13 5PB12 4PD9 4PI12 5PB7 4PI15 5

MLB_CN 7MLB_CP 7

MLB_DN 7MLB_DP 7

PI14 5PJ7 5PD11 4PJ6 5PD6 4

Drawing Title:


Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


C



8 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


C



8 8



Date: Sheet of

Page Title:


SCH-28341 PDF: SPF-28341 A


C



8 8


TPV1 TPV4

P21

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12 TPV6

TPV3

P20

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12TPV2

TPV5

176 QFP DC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B


A

X2X3X4



Clocks

Sheet 8



Table Of Contents:

MPC5748G Customer EVB 176QFP Daughter Card (MPC574XG-176DS)



11 Mar 2013 Alasdair Robertson




Caution:


Initial release sent for review based on X-MPC574XG-324DS X213 Mar 2013 Alasdair Robertson15 Mar 2013 Component consolodation, Added MCU GND tab. Sent to LayoutAlasdair Robertson

Version sent to Pre Layout, incorporating fixes from review

Changes made during layout to Daughtercard Connectors29 Mar 2013 Alasdair Robertson

Alasdair Robertson Post Layout (Back Annotated). Matches PCB RevAX5 LAY RefDes Re-Sequence & SCH Back-Annotate15 Apr 2013 Alasdair Robertson

15 Apr 201322 Jul 2013B Alasdair Robertson Update to accomodate extra socket pins on MCU19 Nov 2013C Jesus Sanchez The socket was updated, exposed center PAD is grounded.

Changes on MCU Power to validate MPC5746Jesus Sanchez19 Dec 2013DD1 17 Aug 2015 Alasdair Robertson Tidy up Schematics for UM (RevD PCB)

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27898 PDF: SPF-27898 D1

MPC5748G 176 QFP Daughter Card

B



A. Robertson

A. Robertson

A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27898 PDF: SPF-27898 D1


B



A. Robertson

A. Robertson

A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27898 PDF: SPF-27898 D1


B



A. Robertson

A. Robertson

A. Robertson

1 8


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


3v3




3v3 5v0 5v0 5v0 5v03v3 3v3

3v3

3v3

5v0



- Don't attempt to over drive an analogue pad to 5Vwhen the digital VDD_HV_x supply is set to 3.3V. Thiswill trigger the ESD protectrion on that pad. Forexample if VDD_HV_A is set to 3.3V and the analoguesupplies are set to 5V, you cannot drive 5V into apad in the VDD_HV_A domain


- 2 fewer VDD_HV_A on 176QFP- 1 fewer VDD_HV_B- No VDD_HV_C- 5 Fewer VDD_LV- No VIN1_CMP_REF- 15 Fewer VSS_LV- 5 Fewer VSS_HV- Heat Dissipation GND TAB

From MCUsupplyjumpers onmain board

INT_BAL_SELECT enableMPC5746


MCU_3V3_S

MCU_5V0_S

MCU_1V25_L

MCU_3V3_L

MCU_5V0_L

HVB

_CAP

HVF

LA_C

AP

LV_C

AP

ADC

0_C

AP

ADC

1_C

AP

ADC

1REF

_CAP

ADC0_GND ADC1_GND

GND

HVA

_CAP


E_C

AP

B_CAP

LVD

EC_C

AP

GND GNDGND

HVA_CAP

GND GND

MCU_1V25_L8

MCU_5V0_S8

MCU_3V3_S8

MCU_5V0_L8

MCU_3V3_L8

Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G MCU Power

2 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G MCU Power

2 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G MCU Power

2 8


C511.0 UF

DNP

R360

1.25v Core & External BallastAnalogue MPC5748G 176QFPPackage 2of3 Power Pins

Flash

Central Pad for heatdissipation & GND

U1B

PPC5748GSK0MKU6 + OTQ-176SG-0.5-004-00

VRC

_CTR

L32

VSS_

LV_1

0910

9

VDD

_LV_

3131

VDD

_LV_

5454

VDD

_LV_

110

110

VDD

_LV_

152

152

VDD

_HV_

A_6

6

VDD

_HV_

A_59

59

VDD

_HV_

A_85

85

VDD

_HV_

A_15

115

1

VDD

_HV_

B_12

412

4

VSS_

HV_

ADC

089

VDD

_HV_

ADC

090

VDD

_HV_

ADC

199

VSS_

HV_

ADC

197

VDD

_HV_

FLA

27

VDD

_HV_

ADC

1_R

EF98

VSS_

HV_

77

VSS_

HV_

2828

VSS_

HV_

5555

VSS_

HV_

5757

VSS_

HV_

8686

VSS_

HV_

123

123

VSS_

HV_

150

150

VDD

_LP_

DEC

30

VSS_

HV_

VPP

26

EX_P

AD1

177

EX_P

AD2

178

EX_P

AD3

179

EX_P

AD4

180

EX_P

AD5

181

J91

2

3

J8

12

R3810K

DNP

J5

1

2

3

R200

R27 0

R8 0

Q20MJD31CT4

34

1J3

1

2

3

TP107TPAD_030

J14

12

J10

1

2

3

TPH2

1

J4

1

2

3

R391.0DNP

R3710K

J11

1

2

3

TPH1

1

J6

1

2

3

R9 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Capacitor Types:





ADC


VDD_HVA VDD_HVB

VDD_LV


VDD_LV (1.25V) Decoupling. Place as close as possible to pin.

Ballast Transistor

Flash


LP Internal Reg Cap




(low ESR)

(lowESR)

(lowESR)


(lowESR)

(lowESR)

(lowESR) (low

ESR)(low ESR)




- 2 Fewer VDD_HV_A capacitor pairs- 1 fewer VDD_HV_B capacitor pair- No VDD_HV_C capacitor pairs- 5 fewer VDD_LV capacitor pairs

ADC0_CAP

ADC0_GND

ADC1REF_CAP

ADC1_GND

ADC1_CAP

ADC1_GND

GND

HVA_CAP

GND

HVB_CAP

LV_CAP

GND

HVFLA_CAP

GND

LV_CAPB_CAP E_CAP

GND

LVDEC_CAP

GND

E_CAP

GND

Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B



3 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B



3 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B



3 8


C250.1UF

C92.2UFDNP

C431000pF

C461000pF

C401.0 UF

C470.1UF

C350.1UF

C280.68uFDNP

C420.1UF

+ C210UF

C450.1UF

C441.0 UF

C290.1UF

C7 4700pF

C32

1000pF

+ C110UFDNP

C341000pF

C82.2UFDNP

+C310UFDNP

C220.1UF

C48470pF

+C410UFDNP

C210.68uF

C27470pF

C41

1000pF

C300.68uF

C260.1UF

C23470pF

C370.1UF

C500.1UF


C200.1UF

C490.68uF


C331.0 UF

C241000pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A




(LIN0_RX)(LIN0_TX)

(LIN1_TX)(LIN1_RX)

(XTAL32)(EXTAL32)

(FR_A_TX)


(FR_B_TX_EN)

(FR_B_RX)(FR_B_TX)

(USB1_CLK)

(USB1_D0)(USB1_D1)

(USB1_D2)(USB1_D3)

(USB1_D4)(USB1_D5)

(USB1_D6)(USB1_D7)

(USB1_DIR)



(MII_RXD3)(MII_CRS)



(RMII_TXEN)




(MII_RXCLK)


(SD_CMD)(SD_CLK)

(SD_WP)


(SAI0_SYNC)


(TDI)(TDO)

(TCK)(TMS)


(MLB_DN)

(MLB_DP)

(MLB_SN)

(MLB_SP / DAT)

(MLB_CN / SIG)





(CMP1_8 / IO)

(CMP1_10 / IO)

(CMP1_11 /IO)

(CMP1_12 / IO)

(CMP1_13 / IO)

(CMP1_14 / IO)(CMP1_15 / IO)

(CLKOUT1 GPIO)

(GPIO)

(GPIO)




(MLB_RST)(MLB_PWR)

(MLB_IRQ - WKPU21)



(CLKOUT0 GPIO)



(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(GPIO)

(CAN0_TX)(CAN0_RX)

(SW4 & GPIO)

(CAN1_RX)(CAN1_TX)

(SW3 & GPIO)


(SD_CD - WKPU19)

(GPIO)(GPIO)(GPIO)



WKPU22

WKPU15


- Port D 11 Not on 176QFP


(GPIO & MLB_ST)

PA0PA1

PA3PA2

PA4PA5

PA7PA6

PA8PA9

PA11PA10

PA12PA13

PA15PA14

PB0PB1

PB3PB2

PB4PB5

PB7PB6

PB8PB9

PB11PB10

PB12PB13

PB15PB14

PC0PC1

PC3PC2

PC4PC5

PC7PC6

PC8PC9

PC11PC10

PC12PC13

PC15PC14

PD0PD1

PD3PD2

PD4PD5

PD7PD6

PD8PD9PD10

PD12PD13

PD15PD14

PE0PE1

PE3PE2

PE4PE5

PE7PE6

PE8PE9

PE11PE10

PE12PE13

PE15PE14

PF0PF1

PF3PF2

PF4PF5

PF7PF6

PF8PF9

PF11PF10

PF12PF13

PF15PF14

PG0PG1

PG3PG2

PG4PG5

PG7PG6

PG8PG9

PG11PG10

PG12PG13

PG15PG14

PH0PH1

PH3PH2

PH4PH5

PH7PH6

PH8PH9

PH11PH10

PH12PH13

PH15PH14

MCU-EXTALMCU-XTAL

PORSTxMCU-RSTx

PH0 7

PORSTx8MCU-RSTx8

MCU-EXTAL6MCU-XTAL6

PB08PB18PB28PB38





PA58


PB58PB48



PC58PC48

PC08PC18PC28PC38

PD128PD138PD147PD157


PD58PD48

PD08PD18PD28PD38





Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G GPIO 1of2

4 8


MPC5748G 176QFPPackage 1of3 GPIO Pins1

U1A

PPC5748GSK0MKU6 + OTQ-176SG-0.5-004-00

RESET29

PORST153

XTAL56

EXTAL58

PA024

PA119

PA217

PA3114

PA451

PA5146

PA6147

PA7128

PA8129

PA9130

PA10131

PA11132

PA1253

PA1352

PA1450

PA1548

PB039

PB140

PB2176

PB31

PB488

PB591

PB692

PB793

PB861

PB960

PB1062

PB1196

PB12101

PB13103

PB14105

PB15107

PC0154

PC1149

PC2145

PC3144

PC4159

PC5158

PC644

PC745

PC8175

PC92

PC1036

PC1135

PC12173

PC13174

PC143

PC154

PD077

PD178

PD279

PD380

PD481

PD582

PD683

PD784

PD887

PD994

PD1095

PD12100

PD13102

PD14104

PD15106

PE018

PE120

PE2156

PE3157

PE4160

PE5161

PE6167

PE7168

PE821

PE922

PE1023

PE1125

PE12133

PE13127

PE14136

PE15137

PF063

PF164

PF265

PF366

PF467

PF568

PF669

PF770

PF842

PF941

PF1046

PF1147

PF1243

PF1349

PF14126

PF15125

PG0122

PG1121

PG216

PG315

PG414

PG513

PG638

PG737

PG834

PG933

PG10138

PG11139

PG12116

PG13115

PG14134

PG15135

PH0117

PH1118

PH2119

PH3120

PH4162

PH5163

PH6164

PH7165

PH8166

PH9155

PH10148

PH11140

PH12141

PH139

PH1410

PH158

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A





(SAI2_D0)

(SAI2_BCLK)

(SAI2_MCLK)

(SAI2_SYNC)

(MLB_CP / CLK)(GPIO)

(GPIO)


(ENET_RST)








- 2 fewer pins on Port I- 12 fewer pins on Port J- No Ports K to Q

(And corresponding changesto daughtercard connectors)

(GPIO & MLB_PS0)(GPIO & MLB_PS1)

PI0PI1

PI3PI2

PI4PI5

PI7PI6

PI8

PI11PI12PI13

PI15PI14

PJ0PJ1

PJ3PJ2

PJ4


PI68PI78PI87

PI58



Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


MPC5748G GPIO 2of2

5 8


MPC5748G 176QFPPackage 3of3 GPIO Pins2

U1C

PPC5748GSK0MKU6 + OTQ-176SG-0.5-004-00

PI0172

PI1171

PI2170

PI3169

PI4143

PI5142

PI611

PI712

PI8108

PI11111

PI12112

PI13113

PI1476

PI1575

PJ074

PJ173

PJ272

PJ371

PJ45

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


(XTAL32)

(EXTAL32)




Clocks

EXTAL

MCU-XTAL

PB8

MCU-EXTALXTAL

PB9

EXT-CLK

GND

GND

GNDMCU-XTAL4

PB84

PB94

MCU-EXTAL4

EXT-CLK8

Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B


Clocks

6 8


J11

2

3

C6 12PF

C38 12PF

R35 0

DNP

R71.0MDNP

Y2032.768KHZ

12

C39 12PF

R301.0MDNP

Y140.0MHZ

12

J2

1

2

3

C5 12PF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A










MLB Termination



PB14

PD15

PB13

PD14

PI8

MLB_SN

MLB_SP

MLB_DN

MLB_DP

MLB_CN

MLB_CP

PB15


PH2PH1

PG12PH0

PG13

PH2-RPH1-RPH0-R

PG13-RPG12-R

PG0-RPG0

PI85

PB144

PB154

PB134


MLB_SN 8

MLB_SP 8

MLB_DN 8

MLB_DP 8

MLB_CN 8

MLB_CP 8



PG0-R 8PG04

PD154

PD144

Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B



7 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B



7 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


B



7 8


R2 50

R24 0

R33 0

R22 0R23 100 1%

R34100DNP

R5 50

R32 105.0 1%

R1 50

R6 50

R21100DNP

R26 0R28 105.0 1%

R4 50

R25100DNP

R3 50

R29 0

R31 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


Notes:

- there was no neat way to fit these connectors onto a B sized sheet so unfortunately thesheet size has been increased to C so will need to be printed on larger paper.

- The Crystal Signals are NOT routed via the daughtercard connectors- The Specific MCU power pins are not routed via the daughter card however the jumpered MCUsupply lines are brought up from the main board (see the top pins of the connector on theleft)

- The connector schematic symbols have been horizontally mirrored so they match the main EVBconnector. This has no bearing on the PCB placement or footprint. Pin1 on the recepticlemates with pin 1 on the plug.

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(PK9)

(PK11)

(PK14)(PK12)

(PP8)(PP11)

(PP3)

(PL0)

(PO1)

(PP4)

(PO11)(PO8)

(PO13)

(PO15)

(PP1)

(PO6)

(PN15)(PO3)

(PO2)

(PN12)

(PN8)

(PN7)

(PK1)

(PN4)

(PK3)(PK5)

(PN5)

(PK7)

(PN2)

(PJ12)

(PJ15)

(PJ14)

(PN3)

(PK15)

(PN6)

(PN0)

(PP10)(PP5)

(PO0)

(PP2)

(PK2)

(PP7)

(PK4)(PK6)

(PP6)

(PK8)

(PJ11)

(PP9)

(PJ10)

(PO12)

(PK0)

(PO7)

(PJ9)

(PO10)

(PJ13)

(PO4)(PO9)

(PO14)

(PP0)

(PO5)

(PN14)

(PN13)

(PN11)

(PN9)

(PK10)

(PN10)

(PK13)

(GND)

(GND) (GND)

(GND)

Plug

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(PM15)

(PM3)

(PM12)

(PM14)

(PQ0)

(PL9)

(PM4)

(PQ4)

(PL1)

(PL3)

(PQ5)

(PM5)

(PQ7)

(PJ5)

(PL12)

(PP15)

(PJ7)

(GND)

(GND)(GND)(GND)

(GND) (GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

Plug

(GND)(GND)

(PQ3)

(PL11)(PL6)

(PD11)

(PQ1)

(PJ6)

(PJ8)

(PQ2)

(PL7)

(PL15)

(PI10)

(PQ6)

(PI9)

(PM2)(PM1)

(PL8)

(PL4)

(PL10)

(PL13)(PL5)

(PM9)(PL14)

(PM0)

(PM8) (PM10)

(PM7)

(PM6)

(PP13)

(PP14)

(PP12)

(PM13)

(PN1)

(PM11)

(PL2)


PE6PI3

PI1PI2

PC13PI0

PB2

EXT-CLK

MCU_3V3_S

MCU_3V3_LMCU_5V0_L

PB3

PA12

PF0PF1

PH8

PH7PH6

PE7

PC12

PA13

PC8

PC9

PC15

PC14PJ4

PF10

PH14

PG5PH13PG4

PI7 PH15

PE10PE1 PE0PI6

PE11 PG2

PC7

PG3 PA2PE9

PE8 PA1MCU-RSTx

PF8PC6

PG9

PF13

PA0

MCU_5V0_S

MCU_1V25_L

PG7 PG6PG8 PC11PC10

PB0

PB10

PA15

PA4

PB1PF12

PF11

PF9PA14

PF3

PF4PF7

PE5

PG14

PC5

PI5 PC3PE4

PC2

PC0

PH2-R

PA8PA9

PF14PG0-R

PG1

PA7

PA10

PE13PF15

PE12PA11

PA3PH0-RPH1-R

PH9

PG13-RPG12-R

PI13

PC1

PB12

PH10PH5PH4PE3

PE15PH12

PG10

PG11

PE14

PH11

PORSTxPC4

PG15

PE2

PA5

PA6

PI4

PF5

PJ2PJ3

PD8

PF2

PB4

PD7

PB5PD5

PJ0

PB11PD1PJ1

MLB_DPMLB_DN

PB6PD0

PD4PF6

PI14

PD2PD6

PD3

MLB_CPMLB_DAT

MLB_CLK

MLB_CN

MLB_SN

MLB_SIG

MLB_SP

PH3

PI11PI12PD9

PD12

PI15

PD13

PB7PD10

DC_5V0_S

DC_P12VDC_1V25_L DC_5V0_L

DC_3V3_L

DC_3V3_S

GND GNDGNDGND

PC154

PG54

PI75

PE14PI65

PE114PG34

PE84

PG94PA04

PG74PG84PC104

PB14

PF94PA144

PE64PI35

PA44

PI15PI25

PC134PI05

PA154

PB24

PB104

EXT-CLK6

MCU_3V3_S 2


PA12 4

PF1 4PF0 4

PA13 4

PF10 4

PC7 4

PF8 4PC6 4

PF134

MCU_5V0_S2

MCU_1V25_L2

PH7 4PH6 4PB3 4PH8 4

PE7 4

PC12 4

PC9 4

PC14 4PJ4 5

PH14 4

PH13 4PG4 4PH15 4

PE10 4PE0 4


PG6 4PC11 4

PB0 4

PF12 4

PF11 4

PC84

PF4 4PF7 4PF3 4

PC0 4

PH9 4

MLB_DP 7MLB_DN 7

PC1 4

PH5 4PE3 4

PE4 4PC3 4

PE15 4PORSTx 4PE2 4

PG11 4

PG10 4

PI4 5

PA9 4PA10 4

PA8 4

PG0-R 7PF14 4

PG12-R 7

PH2-R 7

PG13-R 7

PB12 4PI13 5

PD9 4

PB7 4PI12 5

MLB_CN 7

PI15 5

MLB_CP 7

PI14 5

PD6 4

PD3 4PD2 4

PD0 4PB6 4

PF6 4PD4 4

PH104

PE54PH44

PI55

PG144

PC54

PH124PC44

PC24PA64

PA54PH114

PE144

PG154

PE124PA114

PE134PA74

PG14PF154

PH1-R7

PA34PH0-R7

PH34

PD124PD134

PI115

MLB_DAT7

PD104

MLB_CLK7MLB_SIG7

MLB_SN7

PD74

MLB_SP7

PD54

PJ05

PB114PB54

PJ15PD14

PD84

PF54PB44

PJ35PJ25

PF24

Drawing Title:


Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


C



8 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


C



8 8



Date: Sheet of

Page Title:


SCH-27898 PDF: SPF-27898 D1


C



8 8


TPV4

TPV6TPV5

TPV1

P21

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12

TPV3

P20

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12TPV2

100 QFP DC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B


X2


GPIO - MPC5746C GPIO pins 1 of 2

Clocks

Sheet 8


GPIO - MPC5746C GPIO pins 2 of 2

Table Of Contents:

MPC5746C Customer EVB 100 BGA Daughter Card (MPC574XG-100DS)

X1Power - MPC5746C power pins footprintPower - MPC5746C Decoupling Capacitors


05 Jan 2014 Alasdair Robertson Initial release sent for review based on X-MPC574XG-256DS RevA

These schematics are provided for reference purposes only. As such,Freescale does not make any warranty, implied or otherwise, as to thesuitability of circuit design or component selection (type or value) used inthese schematics for hardware design using the Freescale MPC5746C familyof Microprocessors. Customers using any part of these schematics as abasis for hardware design, do so at their own risk and Freescale does notassume any liability for such a hardware design.



Caution:


07 Jan 2014 Alasdair Robertson Post review corrections incl MCU Orcad Footprint30 Jan 2014 Alasdair Robertson Prototype build releaseA

A1 18 Aug 2015 Alasdair Robertson Tidy up Schematics for UM (RevA PCB)

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-28701 PDF: SPF-28701 A1

MPC5746C 100 BGA Daughter Card

B



A. Robertson

A. Robertson

A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-28701 PDF: SPF-28701 A1


B



A. Robertson

A. Robertson

A. Robertson

1 8


Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-28701 PDF: SPF-28701 A1


B



A. Robertson

A. Robertson

A. Robertson

1 8


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


3v3




3v3 5v0 5v0 5v0 5v03v3 3v3

3v3

3v3 5v0

MPC5746C MCU Power ConnectionsCaution:


- Don't attempt to over drive an analogue pad to 5Vwhen the digital VDD_HV_x supply is set to 3.3V. Thiswill trigger the ESD protectrion on that pad. Forexample if VDD_HV_A is set to 3.3V and the analoguesupplies are set to 5V, you cannot drive 5V into apad in the VDD_HV_A domainFrom MCU

supplyjumpers onmain board

MCU_3V3_S

MCU_5V0_S

MCU_1V25_L

MCU_3V3_L

MCU_5V0_L

HVB

_CAP

HVF

LA_C

AP

LV_C

AP

ADC

0_C

AP

ADC

1_C

AP

ADC

1REF

_CAP


HVA

_CAP


E_C

AP

B_C

AP

LVD

EC_C

AP

GND

HVA_CAP

GND

MCU_1V25_L8

MCU_5V0_S8

MCU_3V3_S8

MCU_5V0_L8

MCU_3V3_L8

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C MCU Power

2 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C MCU Power

2 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C MCU Power

2 8


R350

J9

1

2

3

R371.0K

J8HDR 1X2

12

R24 0

J5

1

2

3

R7 0

R10 0

1.25v Core & External BallastAnalogue MPC5746C 100 BGAPackage 2of3 Power Pins

Flash

U1B

SKT BGA 100 TH + MPC574XG-100

VRC

_CTR

LE1

VSS_

D1

D1

VSS_

E4E4

VSS_

E5E5

VSS_

E6E6

VSS_

E7E7

VSS_

F4F4

VSS_

F5F5

VSS_

F6F6

VSS_

F7F7

VSS_

K4K4

VSS_

K7K7

INT_

BAL_

SEL

E2

VDD

_LV_

D5

D5

VDD

_LV_

D6

D6

VDD

_LV_

G5

G5

VDD

_LV_

G6

G6

VDD

_HV_

A_D

4D

4

VDD

_HV_

A_G

4G

4VD

D_H

V_A_

D7

D7

VDD

_HV_

B_E8

E8

VSS_

HV_

ADC

0K9

VDD

_HV_

ADC

0K1

0

VDD

_HV_

ADC

1G

10VS

S_H

V_AD

C1

H10

VDD

_HV_

FLA_

H3

H3

VDD

_HV_

ADC

1_R

EFH

9

VDD

_LP_

DEC

F2

VSS_

VPP

D2

VDD

_HV_

A_G

7G

7

Q20MJD31CT4

34

1

J3

1

2

3

J10

1

2

3

TPH21

J4

1

2

3

TPH1

1

J6

1

2

3

R9 0

J12

1

2

3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Capacitor Types:





ADC


VDD_HVA VDD_HVB

VDD_LV

VDD_LV (1.25V) Decoupling. Place -.1uFcaps as close as possible to respectiveVDD_LV pins

Ballast Transistor

Flash

MPC5746C MCU Decoupling and bulk storage

LP Internal Reg Cap

Place closeto transistor


(low ESR)

(lowESR)

(lowESR)


(lowESR)

(lowESR)

(lowESR) (low

ESR)(low ESR)

2.2uF caps areDNP. Place closeto emitter One of these is DNP to keep overall capacitance less

than max spec of 3uF. If necessary, these can bereplaced with 0.47uF caps as long as combined ESR of allcaps is less than 0.03 Ohms

ADC0_CAP

ADC0_GND

ADC1REF_CAP

ADC1_GND

ADC1_CAP

ADC1_GND

GND

HVA_CAP

GND

HVB_CAP

LV_CAP

GND

HVFLA_CAP

GND

LV_CAPB_CAP E_CAP

GND

LVDEC_CAP

GND

E_CAP

GND

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C MCU Decoupling

3 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B



3 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B



3 8


C520.1UF

C102.2UFDNP

C481000pF

C541000pF

C571.0 UF

C230.1UF

C550.1UF

C200.68uFDNP

C560.1UF

+ C110UF

C530.1UF

C591.0 UF

C390.1UF

C8 4700pF

C36

1000pF

+ C410UFDNP

C461000pF

C92.2UFDNP

+C310UFDNP

C350.1UF

C22470pF

+C210UFDNP

C310.68uF

C27470pF

C47

1000pF

C600.68uF

C260.1UF

C33470pF

C320.1UF

C240.1UF


C490.1UF

C290.68uF


C581.0 UF

C511000pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MPC5746C GPIO 1 of 2



(FR_A_TX)


(USB1_D0)(USB1_D1)

(USB1_D3)

(USB1_D5)

(USB1_D7)



(MII_RXD3)



(RMII_TXEN)




(MII_RXCLK)

(SAI0_D0)

(SAI0_MCLK)

(SAI0_SYNC)

(TDI)(TDO)

(TCK)(TMS)

Black - Clock, Reset and Control (SAI_I2C2_SCL)(SAI_I2C2_SDA)


(CMP1_8 / IO)

(CMP1_10 / IO)(CMP1_12 / IO)

(CMP1_13 / IO)

(CMP1_14 / IO)(CMP1_15 / IO)

(CLKOUT1 GPIO)

(GPIO)

(HEX2 & GPIO)


(LED1 & GPIO)(LED2 & GPIO)



(CLKOUT0 GPIO)

(CAN0_TX)(CAN0_RX)

(CAN1_RX)(CAN1_TX)

(SW3 & GPIO)

(SD_CD - WKPU19)

(eMIOS E1UC_11_H)(eMIOS E1UC_12_H)


WKPU22


(GPIO & MLB_ST)

PA0PA1

PA3PA2

PA4PA5

PA7PA6

PA8PA9

PA11PA10

PA12PA13

PA15PA14

PB0PB1

PC0PC1

PC5

PD1

PE3PE2

PE8PE9

PE13

PE15

PF0

PF5

PF8PF9PF10

PF15PF14

PG0PG1

PG3PG2

PG7PG6

PG11PG12PG13

PG15PG14

PH0PH1PH2

PH9PH10

PH12

PORSTx

PB10

PD13

PC10PC11

MCU-XTALMCU-EXTAL

MCU-RSTx

PH0 7

PORSTx8MCU-RSTx8

MCU-EXTAL6MCU-XTAL6

PB08PB18

PB108



PA58


PC118PC108

PC58

PC08PC18

PD138

PD18 PH1 7PH2 7

PH9 8PH10 8

PH12 8

PG0 7PG1 8PG2 8PG3 8

PG6 8PG7 8

PG11 8PG12 7PG13 7PG14 8PG15 8

PF0 8

PF5 8

PF8 8PF9 8PF10 8

PF14 8PF15 8

PE2 8PE3 8

PE8 8PE9 8

PE13 8

PE15 8

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C GPIO 1of2

4 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C GPIO 1of2

4 8


MPC5746C 100 BGAPackage 1of3 GPIO Pins1

U1A


RESETF1

PORSTA4

XTALK5

EXTALK6

PA0H4

PA1G3

PA2F3

PA3C10

PA4J3

PA5A5

PA6B4

PA7A10

PA8B10

PA9B9

PA10B8

PA11C8

PA12J7

PA13J6

PA14J5

PA15J4

PB0H2

PB1H1

PB10K8

PC0/TDIC5

PC1/TDOC6

PC5E3

PC11G1

PD1J10

PD13G9

PE2C3

PE3D3

PE8C2

PE9C1

PE13A9

PE15A6

PF0J8

PF5G8

PF8J2

PF9J1

PF10K1

PF14D9

PF15A8

PG0F9

PG1F10

PG2B1

PG3B2

PG6H6

PG7H5

PG11B6

PG12D10

PG13D8

PG14A7

PG15B7

PH0E10

PH1E9

PH2C9

TMS/PH10C7

PH12B5

PC10G2

TCK/PH9C4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MPC5746C GPIO 2 of 2


(SAI1_D0)

(SAI2_D0)

(SAI2_BCLK)(SAI2_SYNC)

(GPIO)(GPIO)







PI0PI1

PI3PI2

PI14

PJ0PJ1PJ2

PJ13PJ14

PI148

PI08PI18PI28PI38

PJ138PJ148

PJ08PJ18PJ28

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C GPIO 2of2

5 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


MPC5746C GPIO 2of2

5 8


MPC5746C 100 BGAPackage 3of3 GPIO Pins2

U1C


PI0A1

PI1A2

PI2B3

PI3A3

PI14J9

PJ0F8

PJ1H8

PJ2H7

PJ13K3

PJ14K2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A




Clocks

(Note the 32KHz oscpins are not bondedout on the 100 pinpackage)

EXTAL

MCU-XTAL

MCU-EXTALXTAL

EXT-CLK

GND

GNDMCU-XTAL4

MCU-EXTAL4

EXT-CLK8

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


Clocks

6 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B


Clocks

6 8


J11

2

3

C7 12PF

R34 0

DNP

Y140.0MHZ

12

R81.0MDNP

J2

1

2

3

C6 12PF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A




PH2PH1

PG12PH0

PG13

PH2-RPH1-RPH0-R

PG13-RPG12-R

PG0-RPG0



PG0-R 8PG04

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B



7 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B



7 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


B



7 8


R1 50

R4 50

R2 50

R5 50R6 50

R3 50

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


Notes:

- there was no neat way to fit these connectors onto a B sized sheet so unfortunately the sheetsize has been increased to C so will need to be printed on larger paper.

- The Crystal Signals are NOT routed via the daughtercard connectors- The Specific MCU power pins are not routed via the daughter card however the jumpered MCUsupply lines are brought up from the main board (see the top pins of the connector on the left)

- The connector schematic symbols have been horizontally mirrored so they match the main EVBconnector. This has no bearing on the PCB placement or footprint. Pin1 on the recepticle mateswith pin 1 on the plug.


(PO12)

(PO3)

(PO2)

(PO7)

(PN12)

(PO10)

(PN8)

(PO4)

(PN7)

(PO9)

(PN4)

(PO14)

(PN5)

(PP0)

(PN2)

(PO5)

(PN14)

(PN13)

(PN11)

(PN9)

(PN10)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

Plug

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(PN3)(PN6)

(PN0)

(PP8)(PP11)

(PP3)(PP10)

(PP4)

(PP5)

(PO11)

(PP2)

(PO8)

(PP7)

(PO13)

(PP6)

(PO15)

(PP1)

(PO6)

(PP9)

(PN15)

(PL11)(PL6)(PL7)

(PL15)(PM1)(PM2)

(PL4)

(PL8)

(PL10)

(PL5)(PL13)(PM0)

(PL14)(PM9)(PM7)

(PM10)(PM8)

(PM6)(PM13)

(PN1)

(PM11)

(PL2)

(PM15)

(PM12)

(PL9)

(PL3)

(PL12)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

Plug

(GND)(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(GND)

(GND)

(GND)

(GND)(GND)

(PB2)

(PE6)

(PC13)

(PK10)(PC8)(PK13)

(PK15)(PC15)

(PG5)

(PD0)(PI7)

(PE1)(PI6)

(PE11)

(PG9)

(PG8)

(PK2)

(PF13)(PK4)(PK6)(PK8)

(PJ11)(PJ10)(PK0)(PJ9)

(PH7)(PH6)(PB3)(PH8)

(PE7)(PK9)

(PC12)(PK11)

(PK14)(PK12)(PC9)(PL0)

(PC14)(PJ4)

(PH14)

(PO1)(PH13)(PG4)(PH15)

(PE10)(PE0)

(PK1)(PF12)

(PK3)(PK5)(PF11)

(PK7)(PC6)

(PC7)

(PJ12)

(PJ15)

(PF1)

(PH4)(PE5)

(PI5)(PQ0)

(PC4)

(PC2)

(PH11)

(PE14)(PQ4)

(PQ5)(PQ7)(PP15)

(PE12)

(PH3)(PM3)

(PM14)

(PD12)(PI11)(PD10)

(MLB_DAT)(MLB_SIG)(MLB_CLK)

(MLB_SN)

(MLB_SP_

(MLB_SP)

(PD7)(PJ5)

(PD5)(PB5)(PB11)

(PD8)(PI9)

(PB4)

(PJ3)

(PF2)

(PH5)

(PQ3)(PC3)(PE4)

(PQ1)

(PG10)(PQ2)

(PQ6)

(PP13)(PP12)(PI4)(PP14)

(PM4)(PL1)

(PM5)(PI13)(PB12)(PD9)(PI12)(PB7)(PI15)

(MLB_CN)(MLB_CP)

(MLB_DN)(MLB_DP)

(PJ7)(PD11)(PJ6)(PD6)(PD2)(PD3)(PJ8)

(PB6)(PD0)(PI10)

(PD4)(PF6)

(PF4)(PF7)(PF3)

PG3

PE8

PA0

MCU_5V0_S

MCU_1V25_L

PB10

PA15

PA4PJ13

PF9PA14

PI3

PI1PI2

PI0

EXT-CLK

PA12

PF0

PA13

PG2PA2PE9PA1MCU-RSTx

PF8

PG6PC11

PB0

MCU_3V3_S

PG7

PC10

PB1

PF10

PJ14

MCU_3V3_LMCU_5V0_L

PC0

PG14

PC5

PA7

PG1PF15PE13

PA11

PH1-RPH0-RPA3

PH10

PH12

PG15

PA6

PA5

PF5

PJ2

PJ0

PJ1PD1

PD13

DC_5V0_S

DC_P12VDC_1V25_L

PA8

PH2-RPG0-RPF14

PA9PA10

PG12-RPG13-R

PC1PE3

PE15

PG11

PORSTxPE2

PI14

DC_3V3_S

DC_5V0_LDC_3V3_L

PH9

GND GNDGND GND


MCU_5V0_S2

MCU_1V25_L2

MCU_3V3_S 2


PG6 4PC11 4

PB0 4

PF8 4

PF10 4

PJ14 5

PA13 4

PA12 4

PF0 4

PI35

PI15PI25

PI05

PG34

PE84

PA04

PG74

PC104

PB14

PF94PA144

PJ135PA44

PA154

PB104

EXT-CLK6PH104

PC54

PG144PH124

PA64

PA54

PG154

PA114


PD134

PJ05

PD14PJ15

PF54

PJ25

PC0 4

PC1 4PE3 4

PE15 4PORSTx 4PE2 4

PG11 4

PA10 4PA9 4PA8 4PF14 4PG0-R 7PH2-R 7

PG12-R 7PG13-R 7

PH9 4

PI14 5

Drawing Title:


Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


C



8 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


C



8 8



Date: Sheet of

Page Title:


SCH-28701 PDF: SPF-28701 A1


C



8 8


TPV6TPV2

TPV1

TPV3

P20

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12

TPV4

TPV5

P21

PLUG 180

2SH1SH2

SH5SH6

14365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952515453565558576059SH3SH4

626164636665686770697271747376757877807982818483868588879089929194939695989710099102101104103106105108107110109112111114113116115118117120119SH7SH8

SH9SH10122121124123126125128127130129132131134133136135138137140139142141144143146145148147150149152151154153156155158157160159162161164163166165168167170169172171174173176175178177180179SH11SH12

Document Number: MPC5748GEVBUG Rev. 0

08/2015

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document. Freescale reserves the right to make changes without

further notice to any products herein.

Freescale makes no warranty, representation, or guarantee regarding the suitability

of its products for any particular purpose, nor does Freescale assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale data

sheets and/or specifications can and do vary in different applications, and actual

performance may vary over time. All operating parameters, including “typicals,”

must be validated for each customer application by customer's technical experts.

Freescale does not convey any license under its patent rights nor the rights of others.

Freescale sells products pursuant to standard terms and conditions of sale, which can

be found at the following address: freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of

their respective owners. The Power Architecture and Power.org word marks and the

Power and Power.org logos and related marks are trademarks and service marks

licensed by Power.org.

© 2015 Freescale Semiconductor, Inc.

http://www.freescale.com/

http://www.freescale.com/support

Documents

MPC5748GEVBUG, MPC5748G EVB User Guide · The EVB has connectors for various peripheral daughtercards (for example MLB) that provide ... MPC5748G EVB User Guide, User Guide, Rev