1

COM 353 MicroprocessorsLecture 3

COM 353 MicroprocessorsLecture 3

Prof. Dr. Halûk Gümüşkayahaluk.gumuskaya@gediz.edu.tr

haluk@gumuskaya.com http://www.gumuskaya.com

Computer Engineering Department

Tuesday, October 23, 2012

Introduction to8-bit MicroprocessorArchitecture and Operation

1. Basic Microprocessor System Concepts2. Microprocessor Architecture and Operation3. Intel 8085 Microprocessor4. 8085 Microprocessor Based System5. Isolated I/O Using IN and OUT Instructions6. Memory Mapped I/O7. Programmable I/O and 8255

A Microprocessor Based System

I

SİSTEM YOLU

3-durumlu buffer Latch, FF

8255, 82568253 (8254)8251825782598279, ...

RWMROM Giriş(Temel)

Çıkış(Temel)

ProgramlanabilirGiriş/ÇıkışBirimleri

A collection of addressable registers:• Those registers reside within the microprocessor are internal registers,• and those exist in the ROM, RWM, and I/O ports are external registers.

Typical Partial Set of System Bus Signals

Name Function Number Direction*

A31–A0 Address bus 16, 20, 24, 32, 36 Output

D63–D0 Data bus 8, 16, 32, 64 Bidirectional

RD Generalized read strobe 1 Output

WR Generalized write strobe 1 Output

IO/M Status (I/O or memory reference) 1 Output

MEMR Memory read strobe 1 Output

MEMW Memory write strobe 1 Output

IOR Input device read strobe 1 Output

IOW Output device write strobe 1 Output

RESET System reset out 1 Output

* Direction is specified with respect to the microprocessor.

3 Buses of a P-Based System

ALU

Çip-üzeri yollar

Hafıza I/O I/O

CPU

Yerel Sistem Yolu

Harici Sistem Yolu

Saklayıcılar

Mikroişlemcili Sistem

Simple Input Port for a P-Based System

3-DurumluBuffer

Giriş Port'u

Cihaz SeçmeLojiği

LatchGiriş Cihazı

E

Veri TutturmaDarbesi

Giriş CihazıSeçme Darbesi

Sistem VeriYolu

D0D1

Dm

A0A1

An

RDIO / M

Simple Output Port for a P-Based System

Latch

Çıkış Port'u

Cihaz SeçmeLojiği

Çıkış Cihazı

Çıkış CihazıSeçme Darbesi

Sistem VeriYolu

D0D1

Dm

A0A1

An

WRIO / M

1. Basic Microprocessor System Concepts

2. Microprocessor Architecture and Operation3. Intel 8085 Microprocessor4. 8085 Microprocessor Based System5. Isolated I/O Using IN and OUT Instructions6. Memory Mapped I/O7. Programmable I/O and 8255

Internal Architecture

Genel AmaçlıSaklayıcılar

R0

R1

R2

R3

R3

SR (Status Register)

IR (Instruction Register)

IP (Instruction Pointer)

SP (Stack Pointer)

MAR (Memory Address Register)

MBR (Memory Buffer Register)

ALU(Arithmetic Logic Unit)

Kontrol Birimi

Teknolojinin gelişmesiyle eklenendiğer donanım ve yazılım

(FPU, hafıza yönetim birimi,cache, ...)

Özel AmaçlıSaklayıcılar

1. Control Unit

2. General Purpose Registers

3. Special Purpose Registers

4. Arithmetic Logic Unit

5. Other Special Units

1. Control Unit

KontrolBirimi

Saat

HariciKontrolGirişleri

HariciKontrolÇıkışları

KomutKod Çözücü

IR

DahiliSaklayıcılaraKontrol Sinyalleri

Bayraklar

MBR

Dahili Veri Yolu

Harici Veri Yolu

Komut Saklayıcısı

It controls and synchronizes all data transfers and transformations in the microprocessor system.

The output of the IR is decoded and used by the control unit to develop a sequence of microoperations (microistructions) and register transfers that execute the instruction.

Simplified States of Control Unit

KomutOkuma(Fetch)

Yürütme(Execute)

Durma(Halt)

Komut mikroişlemcide

Komut yürütmesi biter

RESET

RESET

Donanım sıfırlamasıolmadığı sürece dur

Durma (HALT)Komutu

Fetch Decode Execute Cycles

InstructionFetch

InstructionDecode

OperandFetch

Execute

ResultStore

NextInstruction

Read an instruction from memory

Determine required operations

Locate and obtain operand data

Compute result value or status

Write results to memory for later use

Determine next instruction

2. General Purpose Registers

X86 registers

Intel 8085 registers

A (ACC)

The registers are used and operated upon either singly or in pairs

They are used for storage, arithmetic and logic operations (x86), and addressing purposes.

Halûk Gümüşkaya

3. Special Purpose Registers

X86 registers

• F (Flags) (8-bit status register, modified after an ALU operation)• PC (Program Counter – points to the next instruction to be executed in memory)• MAR (Memory Address Register)• MBR (Memory Buffer Register)• SP (Stack Pointer)

8085 registers

4. Arithmetic Logic Unit

ALU

A Temp. Reg

Flags

Internal Bus

ALU

AXBXCXDXDISIBPSP

Flags

8-bit ALU (8085) 16-bit ALU (8086/8088)

Arithmetic and logic operations on one or two 8-bit, 16-bit (x86), and 32-bit (x86) operands are performed in this unit.

5. Other Special Units FPU (Floating Point Unit) Cache Memory Memory Management Unit ….

External Architecture

Address Bus

Data Bus

Control Bus1. Bus control2. Bus status3. Interrupts4. Bus arbitration5. Coprocessor signaling6. Misc

The pins on a CPU chip Address Bus: Common address bus widths are 16, 20, 32, and 64

Data Bus: Common widths are 8, 16, 32, and 64.

Control Bus: The control pins regulate the flow and timing of data to and from the CPU and have other miscellaneous uses.

Control pins can be roughly grouped into the following major categories: Bus Control Interrupts Bus Arbitration Coprocessor Signalling Status Miscellaneous

Control Bus Bus Control: Mostly outputs from the CPU to the bus telling whether the

CPU wants to read or write memory or do something else. The CPU uses these pins to control the rest of the system.

Status: They show the status (i.e. bus operation, MEMR, IOW) of CPU.

Interrupts: They are inputs from I/O devices to the CPU.

Bus Arbitration: These pins regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time.

Coprocessor Signalling: Some CPU chips are designed to operate with coprocessors such as floating point chips, graphics or other chips.

Miscellaneous: CLK, XTAL, reset, power, …

1. Basic Microprocessor System Concepts2. Microprocessor Architecture and Operation

3. Intel 8085 Microprocessor4. 8085 Microprocessor Based System5. Isolated I/O Using IN and OUT Instructions6. Memory Mapped I/O7. Programmable I/O and 8255

Internal Architecture of 8085A

B C

D E

H L

SP

PC

MAR MAR / MBR

ALU

A Geçici Reg.

Bayraklar (F)

IR

Kesme Kontrol Seri I/O Kontrol

CLKÜretimi

Durum

S0 S1 IO/M

Kontrol

RD WR ALEREADY

X1

X2

CLKOUT

DMA

HOLD

RESET

HLDA RIN ROUT

Zamanlama ve Kontrol

TRAPRST7.5RST6.5RST5.5INTR

INTA

SID SOD

A15- A8Adres Yolu

AD7- AD0Adres/Veri Yolu

Komut KodÇözücü

External Architecture of 8085A

8085A

Vcc40

HLDACLK (OUT)RESET INREADY

S1RDWRALES0A15A14A13A12A11A10A9A8

39383736353433323130292827262524232221

HOLD X1 1

RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS

2 3 4 5 6 7 8 91011121314151617181920

X2 A15 - A0

D7 - D08

16

READY

TRAPRST 7.5

RESET IN

Yol Kontrol

Veri Yolu

Adres Yolu

Kesmeler

YolHakemliği

Yol DurumÇeşitli

8085ARDWR

IO/M

RST 6.5RST 5.5INTR

HOLDHLDA

RESET OUT

SIDSOD

S0

IO/M

S1

ALE

CLK

(a) (b)

INTA

X1X2

Multiplexing of Address/Data Pins of 8085A

A15 - A8 A15 - A8

AD7 - AD0 A7 - A0

ALE

74LS373

8085A

D7 - D0

A15 - A0

Adres Yolu

Veri Yolu

C OEAdresLatch'ı

8085A Based System Machine Cycles and Timing Machine cycle: The fetching and execution of a single instruction. It consists of one more read/write operations (references) to

memory or an I/O device.

There are 7 different types of machine cycles in the 8085: Opcode fetch Memory read – MEMR Memory write – MEMW I/O Read – IOR I/O Write – IOW Interrupt acknowledge Bus idle

Machine Cycle and State Information for the 8085A

Bus Status Bus Control

Machine Cycle IO/M S1 S0 RD WR INTA

Opcode fetch 0 1 1 0 1 1

Memory read 0 1 0 0 1 1

Memory write 0 0 1 1 0 1

I/O read 1 1 0 0 1 1

I/O write 1 0 1 1 0 1

Interrupt Ack. 1 1 1 1 1 0

Bus idle DAD 0 1 0 1 1 1

Ack. of RST, TRAP 1 1 1 1 1 1

HLT 3-state 0 0 3-state 3-state 1

3 status signals generated at the beginning of each machine cycle identify each type and remain valid for the duration of the cycle.

The Format of 8085 Instructions and Instruction Fetch Cycle

The instructions consist of 1 to 3 bytes. Therefore, instruction fetch is 1 to 3 machine cycles The first machine cycle in an instruction cycle is always an

OPCODE FETCH, and the 8-bits obtained during an OPCODE FETCH are always interpreted as the OP code of an instruction.

The total number of machine cycles required varies from 1 to 5, with no one instruction cycle containing more than 5 machine cycles.

Opcode Opcode

Operand

Opcode

Operand1

Operand2

(a) (b) (c)

(a) 1-byte (b) 2-byte (c) 3-byte 8085A instructions.

Execution of STA and LDA Instructions STA (Store Accumulator Direct) transfers the contents of ACC to an

external register (a memory register or a memory mapped output register) whose address is specified in the instruction.

The opcode for STA is 32h. This register can be located anywhere in the 64 K memory space that

the 8085 can directly address, 16-bits are required for the address. LDA (Load Accumulator Direct) does the reverse operation. It reads

from an external register to the ACC. The opcode is 3Ah.

3-byte STA and LDA instructions

İşlem Kodu

Düşük Adres

Yüksek Adres

byte 1

byte 2

byte 3

ADDR

ADDR + 1

ADDR + 2

STA veya LDAkomutu

Timing Values of 8085AH Microprocessor

Processor Crystal MHz (fc) State Time ns (T) ADD Instruction (s)

8085AH-1 11.976 167 0.6680

8085AH-2 10.000 200 0.8000

8085AH-1 6.250 320 1.2800

8085AH-1 6.144 325.5 1.3000

Execution of STA and LDA Instructions Activities Associated with the T-States of 8085A

T1 A memory or I/O device address is placed on the address/data bus (AD7-AD0) and address bus (A15-A0). An address latch enable, ALE, pulse is generated to facilitate latching the low order address bits on AD7-AD0. Status information is placed on IO/M, S1, and S0 to define the type of machine cycle. The halt flag is check.

T2 Ready and hold inputs are sampled. PC is incremented if machine cycle is part of an instruction fetch. In all machine cycles except BUS IDLE, one of the control strobes –RD, WR, or INTA-makes a 1 to 0 transition.

Tw (optional) This state is entered if the ready line is low. The states of the address, data and control signals remain the same as at the end of T2.

T3 An instruction byte or data byte is transfered to/from memory the microprocessor. The active control strobe makes a 0 to 1 transition.

T4 The contents of instruction register (IR) are decoded.

T5 - T6 These states are used to complete the execution of some instructions.

Each machine cycle is divided by system clock into a number of state transitions, or T states, which correspond to the period between two negative going transition of that clock.

T-States of LDA and STA Instructions

Machine Cycles T-States1. Opcode fetch 4

2. Memory read 3

3. Memory write 3

4. Memory write (STA) or read (LDA) 3

Total T-states for 4 machine cycles 13

For STA and LDA instructions, the number of T-states required for the execution is 13.

If the 8085 is operating at a 325.5 nS state time, the STA/LDA instruction cycle is executed in 4.23 S.

Execution of IN and OUT InstructionIN InputPort IN reads the contents of an input device located at InputPort to the

accumulator (ACC). The opcode for IN is DBh. InputPort is an 8-bit port address which is an operand in this instruction.

256 input ports are possible with this 8-bit port address.OUT OutputPort OUT does the reverse operation. It writes the contents of the ACC to the

output port located at OutputPort. OutputPort is also an 8-bit address. This means 256 possible output

ports. The opcode for OUT is D3h.

2-byte IN and OUT instructions

İşlem Kodu

Port Adresi

byte 1

byte 2

ADDR

ADDR + 1IN veya OUT

komutu

Execution of IN and OUT Instruction1. Basic Microprocessor System Concepts2. Microprocessor Architecture and Operation3. Intel 8085A Microprocessor

4. 8085 Microprocessor Based System5. Isolated I/O Using IN and OUT Instructions6. Memory Mapped I/O7. Programmable I/O and 8255

System Memory

The 8085 system has ROM and RWM memory modules, one input port (a simple 8-bit three-state buffer 74LS244) for reading switches, and one output port (74LS374) for driving a LED display.

Use the memory system example given in the first lecture. 4K8 EPROM ve 2K8 RWM EPROM starts from 0000h, after EPROM RWM starts.

ROM

0000h

FFFFh

4K

RWM

2K

58KBoş

0FFFh1000h

17FFh1800h

Memory Map

A15 - A12

0 0 0 00 0 0 0

A11 - A8

0 0 0 01 1 1 1

A7 - A4

0 0 0 01 1 1 1

A3 - A0

0 0 0 01 1 1 1

0000h0FFFh

4K ROM içinde birhafıza hücresini seçer

İlk 4K'lık bloğu seçer

0 0 0 10 0 0 1

0 0 0 00 1 1 1

0 0 0 01 1 1 1

0 0 0 01 1 1 1

1000h17FFh

2K RWM içinde birhafıza hücresini seçer

Üçüncü 2K'lık bloğuseçer

Address Bit Map

System Memory Using Full Decoding

27324K x 8

EPROM

A11 - A0 D7 - D0

RDCEOE

12

61162K x 8RWM

A11 - A0 D7 - D0

RDCSOE

11

WR WE

Veri Yolu

D7 - D0

74LS138

Y0Y1Y2Y3Y4Y5Y6Y7

CBA

G2BG2A

G1

07FFh-0000h

0FFFh-0800h

A11 - A0

A10 - A0

17FFh-1000hA11

A12

A13

A15

A14IO / M

A Simple Input Port at F0h (partial decoding)

+ 5 V

D7

D0

S7

1111000

1

74LS244Octal Buffer

OE

A4

A5

A6

Cihaz SeçmeDarbesi

+ 5 V

F0h AdresindekiGiriş Port'u

S0

RDIO / M

A7

Anahtar bilgisiF8h

A Simple Output Port at F1h (partial decoding)

74LS374Octal FF

OE

Cihaz SeçmeDarbesi

D7

D0

D7

D0

A0

A4

A5

WRIO / M+ 5 V

F1h AdresindekiÇıkış Port'u

A6

CLK

+ 5 V

A7

Simple System Test Program at ROM IN F0h ; F0h adresli giriş port'undan oku ((ACC) <- (F0h)).CMA ; Okunan verinin bit'lerini tersle ((ACC) = (ACC)').STA 1000h ; ACC'yi RAM'ın 1000h nolu hücresine yaz.LDA 1000h ; RAM'ın 1000h nolu hücresinden ACC'ye oku.OUT F1h ; F1h adresli çıkış port'una yaz ((ACC) -> (F1h)).HLT ; Program yürütmesini durdur.

Program Assembly and Machine Code

Address Machine Code Assembly Code0000 DB F0 IN F0h

0002 2F CMA

0003 32 00 10 STA 1000h

0006 3A 00 10 LDA 1000h

0009 D3 F1 OUT F1h

000B 76 HLT

DBh0000hADRES VERİ

F0h0001h2Fh0002h32h0003h00h0004h10h0005h3Ah0006h00h0007h10h0008hD3h0009hF1h000Ah76h000Bh

CMA

STA 1000h

LDA 1000h

IN F0h

OUT F1h

HLT

KOMUTLAR

Execution of In F0h Instruction

Execution of STA 1000h Instruction Execution of Program in the 8085 Simulator

Assembly Program and its Machine Code Registers

EPROM and RWM Input and Output Ports

1. Basic Microprocessor System Concepts2. Microprocessor Architecture and Operation3. Intel 8085A Microprocessor4. 8085 Microprocessor Based System

5. Isolated I/O Using IN and OUT Instructions6. Memory Mapped I/O7. Programmable I/O and 8255

Input and Output Address SpacesIN PortNumber instruction Read from an input port located at PortNumber to the accumulator

(ACC) [PortNumber]. PortNumber = 00h FFh: 256 input ports

OUT PortNumber instruction Write the contents of ACC to an output port located at PortNumber. Again 256 output ports.

I/O Decoding of Control Lines and Addresses The corresponding IO/M, RD, WR signals are generated when these

instructions are executed by the CPU. These signals and some address lines are used by the decoding logic to

access the I/O ports.

I/O Address Spaces and Ports Since there are 2 different instructions for I/O access, two different

address spaces exist for I/O operations. Totally 512 ports (8085)

1. Basic Microprocessor System Concepts2. Microprocessor Architecture and Operation3. Intel 8085A Microprocessor4. 8085 Microprocessor Based System5. Isolated I/O Using IN and OUT Instructions

6. Memory Mapped I/O7. Programmable I/O and 8255

I/O Devices at Memory Address Space I/O devices are located at memory address space. Use memory related instructions (like LDA, STA) to access I/O

devices. The I/O decoders monitor memory related control lines and

addresses.

An Input Device at a Memory Address To access an input port, use a memory access instruction, like LDA The input decoder monitors memory related control lines and addresses.

An example: An input device is located at a memory address F000h. Use partial address decoding, use just 4 address lines from the address

bus: A15, A14, A13, and A12.

An 8-input NAND gate is used as an input decoder. The input device is located at F000h. When IN F000h is executed by CPU, at the last machine cycle, F000h is placed onto the address bus, IO/M becomes 0. Finally RD is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the 3-state buffer of the input device is activated, and data at this device is read to ACC by CPU.

A12

A13

A14

+ 5 V

F000h AdresindekiGiriş Port'unu

Seçme Darbesi

A15

IO / M

RD

MEMR

An Output Device at a Memory Address To write to an output port, use a memory access instruction, like STA. The output decoder monitors memory related control lines and

addresses.

An example: An output device is located at a memory address F001h. Use partial address decoding, use just 5 address lines from the address

bus: A15, A14, A13, A12, and A0.

An 8-input NAND gate is used as an output decoder. The output device is located at F001h. When OUT F001h is executed by CPU, at the last machine cycle, F001h is placed onto the address bus, IO/M becomes 0. Finally WR is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the input device is activated, and 8-bit data at ACC is written to the output device by CPU.

A0

A12

A13

+ 5 V

A14

A15

F001h AdresindekiÇıkış Port'unu

Seçme Darbesi

WR

IO / MMEMW

Memory and I/O Address Spaces

Why Memory Mapped I/O ?Some processors may not have such separate IN and OUT

instructions for I/O in their instruction set.Using IN and OUT, you can only read from or write to an I/O

device. If you want to do some other operations, like OR, AND, ADD, …) directly on I/O devices, the memory mapped I/O technique can be used.

If the number of I/O devices is larger than 512 (for 8085) use the memory mapped I/O.

1. Basic Microprocessor System Concepts2. Microprocessor Architecture and Operation3. Intel 8085 Microprocessor4. 8085 Microprocessor Based System5. Isolated I/O Using IN and OUT Instructions6. Memory Mapped I/O

7. Programmable I/O and 8255

Programmable I/O In our previous simple example, we had very simple I/O devices. In general microprocessor based systems, like PCs, have programmable

I/O devices. These devices have programmable I/O ports. In addition to simple

reading and writing data, they have also some build-in additional features, like timers/counters, interrupts, bit-addressable ports, …

Some examples: Basic and handshake parallel I/O (8255, 8256) Timer/counter (8253/8254) Interrupt controller (8259) Serial/parallel data communication (8250, 8251, 8256) 1-bit data I/O (bit addressable) (8256) Keyboard/display interface (8279) Block data transfer between memory and external world (DMA) (8257)

8255 IC (a) and Logic Diagram (b)

8255A

PA440

PA6PA7WRRESET

D1D2D3D4D5D6D7VCCPB7PB6PB5PB4PB3

39383736353433323130292827262524232221

PA5 PA3 1

PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2

2 3 4 5 6 7 8 91011121314151617181920

PA2 Veri Yolu

8255A

D0

PA1PA

PC

PB

D0 - D7

A0A1

CS

WRRD

RESET

(a) (b)

D7-D0 Data Bus (bidirectional)

PA7-PA0 Port A

PB7-PB0 Port B

PC7-PC0 Port C

CS Chip Select

A0, A1 Port Address

RD Read Control

WR Write Control

RESET Reset Input

VCC +5 Volt

GND 0 Volt

8255A Chip and Port Select Signals

CS A1 A1 Selected Port

0 0 0 Port A

0 0 1 Port B

0 1 0 Port C

0 1 1 Control Register

1 X X 8255A not selected

4 addresses are occupied in I/O space

Programmable pripheral device

8255A at C0h and its Select Logic

+ 5 V

A6

A7

A4

A5

IORIOW

A3

A2

A1

A0

CS

A1

A0

RD

WR

D7 - D0D7 - D0 PA = C0h

PB = C1h

PC = C2h

PA

PB

PC

CS = 0 Address Selected Port

A7 A6 A5 A4 A3 A21 1 0 0 0 0

A1 A00 00 11 01 1

= C0h= C1h= C2h= C3h

PAPBPCControl Register

8255 Control Word

0 / 1

BSR Modu(Bit Set/Reset) I / O Modu

Mod 1Mod 0 Mod 2

A, B ve Cport'ları içinbasitgiriş/çıkış

A ve (veya) Bport'ları içinel sıkışmalı(handshake)çalışma

C port'u elsıkışma sinyalleriiçin kullanılır

A port'u için iki yönlüveri yolu

Port B: Mod 0 veya1 de çalışır

C port'ununbit'leri el sıkışmasinyalleri olarakkullanılır

Kontrol Kelimesi

D7 D6 D5 D4 D3 D2 D2 D0

C Port'u üzerindetek bit 0'lama ve1'leme yapılır

A ve B port'larıetkilenmez

D7 D6 D5 D4 D3 D2 D1 D0

Grup B

Port C (Düşük PC3 - PC0)1 = Giriş0 = Çıkış

Port B1 = Giriş0 = Çıkış

Mod Seçimi1 = Mod 00 = Mod 1

Grup A

Port C (Yüksek PC7 - PC4)1 = Giriş0 = Çıkış

Port A1 = Giriş0 = Çıkış

Mod Seçimi00 = Mode 001 = Mod 11X = Mod 2

1 = I/O Modu0 = BSR modu

Kontrol Kelimesi

8255 for the 8085 Based System Instead of using a 3-state buffer and a latch for I/O devices,

this time use an 8255 for the 8085 based system example. 8255 base address is F0h, that is the address of PA.PA will be used to read switches.PB (at F1h) will be used to drive the LED display.PC (at F2h) will not be used.Control register is at F3h.Control word = 1 0 0 1 0 0 0 0 = 90h.

I/O Operations Using 8255

8255A

Veri Yolu

D0 - D7D0 - D7

A0

A1

CS

WR

RD

A4A5A6

+ 5 V

RD

IO / MA7

WR

A0

A1

PA

+ 5 V

S7

1111000

1

S0

PB

D7

D0

+ 5 V

RESET PC

A simple I/O example using a 8255 located at F0h.

MVI A, 90h ; (ACC) 90h, Load ACC with 90h (A: input, B: output)OUT F3h ; (F3) (ACC), write the contents of ACC (90h) to control register, 8255 is programmed.

IN F0h; ; read switches (ACC) (F0h)OUT F1h ; drive LEDs (F1) (ACC)

References Mikroişlemciler ve Bilgisayarlar, 3. Basım, H. Gümüşkaya, ALFA,

2002. (Chapter 3).