Module 3Instruction Set Architecture (ISA):

ISA LevelElements of Instructions

Instructions TypesNumber of Addresses

RegistersTypes of Operands

Instruction Set Architecture (ISA) Level

ISA Level defines the interface between the compliers (high level language) and the hardware. It is the language that both them understand

What is an Instruction Set? The complete collection of instructions

that are understood by a CPU Known also as Machine Code/Machine

Instruction Binary representation Usually represented by assembly codes User becomes aware of registers,

memory structure, data types supported by machine and the functioning of ALU

Elements of an Instruction-1 Operation code (Opcode)

Specifies the operation to be performed (ADD, SUB etc). Specified as binary code know as OPCODE

Source Operand reference One or more source operands (input for the operation)

Result (Destination) Operand reference Operation produce a result (output for the operation)

Next Instruction Reference Tells processor where to fetch the next instruction

after the execution of current instruction is completed

Elements of an Instruction-2 Source and result operands could be:

Main memory or virtual memory – addresses is supplied for instruction references

CPU registers (processor registers) – One or more registers that can be referenced by instructions

I/O device – instruction specifies the I/O module and device for the operation

Instruction Representation In machine code each instruction has a unique bit pattern Instruction divided into fields and with multiple formats – refer

diagram in the next slide During execution, instruction is read into IR register in the

processor For human consumption (well, programmers anyway) a

symbolic representation is used Opcodes represented as mnemonics indicates the operations

e.g. ADD, SUB, LOAD Difficult to deal in binary representation of machine

instructions Operands can also be represented symbolically

ADD A,B

Simple Instruction Format

Instruction Types Data processing – Arithmetic and

logic instructions Data storage (ma

in memory) – memory instructions Data movement (I/O) – I/O

instructions Control (Program flow control) – Test

and branch instructions

Number of Addresses Number of addresses per instructions can describe processor architecture 3 addresses

Operand 1, Operand 2, Result (Destination) May be a forth address - next instruction (usually implicit, obtained from

PC) Example below: T=temporary location used to store intermediate results Not common in use Needs very long words to hold everything

Number of Addresses 2 addresses

One address doubles as operand and result(destination) Reduces length of instruction and space requirements Requires some extra work

Temporary storage to hold some results Done to avoid altering the operand value

Number of Addresses 1 address

Implicit second address Usually a register (accumulator) Common on early machines

Number of Addresses 0 (zero) addresses

All addresses implicit Uses a stack

How Many Addresses Number of addresses per instruction is a basic design

decision More addresses

More complex (powerful?) instructions More registers

Inter-register operations are quicker Fewer instructions per program

Fewer addresses Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions

Instruction Set Design Decisions (1)

Operation repertoire How many ops? What can they do? How complex are they?

Data types Instruction formats

Length of op code field Number of addresses

Instruction Set Design Decisions (2)

Registers Number of CPU registers available Which operations can be performed

on which registers? Addressing modes (later…) RISC v CISC

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Pentium Registers & Addressing Modes 16

Registers (32-bit)

base pointer Register

esi

edi

esp

ebp

stack pointer Register

eax

ebx

ecx

edx

31 0

‘A’ register

‘B’ register

‘C’ register

‘D’ register

source index register destination index register

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Pentium Registers & Addressing Modes 17

...Registers (16-bit)

esi

edi

esp

ebp

si

di

sp

bp

ax

bx

cx

dx

eax

ebx

ecx

edx

31 1615 0 The least significant 16-

bits of these registers have an additional register name that can be used for accessing just those 16-bits.

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Pentium Registers & Addressing Modes 18

…Registers (8-bit)

ax

bx

cx

dx

eax

ebx

ecx

edx

31 1615 0

bh bl

ch cl

dh dl

ah al15 8 7 0

The 2 least significant bytes of registers eax, ebx, ecx and edx also have register names, that can be used for accessing 8 bits.

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Pentium Registers & Addressing Modes 19

Instruction Pointer Register

eip32-bit

The instruction pointer register eip holds the address of the next instruction to be executed. The eip register corresponds to the program counter register in other architectures.

eip is not normally manipulated explicitly by programs. However it is updated by special control-flow CPU instructions (e.g. call, jmp, ret) that are used to implement if's, while's, method calls etc.

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Pentium Registers & Addressing Modes 20

Flags Register

eflags32-bit

The eflags register holds information about the current state of the CPU. Its 32-bits are mostly of interest to the Operating System; however, some of its bits are set/cleared after arithmetic instructions are executed, and these bits are used by conditional branch instructions:

Types of Operand Numbers – numeric data

Integer/floating point/decimal Limited magnitude of numbers – integer/decimal Limit precision – floating point

Characters – data for text and strings ASCII, UNICODE etc.

Logical Data Bits or flags

Example: Types of Operand for Pentium 4

Module 3Instruction Set Architecture (ISA):

Addressing Modes Instruction Formats

Addressing Modes Addressing – reference a location

in main memory/virtual memory Immediate Direct Indirect Register Register Indirect Displacement (Indexed)

AddressingModes

A=contents of an address field in instruction

R=contents of an address field in instruction that refers to a register

EA=actual (effective) address of the location containing the referenced operand

(X)=contents of memory location X or register X

Addressing Modes

Immediate Addressing Operand is part of instruction Operand = A e.g. ADD EAX,5

Add 5 to contents of register EAX 5 is operand

No memory reference to fetch data Fast Limited range

OperandOpcode

Instruction

Direct Addressing Address field contains address of operand EA = A e.g. ADD EAX, A

Add contents of cell A to register EAX Look in memory at address A for operand

Single memory reference to access data No additional calculations to work out

effective address Limited address space

Direct Addressing Diagram

Address AOpcode

Instruction

Memory

Operand

Indirect Addressing (1) Memory cell pointed to by address

field contains the address of (pointer to) the operand

EA = (A) or EA = [A] Look in A, find address (A) and look

there for operand e.g. ADD EAX,(A) or ADD EAX,[A]

Add contents of cell pointed to by contents of A to register EAX

Indirect Addressing (2) Large address space 2n where n = word length May be nested, multilevel, cascaded

e.g. EA = (((A))) or EA = [[[A]]] Draw the diagram yourself

Multiple memory accesses to find operand

Hence slower

Indirect Addressing Diagram

Address AOpcode

Instruction

Memory

Operand

Pointer to operand

Register Addressing (1) Operand is held in register named

in address filed EA = R Limited number of registers Very small address field needed

Shorter instructions Faster instruction fetch

Register Addressing (2) No memory access Very fast execution Very limited address space Multiple registers helps

performance Requires good assembly programming

or compiler writing c.f. Direct addressing

Register Addressing Diagram

Register Address ROpcode

Instruction

Registers

Operand

Register Indirect Addressing C.f. indirect addressing EA = (R) or EA = [R] Operand is in memory cell pointed

to by contents of register R Large address space (2n) One fewer memory access than

indirect addressing

Register Indirect Addressing Diagram

Register Address ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

Displacement Addressing Combines direct addressing and register

indirect addressing EA = A + (R) or EA = A + [R] Address field hold two values

A = base value R = register that holds displacement or vice versa

3 common displacement addressing technique: Relative addressing Base register addressing Indexing

Displacement Addressing Diagram

Register ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

Address A

+

Relative Addressing A version of displacement

addressing R = Program counter, PC EA = A + (PC) or EA = A + [PC] i.e. get operand from A cells from

current location pointed to by PC c.f locality of reference & cache

usage

Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86

Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays

Pentium Addressing Modes Virtual or effective address is offset into segment

Starting address plus offset gives linear address This goes through page translation if paging enabled

12 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative

Pentium Addressing Mode Calculation

Instruction Formats Layout of bits in an instruction Includes opcode Includes (implicit or explicit)

operand(s) Usually more than one instruction

format in an instruction set

Instruction Formats

Four common instruction formats: (a) Zero-address instruction. (b) One-address instruction (c) Two-address instruction. (d) Three-address instruction.

Instruction Length Affected by and affects:

Memory size Memory organization Bus structure CPU complexity CPU speed

Trade off between powerful instruction repertoire and saving space

Other issues: Instruction length equal or multiple to memory transfer length (bus system)?

Allocation of Bits Number of addressing modes – if indicated

implicitly exp: certain op-odes might always call for indexing; if explicit – one or more bits will be needed

Number of operands – typical instruction has 2 operands – uses mode indicator for operand addresses

Register versus memory – single user register (accumulator), one operand address is implicit and consume no instruction bits; for multiple registers – a few bits are need to specify the registers

Allocation of Bits Number of register sets – have one set of

general purpose registers with 32 or more registers in the set – for example sets of 8 registers only 3 bits are needed to identify the registers, op-code will implicitly determine which register set is being referenced

Address range – the range of addresses that can be referenced related to the number of bits

Address granularity – an address can reference a word or byte a the designer’s choice – byte addressing is convenient for character manipulation

PDP-8 Instruction Format

Fixed Length Instruction: PDP-8 Instruction Format-1

Fixed Length Instruction: PDP-8 Instruction Format -2

Simplest instruction design Has 12 instruction and operates on 12 bit words 3 bit op-code and 3 types of instructions Op-code 0-5 – single address memory reference

including page bit and indirect bit – thus 6 basic operations

Op-code 7 defines microinstructions – remaining bits are used to encode additional operations – each bit defines a specific operations (etc clear accumulator – bit 4)

Op-code 6 is for I/O operations; 6 bits used to select one of 64 devices and 3 bits to specify I/O command

Also supports indirect addressing, displacement addressing and indexing