Modern Semiconductor Devices for Integrated …bkict-ocw.knu.ac.kr/include/download.html?fn=559E1D8711734.pdfModern Semiconductor Devices for Integrated Circuits Chapter 4. PN and

Chapter 4. PN and Metal-Semiconductor JunctionsModern Semiconductor Devices for Integrated Circuits

Energy band diagram of a

Schottky contact with a

forward bias V applied

between the metal and the

semiconductor.

Thermionic Emission Theory

Electron concentration at the interface is

(assuming EFn is flat all the way to the peak of the

barrier) 3/ 2

( ) / ( ) /

2

22B Bq V kT q V kTn

C

m kTn N e e

h

It can be shown that the average velocity of

the left traveling electron is

2 /thx nv kT m

2/ /2 / 2 / /

03

41

2B Bq kT q kTqV kT qV kT qV kTn

S M thx

m kJ qnv T e e KT e e J e

h

Only half of the electrons travel

toward the left.

/

0

( ) /

B

B

q kT

q V kT

S M

J e

J e

Determines how many electrons possess

sufficient energy to surpass the peak of the

energy barrier and enter the metal.

22 2

3

4100 /( / K )nqm k

K A cmh

called Richardson constant


Schottky DiodesAt zero bias (V = 0),

the net current is zero.

0(0)S MI I

0(0)M SI I

0 (0) (0)S M M SI I I

/2

0 0 ,Bq kTwhere I AJ AKT e A diode area

At forward bias,

0( ) (0)M S M SI V I I

because the barrier height remains

unchanged at the value at equilibrium.B

/2 / /

0( ) Bq kT qV kT qV kT

S MI V AkT e e I e

because the barrier height is now

smaller by qV.

/ /

0 0 0( ) ( ) ( ) ( 1)qV kT qV kT

S M M SI V I V I V I e I I e


Schematic IV characteristics of PN and

Schottky diodes having the same area.

Applications of Schottky Diodes/

0 ( 1)qV kTI I e

Block diagram of a switching power supply for

electronic equipment such as PCs.

Schottky diode is preferred in low voltage and

high current rectifier applications.

~ 40 W ( 50 A × 0.8 V),

if PN junction rectifier is used.

Power consumption =~ 15 W ( 50 A × 0.3 V)

Schottky Diodes:

• Majority carrier only: high speed/frequency

(negligible minority carrier injection )• Larger I0→ smaller forward bias→ low power

consumption

Clamp diode


Ohmic Contacts

Semiconductor devices are connected to each

other in an integrated circuit through metal. The

semiconductor to metal contacts should have

sufficiently low resistance.

Ideal ohmic contact: The voltage across an ideal ohmic contact is zero.

For good ohmic contact, the semiconductor must be

very heavily doped to have only few nm-thin depletion

layer.

Tunneling

2

2

8exp 2 ( )H

mP T V E

h

Tunneling probability,

H BnV E

/ 2depT W

The Fermi level cannot deviate from its

equilibrium position and therefore

at ideal ohmic contact.

0n p

Or, equivalently, surface recombination velocity

becomes infinity, .S


/ 22

s Bndep

d

T WqN

2 2

2 2

/

8 8exp 2 ( ) exp 2

2

Bn d

s BnH Bn

d

H N

m mP T V E

h qN h

e

,H BnV E

4, ( ) /s nwhere H m q

h

At V = 0, 1

02

S M M S d thxJ J J qN v P

S MJ

If a small voltage is applied across the contact, the

barrier for is reduced from to Bn ( )Bn V

( ) /1

2

Bn dH V N

S M d thxJ qN v e

Specific contact resistance [Ω cm2],

/

0

1

2

Bn dH NS MV thx d

dJJ V V qv H N e

dV

//2 Bn d

Bn d

H NH N

C

thx d

V eR e

J qv H N

At small V, the net current density is,

(The resistance of a 1 cm2 contact)

The IV characteristics of a 0.3 µm (diameter) TiSi2contact on N+-Si and P+-Si.

(From [11]. © 1999 IEEE.)

Theoretical specific contact resistance.

(After [12].)

Chapter 5. MOS CapacitorModern Semiconductor Devices for Integrated Circuits

MOS Capacitor

Chapter 5

OBJECTIVES

1. Understand the modern MOS structures.

2. Understand the concepts of surface depletion,

threshold, and inversion.

3. Understand the MOS capacitor C-V

4. Build the foundation for understanding the

MOSFETs.


MOS (metal-oxide-semiconductor) Capacitor

The MOS capacitor

An MOS transistor is an MOS capacitor with PN junctions at two ends.

Al (before 1970),

Heavily doped polycrystalline silicon (after 1970)

Various metals (after 2008)

Thickness: as thin as ~ 1.5 nm

Silicon dioxide (almost perfect insulator)

Advanced dielectrics (after 2008)

The MOS capacitor: the simplest of

MOS devices and the structural

heart of all MOS devices includingMOSFETs.


Flat-Band Condition and Flat-Band Voltage

For Vg = 0

Band is not flat.

Applying a negative

voltage equal to flat-

band voltage (Vfb) to the

gate.

E ox

E s

2

0 :

: [ ]

: [ ]

: [ ]

: [ ]

g

s

Si

SiO

E vacuum level

work function of gate material V

work function of semiconductor V

electron affinnity of silicon eV

electron affinnity of oxide eV

In SiO2, the exact position of EF has no significance. 60 3exp[( ) / 10C C Fn N E E kT cm

,assuming EF is around in the middle of the SiO2 band gap.

fb g sV

Flat-Band Voltage

Flat-Band Condition (for Vg = Vfb)

Flat-band

0E ox

0E s

g gateq

0s

0s


Surface Accumulation

For Vg < Vfb: [ ]

: [ ]

:

s

s

ox

surface potential V

q band bending eV

V oxide voltage

, .

, .

C

s

C

negative if E bendsupward

positive if E bendsdownward

hole accumulation

(ps > p0 = Na)

Potential reference

oxqV

/

100 200

,

s

sq kT

s a a

f mV

p N e N p

i

At flat-band, , 0g fb s oxV V V

g Fm Fs fb s oxV E E V V

2[ / ]accQ C cm

( )x

E ox

E s

Accumulation

layer

0s


In the case of surface accumulation, is small in a first-order model.s

ox g fbV V V

Using Gauss’s Law at the surface, ( )D x

1 2 3 4 1,side side sideD AD A D A D AD AD where A A

oxide

semiconductor

surface

accQ

1D

3D 4D

2 0D

x1 ( )D AD x

1 E Es s ox oxD

( )E Es s ox ox acc

xQ

A

E accox

ox

Q

E acc

ox ox ox

ox

QV T

C

(deep into semiconductor)

( )acc ox g fbQ C V V

In general, sub

ox

ox

QV

C

All the charge that may be present in

the substrate, including Qacc.

2, [ / ]oxox

ox

where C F cmT

The MOS capacitor in accumulation behaves

like a capacitor but with a shift in V by Vfb.


The MOS capacitor is biased into

surface depletion.

(a) Types of charge present;

(b) energy band diagram.

Surface Depletion

For Vg > Vfb

2

depsubox

ox ox

a dep a s s

ox ox

QQV

C C

qN W qN

C C

2

2

a dep

s

s

qN W

( )x

E ox

E s

Depletion layer

charge aN

2

2

a dep a dep

g fb s ox fb

s ox

qN W qN WV V V V

C

/sq kT

s a ap N e N p

0s

2 s sdep

a

WqN


Threshold Condition and Threshold VoltageFor more positive (Vg = Vt > Vfb)

2 0s st B

Threshold condition

s an N

( )x

E ox

E s

Depletion layer

charge aN

Surface electron

sn

( ) ( )C F surface F V bulkE E E E

( ) ( )i F bulk F i surfaceE E E E

( )B i F bulkq E E

Fermi potential energy

sub dep inv depQ Q Q Q

( )E x ( )V x

( ) ( )E

s

d x x

dx

( )( )E

dV xx

dx

(0) (0)E Es s ox ox

0x x


Theoretical threshold voltage vs. body doping concentration. ( )

ln

B i F bulk

a

i

q E E

NkT

n

Fermi potential energy

2

exp[ ( ) / ]

exp[ ( ) / ]

exp[ / ]

i C C i

V F V

i C V g

n N E E kT

p N E E kT

n N N E kT

At threshold,

22 ln a

s st B

i

NkT

q n

Threshold Voltage, Vt

(Vg at the threshold condition)

2

2

2

2 22

s Bt g fb s ox

a dep a dep

fb

s ox

a s B

t fb B

ox

V V V V

qN W qN WV

C

qNV V

C

For N-Type Body

2

2 , ln

d s st

t fb st

ox

dst B B

i

qNV V

C

NkT

q n

For P-Type Body


An MOS capacitor is biased into

inversion.

Strong Inversion beyond Threshold

( )x

E ox

E s

Depletion layer

charge aN

Inversion layer

(thickness: ~5 nm)2[ / ]invQ C cm s an N

Inversion layer charge density

Surface becomes N-type.

WithVg > Vt , does not increase much

further beyond since even small

increase in would induce a much

larger surface electron density and

therefore a larger Vox that would soak

up the Vg .

s2 B

s

2

exp( )

2

.B

s

s

s B

Surface potential is essentially pinned at

qn

kT

For Vg > Vt

sub dep invQ Q Q


2 ,s BIf max

2 2s Bdep d

a

W WqN

2

2 22 2

subg fb s ox fb B

ox

dep a s Binv invfb B fb B

ox ox ox ox

invt

ox

QV V V V

C

Q qNQ QV V

C C C C

QV

C

sub dep invQ Q Q

subox

ox

QV

C

( )inv ox g tQ C V V The MOS capacitor in strong

inversion behaves like a

capacitor except for a voltage

offset of Vt.There are few electrons in the P-type body, and it

can take minutes for thermal generation to

generate the necessary electrons to form the

inversion layer.

How to solve this problem?

(a) The surface inversion behavior is best studied with a PN junction

butting the MOS capacitor to supply the inversion charge. (b) The

inversion layer may be thought of as a thin N-type layer.


Review: Basic MOS Capacitor Theory

Surface potential saturates at 2ϕB

in inversion when Vg is larger than

Vt and saturates at Vfb in

accumulation.

Depletion-region width in the

body of an MOS capacitor.


Components of charge (C/cm2) in the MOS

capacitor substrate: (a) depletion-layer charge;

(b) inversion-layer charge; and (c) accumulation-

layer charge.

The total substrate charge, Qsub (C/cm2),

is the sum of Qacc, Qdep, and Qinv.


Qsub Vs. Surface Potential

2( / )subQ C cm2 B

B

( )s V

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Modern Semiconductor Devices for Integrated …bkict-ocw.knu.ac.kr/include/download.html?fn=559E1D8711734.pdfModern Semiconductor Devices for Integrated Circuits Chapter 4. PN and