Mobile 5th Generation Intel Core Processor Family · Mobile 5th Generation Intel® Core™ Processor Family Datasheet – Volume 2 of 2 Supporting 5th Generation Intel® Core™ Processor

Mobile 5th Generation Intel CoreProcessor FamilyDatasheet Volume 2 of 2 Supporting 5th Generation Intel Core Processor based on MobileH-Processor Line

June 2015

Order No.: 332379-001

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Mobile 5th Generation Intel Core Processor FamilyDatasheet Volume 2 of 2 June 20152 Order No.: 332379-001

http://www.intel.com/design/literature.htmhttp://www.intel.com/design/literature.htmhttp://www.intel.com/http://www.intel.com/info/hyperthreadinghttp://www.intel.com/design/chipsets/hdaudio.htmhttp://www.intel.com/design/chipsets/hdaudio.htmhttp://www.intel.com/content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.htmlhttp://www.intel.com/content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.htmlhttp://www.intel.com/go/virtualizationhttp://ark.intel.com/http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-instructions-aes-ni/http://www.intel.com/content/www/us/en/architecture-and-technology/intel-active-management-technology.htmlhttp://www.intel.com/technology/securityhttp://www.intel.com/technology/securityhttps://www-ssl.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.htmlhttps://www-ssl.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.htmlhttps://www-ssl.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.html

Contents

Revision History................................................................................................................15

1.0 Introduction................................................................................................................16

2.0 Processor Configuration Register Definitions and Address Ranges............................. 172.1 Register Terminology............................................................................................ 172.2 PCI Devices and Functions..................................................................................... 182.3 System Address Map.............................................................................................202.4 Legacy Address Range...........................................................................................232.5 Main Memory Address Range (1 MB TOLUD).......................................................... 262.6 Main Memory Address Space (4 GB to TOUUD)......................................................... 292.7 PCI Memory Address Range (TOLUD 4 GB)............................................................ 322.8 PCI Express* Configuration Address Space .............................................................. 342.9 PCI Express* Graphics Attach (PEG) .......................................................................352.10 Graphics Memory Address Ranges......................................................................... 352.11 System Management Mode (SMM)........................................................................362.12 SMM and VGA Access Through GTT TLB.................................................................372.13 Intel Management Engine (Intel ME) Stolen Memory Accesses..............................372.14 I/O Address Space............................................................................................. 382.15 Direct Media Interface (DMI) Interface Decode Rules.............................................. 392.16 PCI Express* Interface Decode Rules....................................................................422.17 Legacy VGA and I/O Range Decode Rules..............................................................432.18 I/O Mapped Registers......................................................................................... 46

3.0 Host Device Configuration Registers........................................................................... 473.1 Host Bridge/DRAM Registers Summary.................................................................... 47

3.1.1 VIDVendor Identification......................................................................... 483.1.2 DIDDevice Identification..........................................................................483.1.3 PCICMDPCI Command............................................................................ 493.1.4 PCISTSPCI Status.................................................................................. 503.1.5 RIDRevision Identification....................................................................... 513.1.6 CCClass Code........................................................................................ 513.1.7 HDRHeader Type....................................................................................523.1.8 SVIDSubsystem Vendor Identification....................................................... 523.1.9 SIDSubsystem Identification....................................................................523.1.10 CAPPTRCapabilities Pointer.................................................................... 523.1.11 PXPEPBARPCI Express Egress Port Base Address.......................................523.1.12 MCHBARHost Memory Mapped Register Range Base.................................. 533.1.13 GGCGMCH Graphics Control Register.......................................................543.1.14 DEVENDevice Enable.............................................................................553.1.15 PAVPCProtected Audio Video Path Control................................................ 563.1.16 DPRDMA Protected Range......................................................................573.1.17 PCIEXBARPCI Express Register Range Base Address..................................573.1.18 DMIBARRoot Complex Register Range Base Address................................. 583.1.19 MESEGIntel Management Engine Base Address Register............................ 593.1.20 MESEGIntel Management Engine Limit Address Register............................ 593.1.21 PAM0Programmable Attribute Map 0....................................................... 603.1.22 PAM1Programmable Attribute Map 1....................................................... 613.1.23 PAM2Programmable Attribute Map 2....................................................... 62

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Mobile 5th Generation Intel Core Processor FamilyJune 2015 Datasheet Volume 2 of 2Order No.: 332379-001 3

3.1.24 PAM3Programmable Attribute Map 3....................................................... 633.1.25 PAM4Programmable Attribute Map 4....................................................... 643.1.26 PAM5Programmable Attribute Map 5....................................................... 653.1.27 PAM6Programmable Attribute Map 6....................................................... 663.1.28 LACLegacy Access Control..................................................................... 673.1.29 SMRAMCSystem Management RAM Control.............................................. 693.1.30 REMAPBASERemap Base Address Register............................................... 703.1.31 REMAPLIMITRemap Limit Address Register...............................................703.1.32 TOMTop of Memory...............................................................................713.1.33 TOUUDTop of Upper Usable DRAM.......................................................... 713.1.34 BDSMBase Data of Stolen Memory..........................................................723.1.35 BGSMBase of GTT stolen Memory........................................................... 733.1.36 TSEGMBTSEG Memory Base...................................................................733.1.37 TOLUDTop of Low Usable DRAM..............................................................733.1.38 SKPDScratchpad Data........................................................................... 743.1.39 CAPID0Capabilities A............................................................................ 753.1.40 CAPID0Capabilities B............................................................................ 75

3.2 Integrated Graphics Device Registers Summary........................................................ 763.2.1 VID2Vendor Identification....................................................................... 773.2.2 DID2Device Identification........................................................................783.2.3 PCICMDPCI Command............................................................................ 783.2.4 PCISTS2PCI Status.................................................................................793.2.5 RID2Revision Identification......................................................................803.2.6 CCClass Code........................................................................................ 803.2.7 CLSCache Line Size................................................................................ 803.2.8 MLT2Master Latency Timer...................................................................... 813.2.9 HDR2Header Type..................................................................................813.2.10 GTTMMADRGraphics Translation Table, Memory Mapped Range Address...... 813.2.11 GMADRGraphics Memory Range Address................................................. 823.2.12 IOBARI/O Base Address........................................................................ 833.2.13 SVID2Subsystem Vendor Identification....................................................833.2.14 SID2Subsystem Identification................................................................ 833.2.15 ROMADRVideo BIOS ROM Base Address...................................................843.2.16 CAPPOINTCapabilities Pointer.................................................................843.2.17 INTRLINEInterrupt Line......................................................................... 843.2.18 INTRPINInterrupt Pin............................................................................ 853.2.19 MINGNTMinimum Grant.........................................................................853.2.20 MAXLATMaximum Latency..................................................................... 853.2.21 CAPID0Capabilities A............................................................................ 853.2.22 CAPID0Capabilities B............................................................................ 863.2.23 DEVEN0Device Enable...........................................................................873.2.24 MSACMulti Size Aperture Control............................................................ 883.2.25 MSIMessage Signaled Interrupts Capability ID..........................................903.2.26 MCMessage Control.............................................................................. 903.2.27 MAMessage Address..............................................................................913.2.28 MDMessage Data..................................................................................913.2.29 AFCIDNPAdvanced Features Capabilities Identifier and Next Pointer............ 913.2.30 AFCTLAdvanced Features Control............................................................923.2.31 AFSTSAdvanced Features Status............................................................ 923.2.32 PMCAPIDPower Management Capabilities ID.............................................923.2.33 PMCAPPower Management Capabilities.................................................... 93

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3.2.34 PMCSPower Management Control/Status................................................. 933.3 Audio Controller Registers Summary....................................................................... 94

3.3.1 VIDVendor Identification......................................................................... 953.3.2 DIDDevice ID........................................................................................ 953.3.3 PCICMDPCI Command............................................................................ 953.3.4 STSPCI Status....................................................................................... 963.3.5 RIDRevision Identification....................................................................... 963.3.6 PIProgramming Interface........................................................................ 973.3.7 SCCSub Class Code................................................................................ 973.3.8 BCCBase Class Code...............................................................................973.3.9 CLSCache Line Size................................................................................ 973.3.10 HDALBARIntel HD Audio Base Lower Address....................................... 973.3.11 HDAHBARIntel HD Audio Base Upper Address.......................................983.3.12 SVIDSubsystem Vendor ID.................................................................... 983.3.13 CAPPTRCapability Pointer...................................................................... 983.3.14 INTLNInterrupt Line..............................................................................983.3.15 INTPNInterrupt Pin............................................................................... 983.3.16 CAPID0Capabilities A............................................................................ 993.3.17 CAPID0Capabilities B............................................................................ 993.3.18 DEVENDevice Enable...........................................................................1003.3.19 PIDPCI Power Management Capability ID............................................... 1013.3.20 PMCSPower Management Control And Status..........................................1023.3.21 MIDMSI Capability ID..........................................................................1023.3.22 MMCMSI Message Control.................................................................... 1033.3.23 MMAMSI Message Lower Address..........................................................1033.3.24 MMDMSI Message Data....................................................................... 1033.3.25 PXIDPCI Express Capability ID..............................................................1033.3.26 PXCPCI Express Capabilities................................................................. 1043.3.27 DEVCAPDevice Capabilities...................................................................1043.3.28 DEVCDevice Control............................................................................1053.3.29 DEVSDevice Status............................................................................. 105

4.0 PCI Express* (PCIe*) Registers ...............................................................................1074.1 PCI Express Controller (x16) Registers Summary.................................................... 107

4.1.1 VIDVendor Identification....................................................................... 1084.1.2 DIDDevice Identification........................................................................1094.1.3 PCICMDPCI Command...........................................................................1094.1.4 PCISTSPCI Status.................................................................................1104.1.5 RIDRevision Identification......................................................................1124.1.6 CCClass Code.......................................................................................1134.1.7 CLCache Line Size................................................................................ 1134.1.8 HDRHeader Type..................................................................................1134.1.9 PBUSNPrimary Bus Number................................................................... 1144.1.10 SBUSNSecondary Bus Number..............................................................1144.1.11 SUBUSNSubordinate Bus Number......................................................... 1144.1.12 IOBASEI/O Base Address.....................................................................1144.1.13 IOLIMITI/O Limit Address.................................................................... 1154.1.14 SSTSSecondary Status........................................................................ 1154.1.15 MBASEMemory Base Address............................................................... 1164.1.16 MLIMITMemory Limit Address...............................................................1174.1.17 PMBASEPrefetchable Memory Base Address............................................117

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4.1.18 PMLIMITPrefetchable Memory Limit Address........................................... 1184.1.19 PMBASEUPrefetchable Memory Base Address Upper................................ 1184.1.20 PMLIMITUPrefetchable Memory Limit Address Upper................................1194.1.21 CAPPTRCapabilities Pointer...................................................................1194.1.22 INTRLINEInterrupt Line....................................................................... 1204.1.23 INTRPINInterrupt Pin.......................................................................... 1204.1.24 BCTRLBridge Control...........................................................................1214.1.25 PMPower Management Capabilities........................................................1224.1.26 PMPower Management Control/Status................................................... 1234.1.27 SSSubsystem ID and Vendor ID Capabilities...........................................1244.1.28 SSSubsystem ID and Subsystem Vendor ID........................................... 1254.1.29 MSIMessage Signaled Interrupts Capability ID........................................ 1254.1.30 MCMessage Control.............................................................................1254.1.31 MAMessage Address............................................................................1264.1.32 MDMessage Data................................................................................ 1264.1.33 PEGPCI Express Capability List............................................................. 1274.1.34 PEGPCI Express Capabilities................................................................. 1274.1.35 DCAPDevice Capabilities...................................................................... 1274.1.36 DCTLDevice Control............................................................................ 1284.1.37 DSTSDevice Status............................................................................. 1294.1.38 LCTLLink Control................................................................................ 1304.1.39 LSTSLink Status................................................................................. 1324.1.40 SLOTCAPSlot Capabilities.....................................................................1334.1.41 SLOTCTLSlot Control........................................................................... 1354.1.42 SLOTSTSSlot Status............................................................................1374.1.43 RCTLRoot Control............................................................................... 1384.1.44 RSTSRoot Status................................................................................ 1404.1.45 DCAP2Device Capabilites 2.................................................................. 1404.1.46 DCTL2Device Control 2........................................................................1424.1.47 LCTL2Link Control 2............................................................................ 1434.1.48 LSTS2Link Status 2.............................................................................1464.1.49 PVCCAP1Port VC Capability Register 1................................................... 1474.1.50 PVCCAP2Port VC Capability Register 2................................................... 1474.1.51 PVCCTLPort VC Control........................................................................1474.1.52 VC0RCAPVC0 Resource Capability......................................................... 1484.1.53 VC0RCTLVC0 Resource Control............................................................. 1484.1.54 VC0RSTSVC0 Resource Status..............................................................149

4.2 PCI Express Controller (x8) Registers Summary...................................................... 1504.2.1 VIDVendor Identification....................................................................... 1514.2.2 DIDDevice Identification........................................................................1524.2.3 PCICMDPCI Command...........................................................................1524.2.4 PCISTSPCI Status.................................................................................1534.2.5 RIDRevision Identification......................................................................1554.2.6 CCClass Code.......................................................................................1564.2.7 CLCache Line Size................................................................................ 1564.2.8 HDRHeader Type..................................................................................1564.2.9 PBUSNPrimary Bus Number................................................................... 1574.2.10 SBUSNSecondary Bus Number..............................................................1574.2.11 SUBUSNSubordinate Bus Number......................................................... 1574.2.12 IOBASEI/O Base Address.....................................................................1574.2.13 IOLIMITI/O Limit Address.................................................................... 158

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4.2.14 SSTSSecondary Status........................................................................ 1584.2.15 MBASEMemory Base Address............................................................... 1594.2.16 MLIMITMemory Limit Address...............................................................1604.2.17 PMBASEPrefetchable Memory Base Address............................................1604.2.18 PMLIMITPrefetchable Memory Limit Address........................................... 1614.2.19 PMBASEUPrefetchable Memory Base Address Upper................................ 1614.2.20 PMLIMITUPrefetchable Memory Limit Address Upper................................1624.2.21 CAPPTRCapabilities Pointer...................................................................1624.2.22 INTRLINEInterrupt Line....................................................................... 1634.2.23 INTRPINInterrupt Pin.......................................................................... 1634.2.24 BCTRLBridge Control...........................................................................1644.2.25 PMPower Management Capabilities........................................................1654.2.26 PMPower Management Control/Status................................................... 1664.2.27 SSSubsystem ID and Vendor ID Capabilities...........................................1674.2.28 SSSubsystem ID and Subsystem Vendor ID........................................... 1684.2.29 MSIMessage Signaled Interrupts Capability ID........................................ 1684.2.30 MCMessage Control.............................................................................1684.2.31 MAMessage Address............................................................................1694.2.32 MDMessage Data................................................................................ 1694.2.33 PEGPCI Express Capability List............................................................. 1704.2.34 PEGPCI Express Capabilities................................................................. 1704.2.35 DCAPDevice Capabilities...................................................................... 1704.2.36 DCTLDevice Control............................................................................ 1714.2.37 DSTSDevice Status............................................................................. 1724.2.38 LCTLLink Control................................................................................ 1734.2.39 LSTSLink Status................................................................................. 1754.2.40 SLOTCAPSlot Capabilities.....................................................................1764.2.41 SLOTCTLSlot Control........................................................................... 1784.2.42 SLOTSTSSlot Status............................................................................1804.2.43 RCTLRoot Control............................................................................... 1814.2.44 RSTSRoot Status................................................................................ 1834.2.45 DCAP2Device Capabilites 2.................................................................. 1834.2.46 DCTL2Device Control 2........................................................................1854.2.47 LCTL2Link Control 2............................................................................ 1864.2.48 LSTS2Link Status 2.............................................................................1894.2.49 PVCCAP1Port VC Capability Register 1................................................... 1904.2.50 PVCCAP2Port VC Capability Register 2................................................... 1904.2.51 PVCCTLPort VC Control........................................................................1904.2.52 VC0RCAPVC0 Resource Capability......................................................... 1914.2.53 VC0RCTLVC0 Resource Control............................................................. 1914.2.54 VC0RSTSVC0 Resource Status..............................................................192

4.3 PCI Express Controller (x4) Registers Summary...................................................... 1934.3.1 VIDVendor Identification....................................................................... 1944.3.2 DIDDevice Identification........................................................................1954.3.3 PCICMDPCI Command...........................................................................1954.3.4 PCISTSPCI Status.................................................................................1964.3.5 RIDRevision Identification......................................................................1984.3.6 CCClass Code.......................................................................................1994.3.7 CLCache Line Size................................................................................ 1994.3.8 HDRHeader Type..................................................................................1994.3.9 PBUSNPrimary Bus Number................................................................... 200

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4.3.10 SBUSNSecondary Bus Number..............................................................2004.3.11 SUBUSNSubordinate Bus Number......................................................... 2004.3.12 IOBASEI/O Base Address.....................................................................2004.3.13 IOLIMITI/O Limit Address.................................................................... 2014.3.14 SSTSSecondary Status........................................................................ 2014.3.15 MBASEMemory Base Address............................................................... 2024.3.16 MLIMITMemory Limit Address...............................................................2034.3.17 PMBASEPrefetchable Memory Base Address............................................2034.3.18 PMLIMITPrefetchable Memory Limit Address........................................... 2044.3.19 PMBASEUPrefetchable Memory Base Address Upper................................ 2044.3.20 PMLIMITUPrefetchable Memory Limit Address Upper................................2054.3.21 CAPPTRCapabilities Pointer...................................................................2054.3.22 INTRLINEInterrupt Line....................................................................... 2064.3.23 INTRPINInterrupt Pin.......................................................................... 2064.3.24 BCTRLBridge Control...........................................................................2074.3.25 PMPower Management Capabilities........................................................2084.3.26 PMPower Management Control/Status................................................... 2094.3.27 SSSubsystem ID and Vendor ID Capabilities...........................................2104.3.28 SSSubsystem ID and Subsystem Vendor ID........................................... 2114.3.29 MSIMessage Signaled Interrupts Capability ID........................................ 2114.3.30 MCMessage Control.............................................................................2114.3.31 MAMessage Address............................................................................2124.3.32 MDMessage Data................................................................................ 2124.3.33 PEGPCI Express Capability List............................................................. 2134.3.34 PEGPCI Express Capabilities................................................................. 2134.3.35 DCAPDevice Capabilities...................................................................... 2134.3.36 DCTLDevice Control............................................................................ 2144.3.37 DSTSDevice Status............................................................................. 2154.3.38 LCTLLink Control................................................................................ 2164.3.39 LSTSLink Status................................................................................. 2184.3.40 SLOTCAPSlot Capabilities.....................................................................2194.3.41 SLOTCTLSlot Control........................................................................... 2214.3.42 SLOTSTSSlot Status............................................................................2234.3.43 RCTLRoot Control............................................................................... 2244.3.44 RSTSRoot Status................................................................................ 2264.3.45 DCAP2Device Capabilites 2.................................................................. 2264.3.46 DCTL2Device Control 2........................................................................2284.3.47 LCTL2Link Control 2............................................................................ 2294.3.48 LSTS2Link Status 2.............................................................................2324.3.49 PVCCAP1Port VC Capability Register 1................................................... 2334.3.50 PVCCAP2Port VC Capability Register 2................................................... 2334.3.51 PVCCTLPort VC Control........................................................................2334.3.52 VC0RCAPVC0 Resource Capability......................................................... 2344.3.53 VC0RCTLVC0 Resource Control............................................................. 2344.3.54 VC0RSTSVC0 Resource Status..............................................................235

5.0 Memory Configuration Registers............................................................................... 2365.1 DMIBAR Registers Summary.................................................................................236

5.1.1 DMIVCECHDMI Virtual Channel Enhanced Capability..................................2375.1.2 DMIPVCCAP1DMI Port VC Capability Register 1.........................................2375.1.3 DMIPVCCAP2DMI Port VC Capability Register 2.........................................238

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5.1.4 DMIPVCCTLDMI Port VC Control............................................................. 2385.1.5 DMIVC0RCAPDMI VC0 Resource Capability...............................................2385.1.6 DMIVC0RCTLDMI VC0 Resource Control...................................................2395.1.7 DMIVC0RSTSDMI VC0 Resource Status................................................... 2395.1.8 DMIVC1RCAPDMI VC1 Resource Capability...............................................2405.1.9 DMIVC1RCTLDMI VC1 Resource Control...................................................2405.1.10 DMIVC1RSTSDMI VC1 Resource Status..................................................2415.1.11 DMIVCPRCAPDMI VCp Resource Capability............................................. 2425.1.12 DMIVCPRCTLDMI VCp Resource Control................................................. 2425.1.13 DMIVCPRSTSDMI VCp Resource Status..................................................2435.1.14 DMIVCMRCAPDMI VCm Resource Capability........................................... 2445.1.15 DMIVCMRCTLDMI VCm Resource Control............................................... 2445.1.16 DMIVCMRSTSDMI VCm Resource Status................................................ 2455.1.17 DMIRCLDECHDMI Root Complex Link Declaration....................................2455.1.18 DMIESDDMI Element Self Description....................................................2465.1.19 DMILE1DDMI Link Entry 1 Description................................................... 2465.1.20 DMILE1ADMI Link Entry 1 Address........................................................ 2475.1.21 DMILUE1ADMI Link Upper Entry 1 Address.............................................2475.1.22 DMILE2DDMI Link Entry 2 Description................................................... 2485.1.23 DMILE2ADMI Link Entry 2 Address........................................................ 2485.1.24 LCAPLink Capabilities.......................................................................... 2485.1.25 LCTLLink Control................................................................................ 2505.1.26 LSTSDMI Link Status...........................................................................2505.1.27 LCTL2Link Control 2............................................................................ 2515.1.28 LSTS2Link Status 2.............................................................................2545.1.29 DMIUESTSDMI Uncorrectable Error Status..............................................2545.1.30 DMIUEMSKDMI Uncorrectable Error Mask...............................................2555.1.31 DMIUESEVDMI Uncorrectable Error Severity........................................... 2565.1.32 DMICESTSDMI Correctable Error Status.................................................2565.1.33 DMICEMSKDMI Correctable Error Mask.................................................. 257

5.2 MCHBAR Registers Summary................................................................................ 2575.2.1 TCDDR Bank or Rank Timing parameters................................................. 2595.2.2 TCDDR Bank or Rank Timing Parametrs...................................................2605.2.3 TCBank or Rank timing parameters.........................................................2605.2.4 PMPower-down configuration register......................................................2615.2.5 TCRefresh parameters...........................................................................2615.2.6 TCRefresh timing parameters.................................................................2625.2.7 PMPower Management DIMM Idle Energy.................................................2625.2.8 PMPower Management DIMM Power Down Energy.....................................2625.2.9 PMPower Management DIMM Activate Energy...........................................2635.2.10 PMPower Management DIMM RdCas Energy........................................... 2635.2.11 PMPower Management DIMM WrCas Energy........................................... 2635.2.12 MADAddress decoder Channel configuration register................................2645.2.13 MADAddress decode channel 0............................................................. 2645.2.14 MADAddress decode channel 1............................................................. 2655.2.15 PMSelf refresh config. register.............................................................. 2665.2.16 DDRDDR_PTM_CTL_0_0_0_MCHBAR_PCU..............................................2675.2.17 DRAMDRAM_ENERGY_SCALEFACTOR_0_0_0_MCHBAR............................ 2685.2.18 DRAMDRAM_RAPL_CHANNEL_POWER_FLOOR_0_0_0_MCHBAR................ 2695.2.19 DDRDDR_THERM_PERDIMM_STATUS_0_0_0_MCHBAR_PCU.....................2695.2.20 DDRDDR_WARM_THRESHOLD_CH0_0_0_0_MCHBAR_PCU.......................269

ContentsProcessor


5.2.21 DDRDDR_WARM_THRESHOLD_CH1_0_0_0_MCHBAR_PCU.......................2705.2.22 DDRDDR_HOT_THRESHOLD_CH0_0_0_0_MCHBAR_PCU..........................2705.2.23 DDRDDR_HOT_THRESHOLD_CH1_0_0_0_MCHBAR_PCU..........................2705.2.24 DDRDDR_THERM_INTERRUPT_CONFIG..................................................2715.2.25 PACKAGEPACKAGE_THERM_MARGIN_0_0_0_MCHBAR_PCU..................... 2725.2.26 DDRDDR_DIMM_TEMPERATURE_CH0_0_0_0_MCHBAR_PCU.....................2725.2.27 DDRDDR_DIMM_TEMPERATURE_CH1_0_0_0_MCHBAR_PCU.....................2735.2.28 DDRDDR_THROTTLE_DURATION_CH0_0_0_0_MCHBAR_PCU................... 2735.2.29 DDRDDR_THROTTLE_DURATION_CH1_0_0_0_MCHBAR_PCU................... 2735.2.30 DDRDDR_WARM_BUDGET_CH0_0_0_0_MCHBAR_PCU.............................2745.2.31 DDRDDR_WARM_BUDGET_CH1_0_0_0_MCHBAR_PCU.............................2745.2.32 DDRDDR_HOT_BUDGET_CH0_0_0_0_MCHBAR_PCU............................... 2745.2.33 DDRDDR_HOT_BUDGET_CH1_0_0_0_MCHBAR_PCU............................... 2745.2.34 DRAMDRAM_POWER_LIMIT..................................................................2755.2.35 DRAMDRAM_ENERGY_STATUS............................................................. 2755.2.36 DRAMDRAM_RAPL_PERF_STATUS......................................................... 2765.2.37 PACKAGEPACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU................2765.2.38 CORECORE_PERF_LIMIT_REASONS.......................................................2765.2.39 GRAPHICSGRAPHICS_PERF_LIMIT_REASONS......................................... 2785.2.40 RINGRING_PERF_LIMIT_REASONS........................................................2805.2.41 PRIMARYPRIMARY_PLANE_ENERGY_STATUS.......................................... 2815.2.42 SECONDARYSECONDARY_PLANE_ENERGY_STATUS.................................2815.2.43 PACKAGEPACKAGE_POWER_SKU.......................................................... 2815.2.44 PACKAGEPACKAGE_POWER_SKU_UNIT................................................. 2825.2.45 PACKAGEPACKAGE_ENERGY_STATUS....................................................2825.2.46 GTGT_PERF_STATUS_0_0_0_MCHBAR_PCU........................................... 2835.2.47 IA32IA32_PLATFORM_ID..................................................................... 2835.2.48 RPRP_STATE_LIMITS_0_0_0_MCHBAR_PCU...........................................2835.2.49 RPRP_STATE_CAP_0_0_0_MCHBAR_PCU............................................... 2845.2.50 TEMPERATURETEMPERATURE_TARGET.................................................. 2845.2.51 VRVR_CURRENT_CONFIG.................................................................... 2855.2.52 IA32IA32_THERM_STATUS.................................................................. 2855.2.53 IA32IA32_THERM_INTERRUPT..............................................................2865.2.54 SSKPDSSKPD_0_0_0_MCHBAR_PCU..................................................... 2875.2.55 CONFIGCONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU............................ 2875.2.56 CONFIGCONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU............................... 2885.2.57 CONFIGCONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU............................... 2885.2.58 CONFIGCONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU............................2895.2.59 TURBOTURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU....................... 2895.2.60 DDRMemory Thermal Camarillo Status.................................................. 2905.2.61 CRDTCTL4IOTrk and RRTrk shared credits..............................................291

5.3 GFXVTBAR Registers Summary............................................................................. 2915.3.1 VERVersion Register............................................................................. 2925.3.2 CAPCapability Register.......................................................................... 2925.3.3 ECAPExtended Capability Register.......................................................... 2955.3.4 GCMDGlobal Command Register............................................................. 2975.3.5 GSTSGlobal Status Register................................................................... 3005.3.6 RTADDRRoot-Entry Table Address Register.............................................. 3015.3.7 CCMDContext Command Register........................................................... 3025.3.8 FSTSFault Status Register..................................................................... 3045.3.9 FECTLFault Event Control Register.......................................................... 305

ProcessorContents


5.3.10 FEDATAFault Event Data Register......................................................... 3065.3.11 FEADDRFault Event Address Register.....................................................3065.3.12 FEUADDRFault Event Upper Address Register......................................... 3075.3.13 AFLOGAdvanced Fault Log Register....................................................... 3075.3.14 PMENProtected Memory Enable Register................................................ 3075.3.15 PLMBASEProtected Low-Memory Base Register....................................... 3085.3.16 PLMLIMITProtected Low-Memory Limit Register...................................... 3095.3.17 PHMBASEProtected High-Memory Base Register......................................3095.3.18 PHMLIMITProtected High-Memory Limit Register..................................... 3105.3.19 IQHInvalidation Queue Head Register....................................................3115.3.20 IQTInvalidation Queue Tail Register...................................................... 3115.3.21 IQAInvalidation Queue Address Register................................................ 3125.3.22 ICSInvalidation Completion Status Register............................................3125.3.23 IECTLInvalidation Event Control Register............................................... 3125.3.24 IEDATAInvalidation Event Data Register................................................ 3135.3.25 IEADDRInvalidation Event Address Register........................................... 3135.3.26 IEUADDRInvalidation Event Upper Address Register................................ 3145.3.27 IRTAInterrupt Remapping Table Address Register................................... 3145.3.28 FRCDLFault Recording Low Register...................................................... 3155.3.29 FRCDHFault Recording High Register..................................................... 3155.3.30 IVAInvalidate Address Register.............................................................3175.3.31 IOTLBIOTLB Invalidate Register............................................................3185.3.32 ARCHDISDMA Remap Engine Policy Control............................................3205.3.33 UARCHDISDMA Remap Engine Policy Control..........................................322

5.4 PXPEPBAR Registers Summary..............................................................................3235.4.1 EPVC0RCTLEP VC 0 Resource Control...................................................... 323

5.5 VC0PREMAP Registers Summary........................................................................... 3245.5.1 VERVersion Register............................................................................. 3255.5.2 CAPCapability Register.......................................................................... 3255.5.3 ECAPExtended Capability Register.......................................................... 3285.5.4 GCMDGlobal Command Register............................................................. 3305.5.5 GSTSGlobal Status Register................................................................... 3335.5.6 RTADDRRoot-Entry Table Address Register.............................................. 3345.5.7 CCMDContext Command Register........................................................... 3355.5.8 FSTSFault Status Register..................................................................... 3365.5.9 FECTLFault Event Control Register.......................................................... 3385.5.10 FEDATAFault Event Data Register......................................................... 3395.5.11 FEADDRFault Event Address Register.....................................................3395.5.12 FEUADDRFault Event Upper Address Register......................................... 3395.5.13 AFLOGAdvanced Fault Log Register....................................................... 3395.5.14 PMENProtected Memory Enable Register................................................ 3405.5.15 PLMBASEProtected Low-Memory Base Register....................................... 3415.5.16 PLMLIMITProtected Low-Memory Limit Register...................................... 3415.5.17 PHMBASEProtected High-Memory Base Register......................................3425.5.18 PHMLIMITProtected High-Memory Limit Register..................................... 3425.5.19 IQHInvalidation Queue Head Register....................................................3435.5.20 IQTInvalidation Queue Tail Register...................................................... 3435.5.21 IQAInvalidation Queue Address Register................................................ 3445.5.22 ICSInvalidation Completion Status Register............................................3445.5.23 IECTLInvalidation Event Control Register............................................... 3445.5.24 IEDATAInvalidation Event Data Register................................................ 345

ContentsProcessor


5.5.25 IEADDRInvalidation Event Address Register........................................... 3455.5.26 IEUADDRInvalidation Event Upper Address Register................................ 3465.5.27 IRTAInterrupt Remapping Table Address Register................................... 3465.5.28 IVAInvalidate Address Register.............................................................3475.5.29 IOTLBIOTLB Invalidate Register............................................................3485.5.30 FRCDLFault Recording Low Register...................................................... 3505.5.31 FRCDHFault Recording High Register..................................................... 350

5.6 MEM GTTMMADR Registers Summary.....................................................................3515.6.1 MTOLUDTop of Low Usable DRAM........................................................... 3525.6.2 MTOUUDTop of Upper Usable DRAM........................................................3525.6.3 MBDSMBase Data of Stolen Memory....................................................... 3535.6.4 MBGSMBase of GTT stolen Memory.........................................................3545.6.5 MPMENProtected Memory Enable Register................................................3545.6.6 MPLMBASEProtected Low-Memory Base Register.......................................3555.6.7 MPLMLIMITProtected Low-Memory Limit Register......................................3555.6.8 MPHMBASEProtected High-Memory Base Register..................................... 3565.6.9 MPHMLIMITProtected High-Memory Limit Register.....................................3565.6.10 MPAVPCProtected Audio Video Path Control............................................3575.6.11 MGCMDGlobal Command Register.........................................................3575.6.12 PRIMARYPRIMARY_PLANE_TURBO_POWER_POLICY.................................3605.6.13 SECONDARYSECONDARY_PLANE_TURBO_POWER_POLICY....................... 361

ProcessorContents


Figures1 Conceptual Platform PCI Configuration Diagram for H-Processor Line .............................202 System Address Range Example................................................................................233 DOS Legacy Address Range...................................................................................... 244 PAM Region Space................................................................................................... 265 Main Memory Address Range.....................................................................................276 PCI Memory Address Range...................................................................................... 337 Example: DMI Upstream VC0 Memory Map................................................................. 42

FiguresProcessor


Tables1 Register Attributes and Terminology...........................................................................172 Register Attribute Modifiers.......................................................................................183 PCI Devices and Functions for H-Processor Line .......................................................... 194 PCI Device Enumeration........................................................................................... 195 SMM Regions.......................................................................................................... 376 IGD Frame Buffer Accesses.......................................................................................447 IGD VGA I/O Mapping.............................................................................................. 448 VGA and MDA IO Transaction Mapping........................................................................459 MDA Resources....................................................................................................... 46

ProcessorTables


Revision History

Revision Description Date

001 Initial Release June 2015

Revision HistoryProcessor


1.0 Introduction

This is Volume 2 of the Datasheet for the following product family. Volume 2 providesregister information for the processor.

5th Generation Intel Core processor based on Mobile H-Processor Line

Note: Throughout this document, the product family listed above may be referred to simplyas "processor".

For Volume 1, refer to the following document.

Mobile H-Processor Line, Refer to document number 332378 for the Mobile 5thGeneration Intel Core Processor Family Datasheet Volume 1 of 2

The processor contains one or more PCI devices within a single physical component.The configuration registers for these devices are mapped as devices residing on thePCI Bus assigned for the processor socket. This document describes theseconfiguration space registers or device-specific control and status registers only.

ProcessorIntroduction


2.0 Processor Configuration Register Definitions andAddress Ranges

This chapter describes the processor configuration register I/O and memory addressranges. The chapter provides register terminology. PCI Devices and Functions aredescribed.

Register Terminology

Register Attributes and Terminology table lists the register-related terminology andaccess attributes that are used in this document. Register Attribute Modifiers tableprovides the attribute modifiers.

Table 1. Register Attributes and Terminology

Item Description

RO Read Only: These bits can only be read by software, writes have no effect. The value of thebits is determined by the hardware only.

RW Read / Write: These bits can be read and written by software.

RW1C Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a '1' to a bitwill clear it, while writing a '0' to a bit has no effect. Hardware sets these bits.

RW0C Read / Write 0 to Clear: These bits can be read and cleared by software. Writing a '0' to a bitwill clear it, while writing a '1' to a bit has no effect. Hardware sets these bits.

RW1S Read / Write 1 to Set: These bits can be read and set by software. Writing a '1' to a bit willset it, while writing a '0' to a bit has no effect. Hardware clears these bits.

RsvdP

Reserved and Preserved: These bits are reserved for future RW implementations and theirvalue must not be modified by software. When writing to these bits, software must preserve thevalue read. When SW updates a register that has RsvdP fields, it must read the register valuefirst so that the appropriate merge between the RsvdP and updated fields will occur.

RsvdZ Reserved and Zero: These bits are reserved for future RW1C implementations. Software mustuse 0 for writes.

WOWrite Only: These bits can only be written by software, reads return zero.Note: Use of this attribute type is deprecated and can only be used to describe bits without

persistent state.

RC

Read Clear: These bits can only be read by software, but a read causes the bits to be cleared.Hardware sets these bits.Note: Use of this attribute type is only allowed on legacy functions, as side-effects on reads

are not desirable

RSW1C Read Set / Write 1 to Clear: These bits can be read and cleared by software. Reading a bitwill set the bit to '1'. Writing a '1' to a bit will clear it, while writing a '0' to a bit has no effect.

RCW

Read Clear / Write: These bits can be read and written by software, but a read causes thebits to be cleared.Note: Use of this attribute type is only allowed on legacy functions, as side-effects on reads

are not desirable.

2.1

Processor Configuration Register Definitions and Address RangesProcessor


Table 2. Register Attribute Modifiers

AttributeModifier

ApplicableAttribute

Description

S

RO (w/ -V) Sticky : These bits are only re-initialized to their default value by a "Power GoodReset".Note: Does not apply to RO (constant) bits.RW

RW1C

RW1S

-K RW Key: These bits control the ability to write other bits (identified with a 'Lock'modifier)

-LRW Lock: Hardware can make these bits "Read Only" using a separate configuration

bit or other logic.Note: Mutually exclusive with 'Once' modifier.WO

-O

RW Once: After reset, these bits can only be written by software once, after whichthey become "Read Only".Note: Mutually exclusive with 'Lock' modifier and does not make sense with

'Variant' modifier.WO

-FW RO Firmware Write: The value of these bits can be updated by firmware (PCU, TAP,and so on).

-V ROVariant: The value of these bits can be updated by hardware.Note: RW1C and RC bits are variant by definition and therefore do not need to

be modified.

PCI Devices and Functions

The processor contains the following PCI devices within a single component. Theconfiguration registers for the devices are mapped as devices residing on PCI Bus 0.

Device 0: Host Bridge / DRAM Controller / LLC Controller0 Logically this deviceappears as a PCI device residing on PCI bus 0. Device 0 contains the standard PCIheader registers, PCI Express base address register, DRAM control (includingthermal/throttling control), configuration for the DMI, and other processor specificregisters.

Device 1: Host-PCI Express* Bridge - Logically this device appears as a "virtual"PCI-to-PCI bridge residing on PCI bus 0, and is compliant with the PCI-to-PCIBridge Architecture Specification, Revision 1.2. Device 1 is a multi-function device(MFD) consisting of three functions (0, 1, and 2). Device 1 contains the standardPCI-to-PCI bridge registers and the standard PCI Express/PCI configurationregisters.

Device 2: Integrated Graphics Device Logically, this device appears as a PCIdevice residing on PCI bus 0. Physically, Device 2 contains the configurationregisters for 3D, 2D, and display functions. In addition, Device 2 is located in twoseparate physical locations GT and Display Engine.

Device 3: High Definition Audio controller. This device contains registers used ascontrol and status for integrated audio controller. Previous implementation of thiscontroller was in the PCH.

2.2

ProcessorProcessor Configuration Register Definitions and Address Ranges


Table 3. PCI Devices and Functions for H-Processor Line

Description DID (Mobile) Bus Device Functions

HOST Bridge 0x1614 0 0 0

PCI Express*Controller (x16 PCIe) 0x1601 0 1 0



Integrated GraphicsDevice

N/A -GT1

0 2 00x1612 - GT2

0x1622 - GT3

Audio Controller 0x160C 0 3 0

Notes: 1. Not all devices are enabled in all configurations.2. DID values in this table differ from what is listed at the register ID description tables. The values

listed in this table are the correct DID default values.

From a configuration standpoint, the DMI is logically PCI bus 0. As a result, all devicesinternal to the processor and the PCH appear to be on PCI bus 0.

For H-Processor Line 2-chip LGA/BGA, the PCI Express controllers (PEG10, PEG11, andPEG12) appear to system software to be real PCI buses behind PCI-to-PCI bridges thatare devices resident on PCI bus 0. This is shown in Figure 1 on page 20.

Table 4. PCI Device Enumeration

Segment Bus ID [7:0] Device ID [4:0] Function ID[2:0]

Endpoint

H-Processor Line 0x00 00000b (0) 000 (0) Host Bridge

H-Processor Line0x00 00001b (1) 000 (0)

PEG Root Port10 - x16controller


PEG Root Port11 - x8

controller


PEG Root Port12 - x4

controller

H-Processor Line 0x00 00010b (2) 000 (0) IntegratedGraphics Device

H-Processor Line 0x00 00011b (3) 000 (0) Audio Controller



Figure 1. Conceptual Platform PCI Configuration Diagram for H-Processor Line

PCI Configuration Window

Host PCI Express Bridge- Bus 0, Device 1, Function 0- Bus 0, Device 1, Function 1- Bus 0, Device 1, Function 2

Host Bridge, DRAM Controller

Bus 0, Device 0, Function 0

Host Bridge, DRAM Controller

Bus 0, Device 2, Function 0

Audio ControllerBus 0, Device 3, Function 0

DMI

DMI

Processor

PCH

System Address Map

The processor supports 512 GB (39 bits) of addressable memory space and 64 KB+3of addressable I/O space.

This section focuses on how the memory space is partitioned and how the separatememory regions are used. I/O address space has simpler mapping and is explainedtowards the end of this chapter.

2.3



The processor supports PEG port upper prefetchable base/limit registers. This allowsthe PEG unit to claim I/O accesses above 32 bit. Addressing of greater than 4 GB isallowed on either the DMI Interface or PCI Express interface.

The processor supports a maximum of 32 GB of DRAM. No DRAM memory will beaccessible above 32 GB. DRAM capacity is limited by the number of address pinsavailable. There is no hardware lock to prevent more memory from being insertedthan is addressable.

When running in internal graphics mode, processor initiated TileX/TileY/linear reads/writes to GMADR range are supported. Write accesses to GMADR linear regions aresupported from DMI and PEG. GMADR write accesses to TileX and TileY regions(defined using fence registers) are not supported from the DMI or the PEG port.GMADR read accesses are not supported from DMI or PEG.

In the following sections, it is assumed that all of the compatibility memory rangesreside on the DMI Interface. The exception to this rule is VGA ranges, which may bemapped to PCI Express*, DMI, or to the internal graphics device (IGD). In theabsence of more specific references, cycle descriptions referencing PCI should beinterpreted as the DMI Interface/PCI, while cycle descriptions referencing PCI Expressor IGD are related to the PCI Express bus or the internal graphics device respectively.The processor does not remap APIC or any other memory spaces above TOLUD (Topof Low Usable DRAM). The TOLUD register is set to the appropriate value by BIOS.The remapbase/remaplimit registers remap logical accesses bound for addressesabove 4 GB onto physical addresses that fall within DRAM.

The Address Map includes a number of programmable ranges:

Device 0:

PXPEPBAR PxP egress port registers. (4 KB window)

MCHBAR Memory mapped range for internal MCH registers. (32 KB window)

DMIBAR This window is used to access registers associated with theprocessor/PCH Serial Interconnect (DMI) register memory range. (4 KBwindow)

GGC.GMS Graphics Mode Select. Used to select the amount of main memorythat is pre-allocated to support the internal graphics device in VGA (non-linear) and Native (linear) modes. (0 512 MB options).

GGC.GGMS GTT Graphics Memory Size. Used to select the amount of mainmemory that is pre-allocated to support the Internal Graphics TranslationTable. (0 2 MB options).

For each of the following device functions

Device 1, Function 0: (PCIe x16 Controller)



Device 2, Function 0: (Integrated Graphics Device (IGD))

IOBAR I/O access window for internal graphics. Through this windowaddress/data register pair, using I/O semantics, the IGD and internal graphicsinstruction port registers can be accessed. This allows accessing the sameregisters as GTTMMADR. The IOBAR can be used to issue writes to theGTTMMADR or the GTT Table.



GMADR Internal graphics translation window (128 MB, 256 MB, 512 MBwindow).

GTTMMADR This register requests a 4 MB allocation for combined GraphicsTranslation Table Modification Range and Memory Mapped Range. GTTADR willbe at GTTMMADR + 2 MB while the MMIO base address will be the same asGTTMMADR

Device 3, Function 0: (Audio Controller)

The rules for the above programmable ranges are:

1. For security reasons, the processor will now positively decode ( FFE0_0000h toFFFF_FFFFh) to DMI. This ensures the boot vector and BIOS execute off the PCH.

2. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS orsystem designer's responsibility to limit memory population so that adequate PCI,PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memoryspace can be allocated.

3. In the case of overlapping ranges with memory, the memory decode will be givenpriority. This is an Intel Trusted Execution Technology (Intel TXT) requirement.It is necessary to get Intel TXT protection checks, avoiding potential attacks.

4. There are NO Hardware Interlocks to prevent problems in the case of overlappingranges.

5. Accesses to overlapped ranges may produce indeterminate results.

6. The only peer-to-peer cycles allowed below the Top of Low Usable memory(register TOLUD) are DMI Interface to PCI Express VGA range writes. Peer-to-peercycles to the Internal Graphics VGA range are not supported.



Figure 2. System Address Range Example

Main Memory Add Range

OS VISIBLE< 4 GB

PCI Memory Add. Range

(subtractively decoded to

DMI)

Host/System ViewPhysical Memory

(DRAM Controller View)

TSEG

00

TSEG BASE

GFX Stolen(0-256MB)

ME-UMA

TOM

GFX GTT Stolen BASE

MESEG BASE

1 MB aligned

1 MB aligned

OS Invisible Reclaim

1 MB aligned for reclaim

1 MB aligned

4GB

FEC0_0000

GFX GTT STOLEN(0-2MB)

GFX Stolen BASE 1 MB aligned

TSEG (0-8MB)

Legacy Add. Range

1 MB

Main Memory Address Range

OS visible > 4GB

Main Memory Reclaim Add

RangeReclaim BASE

1 MB aligned

TOUUD BASEReclaim Limit

= Reclaim Base +X

1 MB aligned

PCI Memory Add. Range

(subtractively decoded to

DMI)

1 MB aligned

512G

X

Flash, APIC LT(20 MB)

TOLUD BASE1 MB aligned

Legacy Address Range

The memory address range from 0 to 1 MB is known as Legacy Address. This area isdivided into the following address regions:

0 640 KB - DOS Area

640 768 KB - Legacy Video Buffer Area

768 896 KB in 16 KB sections (total of 8 sections) Expansion Area

896 960 KB in 16 KB sections (total of 4 sections) Extended System BIOS Area

2.4



960 KB 1 MB Memory, System BIOS Area

The area between 768 KB 1 MB is also collectively referred to as PAM(Programmable Address Memory). All accesses to the DOS and PAM ranges from anydevice are sent to DRAM. However, access to the legacy video buffer area is treateddifferently.

Assumption: GT never sends requests in the Legacy Address Range; thus, there is noblocking of GT requests to this range in the System Agent.

Figure 3. DOS Legacy Address Range

Expans ion Area128 KB ( 16 KB x 8 )

000C_0000h

000D_FFFFh896 KB

Ex tended S ys tem B I OS ( Lower)64 KB ( 16 KB x 4 )000E_0000h

000E_FFFFh960 KB

Legacy V ideo Area( S MM Memory )

128 KB

000A_0000h

000B_FFFFh768 KB

DOS Area

0000_0000h

0009_FFFFh640 KB

S ys tem B I OS ( Upper)64 KB000F_0000h

000F_FFFFh1 MB



DOS Range (0h 9_FFFFh)

The DOS area is 640 KB (0000_0000h 0009_FFFFh) in size and is always mapped tothe main memory.

Legacy Video Area / Compatible SMRAM Area (A_0000h B_FFFFh)

The same address region is used for both Legacy Video Area and Compatible SMRAM.

Legacy Video Area: The legacy 128 KB VGA memory range, frame buffer, at000A_0000h 000B_FFFFh, can be mapped to IGD (Device 2), to PCI Express(Device 1), and/or to the DMI Interface.

Monochrome Adapter (MDA) Range: Legacy support requires the ability to have asecond graphics controller (monochrome) in the system. The monochromeadapter may be mapped to IGD, PCI Express or DMI. Like the Legacy Video Area,decode priority is given first to IGD, then to PCI Express, and finally to DMI.

Compatible SMRAM Address Range:

Legacy Video Area

The legacy 128 KB VGA memory range, frame buffer at 000A_0000h 000B_FFFFh,can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMIInterface.

Monochrome Adapter (MDA) Range

Legacy support requires the ability to have a second graphics controller(monochrome) in the system. The monochrome adapter may be mapped to IGD, PCIExpress or DMI. Like the Legacy Video Area, decode priority is given first to IGD, thento PCI Express, and finally to DMI.

Compatible SMRAM Address Range

When compatible SMM space is enabled, SMM-mode CBO accesses to this range routeto physical system DRAM at 00_000A_0000h 00_000B_FFFFh.

Non-SMM mode CBO accesses to this range are considered to be to the Video BufferArea as described above. PCI Express and DMI originated cycles to SMM space are notsupported and are considered to be to the Video Buffer Area.

The processor always positively decodes internally mapped devices, namely the IGDand PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMIInterface depends on the Legacy VGA configuration bits (VGA Enable and MDAP). Thisregion is also the default for SMM space.

Programmable Attribute Map (PAM) (C_0000h F_FFFFh)

PAM is a legacy BIOS ROM area in MMIO. It is overlaid with DRAM and used as afaster ROM storage area. It has a fixed base address (000C_0000h) and fix size of256 KB. The 13 sections from 768 KB to 1 MB comprise what is also known as thePAM Memory Area. Each section has Read enable and Write enable attributes.



Figure 4. PAM Region Space

10_000

F_0000

PAM 0

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

E_4000

E_8000PAM 6

PAM 5

PAM 4

PAM 3

PAM 2

PAM 1

E_4000

E_0000

D_C000

D_8000

D_4000

D_0000

C_C000

C_8000

C_4000

C_0000

64 KB

32 KB

The PAM registers are mapped in Device 0 configuration space.

ISA Expansion Area (C_0000h D_FFFFh)

Extended System BIOS Area (E_0000h E_FFFFh)

System BIOS Area (F_0000h F_FFFFh)

The processor decodes the Core request, then routes to the appropriate destination(DRAM or DMI).

Snooped accesses from PCI Express or DMI to this region are snooped on processorCaches.

Non-snooped accesses from PCI Express or DMI to this region are always sent toDRAM.

Graphics translated requests to this region are not allowed. If such a mapping erroroccurs, the request will be routed to C_0000h. Writes will have the byte enables de-asserted.

Main Memory Address Range (1 MB TOLUD)

This address range extends from 1 MB to the top of Low Usable physical memory thatis permitted to be accessible by the processor (as programmed in the TOLUDregister). The processor will route all addresses within this range to the DRAM unlessit falls into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.

2.5



This address range is divided into two sub-ranges:

1 MB to TSEGMB

TSEGMB to TOULUD

TSEGMB indicates the TSEG Memory Base address.

Figure 5. Main Memory Address Range

Main Memory

ISA Hole (optional)

DOS Compatibility Memory

0h

FLASHFFFF_FFFFh

00F0_0000h 15 MB

16 MB0100_0000h

0 MB

TOLUD

APIC

Main Memory

0010_0000h 1 MB

IGD

Intel TXT

PCI Memory Range

4 GB Max

TSEG

IGGTT

DPR

TSEG_BASE

ISA Hole (15 MB 16 MB)

The ISA Hole (starting at address F0_0000h) is enabled in the Legacy Access ControlRegister in Device 0 configuration space. If no hole is created, the processor will routethe request to DRAM. If a hole is created, the processor will route the request to DMI,since the request does not target DRAM. These downstream requests will be sent toDMI (subtractive decoding).



Graphics translated requests to the range will always route to DRAM.

1 MB to TSEGMB

Processor access to this range will be directed to memory, unless the ISA Hole isenabled.

TSEG

For processor initiated transactions, the processor relies on correct programming ofSMM Range Registers (SMRR) to enforce TSEG protection.

TSEG is below IGD stolen memory, which is at the Top of Low Usable physical memory(TOLUD). BIOS will calculate and program the TSEG BASE in Device 0 (TSEGMB), usedto protect this region from DMA access. Calculation is:

TSEGMB = TOLUD DSM SIZE GSM SIZE TSEG SIZE

SMM-mode processor accesses to enabled TSEG access the physical DRAM at thesame address.

When the extended SMRAM space is enabled, processor accesses to the TSEG rangewithout SMM attribute or without WB attribute are handled by the processor as invalidaccesses.

Non-processor originated accesses are not allowed to SMM space. PCI-Express, DMI,and Internal Graphics originated cycles to enabled SMM space are handled as invalidcycle type with reads and writes to location C_0000h and byte enables turned off forwrites.

Protected Memory Range (PMR) - (programmable)

For robust and secure launch of the MVMM, the MVMM code and private data need tobe loaded to a memory region protected from bus master accesses. Support forprotected memory region is required for DMA-remapping hardware implementationson platforms supporting Intel TXT, and is optional for non-Intel TXT platforms. Sincethe protected memory region needs to be enabled before the MVMM is launched,hardware must support enabling of the protected memory region independently fromenabling the DMA-remapping hardware.

As part of the secure launch process, the SINIT-AC module verifies the protectedmemory regions are properly configured and enabled. Once launched, the MVMM cansetup the initial DMA-remapping structures in protected memory (to ensure they areprotected while being setup) before enabling the DMA-remapping hardware units.

To optimally support platform configurations supporting varying amounts of mainmemory, the protected memory region is defined as two non-overlapping regions:

Protected Low-memory Region: This is defined as the protected memoryregion below 4 GB to hold the MVMM code/private data, and the initial DMA-remapping structures that control DMA to host physical addresses below 4 GB.DMA-remapping hardware implementations on platforms supporting Intel TXT arerequired to support protected low-memory region 5.

Protected High-memory Region: This is defined as a variable sized protectedmemory region above 4 GB, enough to hold the initial DMA-remapping structuresfor managing DMA accesses to addresses above 4 GB. DMA-remapping hardware



implementations on platforms supporting Intel TXT are required to supportprotected high-memory region 6, if the platform supports main memory above4 GB.

Once the protected low/high memory region registers are configured, bus masterprotection to these regions is enabled through the Protected Memory Enable register.For platforms with multiple DMA-remapping hardware units, each of the DMA-remapping hardware units must be configured with the same protected memoryregions and enabled.

DRAM Protected Range (DPR)

This protection range only applies to DMA accesses and GMADR translations. It servesa purpose of providing a memory range that is only accessible to processor streams.The range just below TSEGMB is protected from DMA accesses.

The DPR range works independent of any other range, including the PMRC checks inIntel VT-d. It occurs post any Intel VT-d translation. Therefore, incoming cycles arechecked against this range after the Intel VT-d translation and faulted if they hit thisprotected range, even if they passed the Intel VT-d translation.

The system will set up:

0 to (TSEG_BASE DPR size 1) for DMA traffic

TSEG_BASE to (TSEG_BASE DPR size) as no DMA.

After some time, software could request more space for not allowing DMA. It will getsome more pages and make sure there are no DMA cycles to the new region. DPR sizeis changed to the new value. When it does this, there should not be any DMA cyclesgoing to DRAM to the new region.

If there were cycles from a rogue device to the new region, then those cycles coulduse the previous decode until the new decode can ensure PV. No flushing of cycles isrequired. On a clock-by-clock basis proper decode with the previous or new decodeneeds to be ensured.

All upstream cycles from 0 to (TSEG_BASE 1 DPR size), and not in the legacyholes (VGA), are decoded to DRAM.

Because Bus Master cycles can occur when the DPR size is changed, the DPR sizeneeds to be treated dynamically.

Pre-allocated Memory

Voids of physical addresses that are not accessible as general system memory andreside within the system memory address range (< TOLUD) are created for SMM-mode, legacy VGA graphics compatibility, and GFX GTT stolen memory. It is theresponsibility of BIOS to properly initialize these regions.

Main Memory Address Space (4 GB to TOUUD)

The maximum main memory size supported is 32 GB total DRAM memory.

A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB orlarger. As a result, TOM and TOUUD registers and REMAPBASE/REMAPLIMIT registersbecome relevant.

2.6



The remap configuration registers exist to remap lost main memory space. Thegreater than 32-bit remap handling will be handled similar to other MCHs.

Upstream read and write accesses above 39-bit addressing will be treated as invalidcycles by PEG and DMI.

Top of Memory (TOM)

The "Top of Memory" (TOM) register reflects the total amount of populated physicalmemory. This is NOT necessarily the highest main memory address (holes may existin main memory address map due to addresses allocated for memory mapped IOabove TOM).

On Front Side Bus (FSB) chipsets, the TOM was used to allocate the Intel ManagementEngine (Intel ME) stolen memory. The Intel ME stolen size register reflects the totalamount of physical memory stolen by the Intel ME. The Intel ME stolen memory islocated at the top of physical memory. The Intel ME stolen memory base is calculatedby subtracting the amount of memory stolen by the Intel ME from TOM.

Top of Upper Usable DRAM (TOUUD)

The Top of Upper Usable DRAM (TOUUD) register reflects the total amount ofaddressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Intel ME stolensize. If remap is enabled, then it will reflect the remap limit. When there is more than4 GB of DRAM and reclaim is enabled, the reclaim base will be the same as TOM minusIntel ME stolen memory size to the nearest 1 MB alignment.

Top of Low Usable DRAM (TOLUD)

TOLUD register is restricted to 4 GB memory (A[31:20]), but the processor cansupport up to 32 GB, limited by DRAM pins. For physical memory greater than 4 GB,the TOUUD register helps identify the address range between the 4 GB boundary andthe top of physical memory. This identifies memory that can be directly accessed(including remap address calculation) that is useful for memory access indication andearly path indication. TOLUD can be 1 MB aligned.

TSEG_BASE

The "TSEG_BASE" register reflects the total amount of low addressable DRAM, belowTOLUD. BIOS will calculate memory size and program this register; thus, the systemagent has knowledge of where (TOLUD) (Gfx stolen) (Gfx GTT stolen) (TSEG) islocated. I/O blocks use this minus DPR for upstream DRAM decode.

Memory Re-claim Background

The following are examples of Memory Mapped IO devices that are typically locatedbelow 4 GB:

High BIOS

TSEG

GFX stolen

GTT stolen

XAPIC

Local APIC

MSI Interrupts



Mbase/Mlimit

Pmbase/PMlimit

Memory Mapped IO space that supports only 32B addressing

The processor provides the capability to re-claim the physical memory overlapped bythe Memory Mapped IO logical address space. The MCH re-maps physical memoryfrom the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to anequivalent sized logical address range located just below the Intel ME stolen memory.

Indirect Accesses to MCHBAR Registers

Similar to prior chipsets, MCHBAR registers can be indirectly accessed using:

Direct MCHBAR access decode:

Cycle to memory from processor

Hits MCHBAR base, AND

MCHBAR is enabled, AND

With

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