Text of Mid semester Presentation Data Packages Generator & Flow Management Data Packages Generator & Flow...
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Mid semester Presentation Data Packages Generator & Flow
Management Data Packages Generator & Flow Management Data
Packages Generator & Flow Management Supervisor: Mony Orbach
D0317 One-Semester Project Liran Tzafri Michael Gartsbein
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" Background Desired System Parallel Processing System Based on
Altera FPGA Using Nios core Sampling System PreprocessingSystem
Data Stream Analog Input N
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" Equivalent System Data Stream Parallel Processing System
Based on Altera FPGA Using Nios core Parallel accelerator Algorithm
MultiCore Embedded System PCI ProcStarII board Based on STRATIX II
Data Packages Generator & Flow Management Our Project
" The Host Application System flow: System flow: Host
Application generates times of arrival (TOA) vector in software The
Host App sends the vectors to the hardware system and gets the
results The communication is through PCI bus It will also make
processing in software The results are analized In multi processors
system we will try to use different load balancing schemes
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" Project Objectives Programming the Host application, which
will generate the data Programming the Host application, which will
generate the data Creating modular design Defining the interface
and protocol to the board with the relevant groups Adding software
processing to the Host program for comparison with hardware Adding
software processing to the Host program for comparison with
hardware Testing simulations results Testing simulations
results
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" Stratix 2 FPGA on Altera board PCI bus Host PCs fan
Tools
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" Tools Stratix 2 FPGA Altera board Altera board Gidels Proc
wizard and IP cores Gidels Proc wizard and IP cores Host PC Host PC
Visual Studio 2005 Visual Studio 2005
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" Host Application Interface Inputs Inputs Packet noise
parameters Missing elements parameters Region of interest Operation
mode Outputs Outputs System throughput Vectors after hardware or
software processing This image is for illustation only
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Packet Structure : Packet Generator Output *
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Packet Structure : Packet Receiver Input * *For further details
see the Packet Structure document
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" Packet Generator\Receiver Interface Inputs Inputs Was the
data series identified Average period Number of values assigned to
the data series Indexes of these values Outputs Outputs TOA vectors
of random length between 8 to 1024 Each TOA is a DWORD (32 bits)
Each vector has 1 to 3 data series with a random period between 10
to 10000, and noise Percentage of noise in each vector is an input
to the Host App Percentage of missing data from each vector is an
input to the Host App
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Host App Operation Modes In order to check the performance of
the system, there will be two modes of operation: Correctness test:
Checks correctness for finite number of packets Performance test:
Packets will be sent continuously, elaborated in next slides
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Packet Send Chain Packets are generated continuously, by the
Packet Generator. Here, the Packet contains only the data (TOAs),
an ID, and the length The Packets are forwarded to the Packetizer,
which adds a header and footer to the packet, according to the
interface
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Packet Send Chain (Cont.) The Packetizer then forwards a bit
stream to the RxTx entity The data is then sent immediately to the
hardware (using DMA and Gidels API) Several sending techniques will
be examined in order to maximally utilize the PCI bus
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Packet Receive Chain While there is data in hardware, it is
read continuously, and stored in a local FIFO The Depacketizer
entity transforms the DWORD stream from the FIFO into packets
Performance of the system is checked: number of packets processed
compared with the run time
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" This page was left blank on purpose
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" Special Problems Problem: Naming the project with a
meaningful name Problem: Naming the project with a meaningful name
Solution: Packet I/O Software Management Application (PISMA)
Solution: Packet I/O Software Management Application (PISMA)
Problem: Integration and synchronicity between different project
parts/groups Problem: Integration and synchronicity between
different project parts/groups Solution: Defining an all-accepted
Interface Problem: Debugging hardware and software simultaneously
Problem: Debugging hardware and software simultaneously
Solution:
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" Schedule AssignmentDate Learning the system blocks and Gidels
API1.10-19.10 Checking feasibility and communication between
units20.10-12.11 Design of the Host program7.11-22.11
Characterization presentation20.11 Implementing the packet
generator Creating basic I/O loop with the hardware Defining the
interface with other groups Mid semester presentation 23.11-3.12
4.12-12.12 22.12 16.1
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" Schedule (cont.) AssignmentDate Transition from Simple to
Multi FIFO2.1-11.1 Integration of Pulse Deinterleaver Algorithm in
software12.1-16.1 Create the Depacketizer Entity17.1-22.1 Implement
the systems two modes of operation23.1-24.1 Debug of system Test of
system Final presentation 25.1-10.2 11.2-17.2 18.2-20.2
