Microprocessor based System Design_1_Lec

Microprocessor based System Design

Ravi S Gupta

Organization• Goals of the Course• Historical Perspective - Microprocessors• The Technology Aspect: Moore’s Law• Inside a Microprocessor• Processor system architecture• Computer Classification• Advantages of Microprocessor based system design• Disadvantages of Microprocessor based system design• Microcontroller• Digital Signal Processor• Functional and Architecture description of 8085• Pin description of 8085• Memory Interfacing• Addressing Modes in 8085• Instruction Set of 8085• Interrupts of 8085• Timing Diagram of 8085

Goals and ObjectivesIn this course, you will:

Learn how the hardware (HW) and software (SW) components of a microprocessor-based system work together to implement digital systems.Learn both HW and SW aspects of integrating digital devices (memory, I/O interfaces, etc.) into microprocessor systems.Get practical hands-on experience in system design and assembly language programming.

In the classroom lectures, you will learn more about thehardware architecture aspects of microprocessors, theirinternal building blocks, operation principles, interfacingwith other digital systems etc…

In the laboratory sessions, you will learn more about themachine code and assembly language programming ofmicroprocessors, and implementation of digital systemsusing these devices.

Goals and Objectives

Microprocessors are found almost everywhere

Microprocessor HistoryA microprocessor -- also known as a CPU or central

processing unit -- is a complete computationengine that is fabricated on a single chip.

The first microprocessor was the Intel 4004,introduced in 1971. The 4004 was not verypowerful -- all it could do was add and subtract,and it could only do that 4 bits at a time. But itwas amazing that everything was on one chip. Priorto the 4004, engineers built computers either fromcollections of chips or from discrete components(transistors). The 4004 powered one of the firstportable electronic calculators.

The first microprocessor to make it into a homecomputer was the Intel 8080, a complete 8-bitcomputer on one chip, introduced in 1974. Thefirst microprocessor to make a real splash in themarket was the Intel 8088, introduced in 1979and incorporated into the IBM PC (which firstappeared around 1982).

If you are familiar with the PC market and its history,you know that the PC market moved from the 8088to the 80286 to the 80386 to the 80486 to thePentium to the Pentium II to the Pentium III to thePentium 4. All of these microprocessors are madeby Intel and all of them are improvements on thebasic design of the 8088. The Pentium 4 canexecute any piece of code that ran on the original8088, but it does it about 5,000 times faster!

Historical PerspectiveN am e Da te Tran sisto rs M ic rons Clock

speed Da ta width M IPS

8080 1974 6,000 6 2 MH z 8 bits 0.64

8088 1979 29 ,000 3 5 MH z 16 b its 8 -b it bus 0.33

80286 1982 134 ,000 1 .5 6 MH z 16 b its 1 80386 1985 275 ,000 1 .5 16 MHz 32 b its 5 80486 1989 1,200,000 1 25 MHz 32 b its 20

P en tium 1993 3,100,000 0 .8 60 MHz 32 b its 64 -b it

bus 100

P en tium II 1997 7,500,000 0.35 233 M Hz

32 b its 64 -b it

bus ~300

P en tium III 1999 9,500,000 0.25 450 M Hz

32 b its 64 -b it

bus ~510

P en tium 4 2000 42 ,000,000 0.18 1 .5 G Hz

32 b its 64 -b it

bus ~1 ,700

• The date is the year that the processor was firstintroduced.

• Transistors is the number of transistors on thechip. You can see that the number of transistorson a single chip has risen steadily over the years.

• Microns is the width, in microns, of the smallestwire on the chip. For comparison, a human hair is100 microns thick. As the feature size on the chipgoes down, the number of transistors rises.

• Clock speed is the maximum rate that the chipcan be clocked at.

• Data Width is the width of the ALU. An 8-bit ALUcan add/subtract/multiply/etc. two 8-bitnumbers, while a 32-bit ALU can manipulate 32-bit numbers.

• MIPS stands for "millions of instructions persecond" and is a rough measure of the performanceof a CPU.

Inside a Microprocessor• The microprocessor is a semiconductor device

(Integrated Circuit) manufactured by the VLSI (VeryLarge Scale Integration) technique. It includes the ALU,register arrays and control circuit on a single chip. Toperform a function or useful task we have to form asystem by using microprocessor as a CPU andinterfacing memory, input and output devices to it.A system designed using a microprocessor as its CPU iscalled a microcomputer.

• The Microprocessor based system (single boardmicrocomputer) consists of microprocessor as CPU,semiconductor memories like EPROM and RAM, inputdevice, output device and interfacing devices. Thememories, input device, output device and interfacingdevices are called peripherals.

• The popular input devices are keyboard and floppy diskand the output devices are printer, LED/LCD displays,CRT monitor, etc.

Memory

Input Output

ALU

CU

CPU

Block Diagram of a computer with the Microprocessor as CPU

CPU-> Central Processing UnitALU -> Arithmetic and Logical UnitCU -> Control Unit

Microprocessor based system

Processor System ArchitectureThe typical processor system consists of:

CPU (central processing unit) ALU (arithmetic-logic unit) Control Logic Registers, etc…

Memory Input / Output interfaces

Interconnections between these units: Address Bus Data Bus Control Bus

Bus and CPUBus: A shared group of wires used for communicating

signals among devices.– address bus: the device and the location within

the device that is being accessed, unidirectional– data bus: the data value being communicated,

bidirectional– control bus: describes the action on the address

and data buses; like Reset the deviceCPU: Core of the processor, where instructions are

executed– High-level language: a = b + c– Assembly language: add r1 r2 r3– Machine language: 0001001010111010101

Central Processing UnitMicroprocessor consists of ALU, REGISTER ARRAY

and CONTROL UNIT. • ALU (Arithmetic and Logical Unit): Computing

functions are performed on data in this area ofmicroprocessor. It performs arithmetic and logicoperations.

• REGISTER ARRAY: It is a group of variousregisters. They are used to store data temporarilyduring the execution of a program.

• CONTROL UNIT: It controls the flow of databetween the microprocessor and peripherals (I/0ports and memory) by sending proper timing andcontrol signals.

Memory and I/O• Memory: Where instructions (programs) and data are

stored.– stores binary information, called instructions and

data.– provides the instructions and data to the

microprocessor on request.– stores results and data for the microprocessor.

• I/O devices: Enable system to interact with the world.– Device interface (a.k.a. controller or adapter)

hardware connects actual device to bus– The CPU views the I/O device registers just like

memory that can be accessed over the bus. However, I/O registers are connected to external wires, device control logic, etc.

– The I/P device enters data and instructions under the control of a program such as a monitor program.

– The O/P device accepts data from the microprocessor as specified in a program.

Computer classificationComputers are divided into three categories as per the

superiority and number of microprocessors used. Theseare:

• A microcomputer is a small computer containing onlya single central processing unit (CPU). Their wordlength varies between 8 and 32 bits and used in smallindustrial and process control systems. The storagecapacity and speed requirements of microcomputers aremoderate.

• Mini computers are having more storage capacity andmore speed than micro computers. Mini computers areused in research, data processing, scientificcalculations etc.

• Mainframe computers are designed to work at veryhigh speed and they have very high storage capacity.Their word length is typically 64-bits. These are usedfor research, data processing, graphic applications, etc.

Advantages of Microprocessor based system

• Computational/processing speed is high.• Intelligence has been brought to systems.• Automation of industrial processes and office

administration.• Since the devices are programmable, there is

flexibility to alter the system by changing thesoftware alone.

• Less number of components, compact in size andcost less. Also it is more reliable.

• Operation and maintenance are easier.

Disadvantages of Microprocessor based System

• It has limitations on the size of data.• The applications are limited by the physical

address space.• The analog signals cannot be processed directly

and digitizing the analog signals introduces errors.• The speed of execution is slow and so real time

applications are not possible.• Most of the microprocessors does not support

floating point operations.

Microcontrollers• Integration of Microprocessor along with I/O

ports and minimum memory in a single packageis named as microcontroller.

• Peripherals like programmable timer is alsoincluded in a single package.

• Sometimes microcontroller is called single chipmicro-computer.

ROM/RAM Memory

I/O Ports

Peripheral Timer

MicroProcessor

Digital Signal Processors• A Digital Signal Processor is a special-purpose

CPU (Central Processing Unit) that provides ultra-fast instruction sequences, such as shift and add,and multiply and add, which are commonly used inmath-intensive signal processing applications.

• A digital signal processor (DSP) is a specializedmicroprocessor designed specifically for digitalsignal processing, generally in real time.

• Digital – operating by the use of discrete signals to

represent data in the form of numbers. • Signal

– a variable parameter by which information is conveyed through an electronic circuit.

• Processing – to perform operations on data according to

programmed instructions.

• Characteristics of Digital Signal Processors: – Separate program and data memories. – Only parallel processing, no multitasking. – The ability to act as a direct memory access

device if in a host environment.– Takes digital data from ADC (Analog-Digital

Converter) and passes out data which is finally output by converting into analog by DAC (Digital-Analog Converter).

– analog input-->ADC-->DSP-->DAC--> analog output.

8085 Model

• A model is a conceptualrepresentation of a real object.

• The Microprocessor can berepresented in terms of its:– Hardware Model, and– Programming Model.

8085 Hardware Model

Accumulator

ALU

Flags

Instruction Decoder

Register Array

MemoryPointer Reg

16-bit AddressBus

8-bit DataBus

Control Signals

Timing and Control

8085 Programming Model

The programming model consists of following components:

• Arithmetic logic unit and Registers• Accumulator• Flags • Program Counter• Stack Pointer

ARITHMETIC LOGIC UNIT (ALU)

• The arithmetic logic unit is the heart of themicroprocessor.

• ALU is used in computing function.• It is used to perform certain arithmetic

operations such as addition, subtraction etcand logical operations such as AND, OR,EX-OR etc. and the result is stored in theaccumulator and the flags are set or resetaccording to the result of the operation.

• ALU includes the accumulator, temporaryregister, arithmetic and logic circuits andfive flags.

Registers

Registers are used to store data temporarilyduring the execution of a program.

Different types of registers are:• General purpose Registers• Accumulator• Program Counter (pc)• Stack pointer (sp)• Flag Register

General Purpose Register

• There are six 8 bit general purpose registerlabeled as B, C, D, E, H & L.

• These registers can be used as a single 8 bitregisters or in pairs like BC, DE, and HL.

• These registers are programmable meaningthat a programmer can use them to load ortransfer data from the registers by usinginstructions.

ACCUMULATOR REGISTER

• It is an 8 bit register.• It is a part of ALU.• It is used to store 8-bit data and to perform

arithmetic and logic operations. (Arithmeticoperations such as addition, Subtractionetc, logical operations- and, or, ex-or etc)

• The result of an operation is stored in theaccumulator.

• Accumulator is identified as Register A.

PROGRAM COUNTER (PC)• It is a 16 bit register microprocessor uses

this register for sequencing the execution ofinstructions.

• This register is a memory pointer.• The function of the program counter is to

point to the memory address from whichthe next byte is to be fetched

• When a byte (machine code) is beingfetched the program counter is incrementedby one, to point to the next memorylocation.

STACK POINTER (SP)

• It is a 16 bit register and it is used asa memory pointer.

• It points to a memory location in usermemory called stack.

• The beginning of the stack is definedby loading a 16-bit address in thestack pointer register.

FLAG REGISTER• The ALU has 5 flip flops that are set or reset

according to data conditions in theaccumulator and other registers.

• The microprocessor uses them to test fordata conditions.

• Flag registers are used in the decisionmaking process of the microprocessor.

• It is a single bit register which stores 8 bitregister so that the programmer canexamine these flags for data conditions.

Basically, there are five types of flags: • SIGN FLAG • ZERO FLAG • CARRY FLAG • PARITY FLAG • AUXILLARY FLAG

SIGN FLAG:After the execution of arithmetic or logical operation, if the resultant

operation is minus then the flag is set, if the resultant operation isplus then the flag is reset.

ZERO FLAG:The zero flag is set if the ALU operation results in zero and reset if the

resultant operation is not zero.CARRY FLAG:If the carry is generated from MSB (most significant bit) in a arithmetic

operation then carry flag is set otherwise reset.PARITY FLAG:After the arithmetic and logical operation if the result as even number

of 1‟s then the flag is set, if odd number of 1‟s then the flag is reset.AUXILLARY FLAG:If an arithmetic operation produces carry out from the lower order 4-

bits then the flag is set, otherwise the flag is reset.

Problem on Carry flag:Hexadecimal Addition: AA+7CHexadecimal Addition: 3A+7C

Problem on Zero flag:Hexadecimal Addition: 84+7CHexadecimal Addition: 3A+7C

Problem on Parity flag:Hexadecimal Addition: 3A+78Hexadecimal Addition: 3A+7C

Problem on Auxillary-Carry flag:Hexadecimal Addition: 3A+7C

TIMING AND CONTROL UNIT

• This unit synchronizes all themicroprocessor operations with theclock and generates the controlsignals necessary for communicationbetween the microprocessor andperipherals.

INSTRUCTION REGISTER AND DECODER

• The instruction register and thedecoder are part of the ALU.

• When an instruction register isfetched from memory, it is loaded inthe instruction register.

• The decoder decodes the instructionand establishes the sequence ofevents to follow.

8085 Architecture

The internal logic design of a µP knownas its architecture reveals whatexactly is happening and how differentoperations are executed inside themicro processing unit (MPU).

Salient featuresThe salient features of 8085 µp are:

– It is a 8 bit microprocessor.– It is manufactured with N-MOS technology.– It has 16-bit address bus and hence can address up to 216 =

65536 bytes (64KB) memory locations through A0-A15.– The first 8 lines of address bus and 8 lines of data bus are

multiplexed AD0 – AD7.– Data bus is a group of 8 lines D0 – D7.– It supports external interrupt request.– A 16 bit program counter (PC).– A 16 bit stack pointer (SP).– Six 8-bit general purpose register arranged in pairs: BC, DE, HL.– It requires a signal +5V power supply and operates at 3.2 MHZ

single phase clock.– It is enclosed with 40 pins DIP (Dual in line package).

BATA CAT IISBussesAccumulatorTemp RegisterALU & Flags

CPU RegistersAddr,Data BufferTiming Unit

Instruction Register & DecoderInterrupt ControlSerial Control

Address Buffer and Address/Data Buffer:• These buffers are used to increase the driving

capacity of address/data busses.• In the simplest form these form emitter follower

with large current amplification.Timing and Control Unit:• It includes an on chip oscillator and a control

sequencer.• The control sequencer is micro programmed; it

has a ROM that stores all the micro routinesneeded for executing the instructions.

Pin Descriptions of 8085

The signals of 8085 can be classified into seven groups according to their functions. These are:

• (1) Power supply and frequency signals • (2) Data and Address buses • (3) Control bus• (4) Interrupt signals • (5) Serial I/O signals • (6) DMA signals • (7) Reset signals.

address(8 bits)


address and data(8 bits)

dual - use pins !!


• Pins 1 and 2 (X1, X2 (Input))Crystal or R-C / L-C network

connections to set the internal clock generatorX1 can also be an external clock input

instead of a crystal. The input frequency is divided by 2 to

give the internal operating frequency.

• Pin 3 (RESET OUT (Output)) Indicates CPU is being reset.Can be used as a system RESET. The signal

is synchronized to the processor clock.Q) What is the state of registers when they

are reset?• Pin 4 and 5 (SOD and SID)It consists of a set of SIPO and PISO flip-flops.SID (Input)Serial input data line: RIM instruction

affects this pin.SOD (output)Serial output data line. SIM instruction

affects this pin.

• Pins 6 to 11 (Interrupts) These pins form the interrupt control section. There are 5

hardware interrupt request TRAP, RST 7.5, RST 6.5, RST 5.5and INTR and 1 acknowledgement INTA. These interrupts areserviced on the order of priority. TRAP has got the highestpriority while INTR has least.

• Pins 12 to 19 (AD0-AD7) These pins form the lower order address bus multiplexed with

the data bus to form Address/Data bus AD0-AD7. This bus is bidirectional one.• Pins 21 to 28 (A8-A15) These pins form the higher order address bus. This bus is unidirectional one.• Pins 29 and 33 (S0 & S1) Data Bus Status. Encoded status of the bus cycle:

• Pins 31, 32 and 34 (WR,RD, IO/M) These pins are to write (store), read (load) either from memory or

from I/O device. RD & WR both together cannot be activated. As an example, if IO/M = 0, RD=0 & WR = 1 means it is memory

read operation.• Pin 30 (ALE (Output))Address Latch Enable: This is an important pin which supports

multiplexing of A0-A7 with D0-D7.• Pin 35 (READY) This is another important pin on 8085. It permits the use of cheaper

(slow) peripherals. At first the uP asks the device to get ready. If thedevice is ready, then data transfer takes place and if not, the devicesends back a low on READY pin.

If READY = 0 the processor generates WAIT states till it gets ready,thus enabling the use of slower devices (speed matching).

• Pins 36 and 37 (RESETIN and CLKOUT) A low signal on pin 36 resets the PC, IR etc and sends a reset signal

(RESET OUT) to peripherals through Pin 3. Pin 37 is the system clock. The signal generated by the on-chip

oscillator after passing through divide by 2 flip-flop. Is connected topin 37 which can be used to synchronize all the peripherals with theuP.

Generation of Control Signals

• The figure below shows the generationof active low MEMR and MEMWsignals, along with active low IOR andIOW signals.

• Pins 38 and 39 (HLDA and HOLD)These 2 pins form the DMA (Direct Memory Access)

section. In certain situations, the intervention ofCPU reduces the speed of operation. In order totransfer huge amounts of data, it is wise to bypassCPU. The DMA controller issues a signal HOLD toCPU requesting the uP for DMA. CPUacknowledges back by issuing HLDA and givescontrol of busses to DMA controller. Once DMA iscompleted, uP regains the bus control.

• Pins 20 and 40 Vss Ground Reference. Vcc +5 volt supply.

I/O Device uP/CPU Memory

DMA

HLDA

HOLD

Demultiplexing the address / data bus

16

8

Demultiplexing the bus: AD0-AD7

• The arrangement uses a Latch 74LS373 and ALEsignal from 8085 for the purpose. The bus AD0-AD7 is connected to the input of latch. The ALEsignal is connected to the enable (G) pin of Latchand the o/p control (OC) is connected to Gnd.

• During T1 of every M/C cycle ALE goes high andremains low for the remaining portion of that M/Ccycle. Thus during T1 of each and every M/C cycle,the latch follows its i/p (A0 – A7). However, for thenext of the period the latch will be disabled as ALE(G) remains low. In other words till the next ALE (innext M/C cycle) the previous low order addressremains on latch. The data bus now carries thedata D0-D7.

Memory: basic concepts• Stores large number of bits

– m x n: m words of n bits each– k = Log2(m) address input signals– or m = 2^k words– e.g., 4,096 x 8 memory:

• 32,768 bits• 12 address input signals• 8 input/output data signals

• Memory access– r/w: selects read or write– enable: read or write only when

asserted

m × n memory

…

…

n bits per word

mw

ords

enable2k × n read and write

memory

A0…

r/w

…

Q0Qn-1

Ak-1

memory external view

ROM: “Read-Only” Memory

• Nonvolatile memory• Can be read from but not written to, by a

processor in an embedded system• Traditionally written to, “programmed”,

before inserting to embedded system• Uses

– Store software program for general-purpose processor

• program instructions can be one or more ROM words

– Store constant data needed by system– Implement combinational circuit

2k × n ROM

…

Q0Qn-1

A0

…

enable

Ak-1

External view

Example: 8 x 4 ROM• Horizontal lines = words• Vertical lines = data• Lines connected only at circles• Decoder sets word 2’s line to 1 if

address input is 010• Data lines Q3 and Q1 are set to 1

because there is a “programmed” connection with word 2’s line

• Word 2 is not connected with data lines Q2 and Q0

• Output is 1010

8 × 4 ROM

3×8decoder

Q0Q3

A0

enable

A2

word 0word 1

A1

Q2 Q1

programmable connection wired-OR

word line

data line

word 2

Internal view

Implementing combinational function

• Any combinational circuit of n functions of same k variables can be done with 2^k x n ROM

Truth tableInputs (address) Outputsa b c y z0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 1 01 0 1 1 11 1 0 1 11 1 1 1 1

0 00 10 11 01 01 11 11 1

zy

c

enable

ab

8×2 ROMword 0word 1

word 7

RAM: “Random-access” memory

• Typically volatile memory– bits are not held without power supply

• Read and written to easily by embedded system during execution

• Internal structure more complex than ROM– a word consists of several memory cells,

each storing 1 bit– each input and output data line connects

to each cell in its column– rd/wr connected to every cell– when row is enabled by decoder, each cell

has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read

enable2k × n read and write

memory

A0 …

r/w

…

Q0Qn-1

Ak-1

external view

4×4 RAM

2×4 decoder

Q0Q3

A0

enable

A1

Q2 Q1

Memory cell

I0I3 I2 I1

rd/wr To every cell

internal view

Composing memory• Memory size needed often differs from size of

readily available memories• When available memory is larger, simply ignore

unneeded high-order address bits and higher data lines

• When available memory is smaller, compose several smaller memories into one larger memory– Connect side-by-side to increase width of

words– Connect top to bottom to increase number of

words• added high-order address line selects

smaller memory containing desired word using a decoder

– Combine techniques to increase number and width of words

…

2m × 3n ROM2m × n ROM

A0 …

enable 2m × n ROM

…

2m × n ROM

…

Q3n-1 Q2n-1

…

Q0

…Am

Increase width of words

2m+1 × n ROM2m × n ROM

A0 …

enable

…

2m × n ROM

Am-1

Am1 × 2

decoder

…

…

…

Qn-1 Q0

…

Increase number of words

A

enable

outputs

Increase number and width of

words

INTERFACING EXAMPLES

• Draw the circuit diagram of an 8085 system, having a 4 KBEPROM and two 8 KB RAM ICs. The starting address of theEPROM is 0000H and that of RAM is 8000H. The address ofthe decoder circuits should be clearly shown.

Answer :• EPROM - 4 KB(Address lines required is 12 – A0 to A11 )• RAM-I - 8 KB(Address lines required is 13 – A0 to A12 )• RAM-II - 8 KB(Address lines required is 13 – A0 to A12 )• Mapping of Addresses to Memory Ics

ICs Binary Address Hex Addres sA15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

EPRO M4 KB

00..0

00..0

x x.

. x

x x.

. x

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

01..1

00000001

.

.0FFF

RAM-I8 KB

00..0

11..1

x x.

. x

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

01..1

40004001

.

.5FFF

RAM-II8 KB

11..1

00..0

x x.

. x

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

00..1

01..1

80008001

.

.9FFF

Instruction Formats of 8085• An instruction is a command given to the

uP to perform a specific task or function ona given data.

• An instruction comprises of an operationcode (called ‘opcode’) which specifies thenature of the task to be performed by aninstruction and the address of the data(called ‘operand’), on which the o pcodeoperates. The operand may be 8-bitdata,16-bit data, a register/pair, a memorylocation, 8-bit/16-bit address. Symbolically,an instruction looks like

Based on length 8085 instruction set can be classified into 3 types:

• In 1-byte instruction, the opcode and the operand are in the same byte i.e.,

• Example: ADD B

• A 2-byte instruction looks like this:

• Example: ADI 00H

• While a 3-byte instruction looks like the following:

• Example: LDA 4400H

Functionally, the instructions can be classified into five groups:

• data transfer (copy) group• arithmetic group• logical group• branch group• stack, I/O and machine control group.

Addressing Modes in 8085Each instruction indicates an operation to be

performed on certain data. There arevarious methods to specify the data for theinstructions, known as ‘addressing modes’.

For 8085 microprocessor, there are fiveaddressing modes. These are:

• Direct addressing.• Register addressing.• Register indirect addressing.• Immediate addressing.• Implicit addressing.

Direct Addressing:

• In this mode, the address of theoperand is specified within theinstruction itself.

• Examples of this type are:• LDA 4000H, STA 5513H, etc.• IN/OUT instructions (like IN 08H, OUT

08H, etc.) also falls under thiscategory.

Register Addressing:

• In this mode of addressing, theoperand are in the general purposeregisters.

• Examples are: MOV A, B ; ADD D, etc.

Register Indirect Addressing:

• In this mode, instead of specifying aregister, a register pair is specified toaccommodate the 16-bit address ofthe operand.

• MOV A, M; ADD M are examples ofthis mode of addressing.

Immediate Addressing:

• The operand is specified in theinstruction in this mode. Here, theoperand address is not specified.

• MVI A, 07; ADI 0F are examples ofImmediate Addressing mode.

Implicit Addressing:

• In this mode of addressing, theoperand is fully absent.

• Examples are RAR, RAL, CMA, etc.

How to identify addressing mode?

• Letter ending with I -> Immediate• Letter ending with X -> Indirect• Letter involving M -> May be Indirect

or Register Indirect• Letter involving D -> Direct• Letter involving only Register ->

Register

INSTRUCTION SET:• The 8085 microprocessor instruction set has 74

operation codes that result in 246 instructions.• We should be able to grasp an overview of these

frequently used instruction listed below along withthe following notations.

• M = Memory location • n = 8/16-bit Data• R = 8085 8-bit register (A, B, C, D, E, H, L ) • Rs = Register source (A, B, C, D, E, H, L ) • Rd = Register destination (A, B, C, D, E, H, L ) • Rp = Register pair (BC, DE, HL, SP) • ( ) = Contents of

Data Transfer (copy) Group:• The different types of data transfer operations

possible are cited below:

• The term ‘data transfer’ is a misnomer-actually data is not transferred, but copied from source to destination.

The data transfer instructions move data between registers orbetween memory and registers.

• MOV : Move• MVI : Move Immediate• LDA : Load Acc Directly from Memory• STA : Store Acc Directly in Memory• LHLD : Load H & L Registers Directly from Memory• SHLD : Store H & L Registers Directly in MemoryAn 'X' in the name of a data transfer instruction implies that it

deals with a register pair (16-bits);• LXI : Load Register Pair with Immediate data• LDAX : Load Acc from Address in Register Pair• STAX : Store Acc in Address in Register Pair• XCHG : Exchange H & L with D & E

DATA TRANSFER GROUP

Instruction Operation Flags

MOV Rd, Rs (Rd) <- (Rs) NIL

MOV Rd, M (Rd) <- M[HL] NIL

MOV M, Rs M[HL] <- (Rs) NIL

MVI Rd, n8 (Rd) <- n8 NIL

MVI M, n8 M[HL] <- n8 NIL

LXI Rp, n16 (Rp) <- n16 NIL

LDA addr (A) <- [addr] NIL

STA addr [addr] <- (A) NIL

LHLD addr (L) <- [addr], (H) <- [addr + 1] NIL

SHLD addr [addr] <- (L), [addr + 1] <- (H) NIL

LDAX Rp (A) <- [Rp] NIL

STAX Rp [Rp] <- (A) NIL

XCHG (H) (D), (L) (E) NIL

Arithmetic Group: • The arithmetic instructions add, subtract, increment, or decrement

data in registers or memory. • ADD : Add to Accumulator • ADI : Add Immediate Data to Accumulator • ADC : Add to Accumulator Using Carry Flag • ACI : Add Immediate data to Accumulator Using Carry • SUB : Subtract from Accumulator • SUI : Subtract Immediate Data from Accumulator • SBB : Subtract from Accumulator Using Borrow(CY)Flag • SBI : Subtract Immediate from Accumulator Using

Borrow (Carry) Flag • INR : Increment Specified Byte by One • DCR : Decrement Specified Byte by One • INX : Increment Register Pair by One • DCX : Decrement Register Pair by One • DAD : Double Register Add; Add Content of Register Pair to H & L Register Pair

ADDITIONInstruction Operation Flags

ADD r (A) <- (A) + (r) All

ADD M (A) <- (A) + M[HL] All

ADI n (A) <- (A) + n All

ADC r (A) <- (A) + (r) + CY All

ADC M (A) <- (A) + M[HL] + CY All

ACI n (A) <- (A) + n + CY All

DAA Decimal adjust Acc All

DAD rp (HL) <- (HL) + (rp) CY (Result >16bits)

SUBTRACTIONInstruction Operation Flags

SUB r (A) <- (A) – (r) All

SUB M (A) <- (A) - M[HL] All

SUI n (A) <- (A) – n All

SBB r (A) <- (A) – (r) – CY All

SBB M (A) <- (A) - M[HL] – CY All

SBI n (A) <- (A) - n - CY All

INCREMENT AND DECREMENT


INR r (r) <- (r) + 1 Not CY

INR M M[HL] <- M[HL] + 1 Not CY

DCR r (r) <- (r) - 1 Not CY

DCR M M[HL] <- M[HL] - 1 Not CY

INX rp (rp) <- (rp) + 1 None

DCX rp (rp) <- (rp) – 1 None

• Execution of DAA instruction converts the contentof the accumulator into two BCD values. Thesystem utilises the AC flag for this conversion byfollowing the procedures stated below:

• (a) If the lower order 4-bits (D3 – D0) of theaccumulator is greater than 910 or if the AC flag isset, then this instruction (i.e., DAA) adds 0610 tothe low-order 4-bits.

• (b) If the higher order 4-bits (D7 – D4) of theaccumulator is greater than 910 or if the CY flag isset, then this instruction (i.e., DAA) adds 6010 tothe high-order 4-bits.

DAA Working

Examples follow to explain the above:• (i) Let ACC contains 34BCD. Add 19BCD to this34BCD = 0 0 1 1 0 1 0 019BCD = 0 0 0 1 1 0 0 153BCD = 0 1 0 0 1 1 0 1 = 4D H• Since the lower 4-bits represent D (> 910), hence execution of

DAA adds 0610 to the above4D = 0 1 0 0 1 1 0 106 = 0 0 0 0 0 1 1 0

0 1 0 1 0 0 1 1 = 53BCD• (ii) Let ACC = 99BCD. Add 79BCD to this99BCD = 1 0 0 1 1 0 0 179BCD = 0 1 1 1 1 0 0 1178BCD = 0 0 0 1 0 0 1 0 = 12 H

1 1CY AC

• Here both higher order (0001) and lower order (0010) 4-bitsare less than 910, but both AC and CY flags are set. Thus,DAA instruction execution will add 6610 to the result.

Logical Group:This group performs logical (Boolean) operations on data

in registers and memory and on condition flags.The logical AND, OR, and Exclusive OR instructions

enable you to set specific bits in the accumulator ON orOFF.

• ANA : Logical AND with Accumulator• ANI : Logical AND with Accumulator Using

Immediate Data• ORA : Logical OR with Accumulator• OR : Logical OR with Accumulator Using

Immediate Data• XRA : Exclusive Logical OR with Accumulator• XRI : Exclusive OR Using Immediate Data

ANDING


ANA r (A) <- (A) (r) All

ANA M (A) <- (A) M[HL] All

ANI n (A) <- (A) n All

ORING


ORA r (A) <- (A) (r) All

ORA M (A) <- (A) M[HL] All

ORI n (A) <- (A) n All

XORING


XRA r (A) <- (A) (r) All

XRA M (A) <- (A) M[HL] All

XRI n (A) <- (A) n All

COMPARISON


CMP r Compare A and r All

CMP M Compare A and M[HL] All

CPI n Compare A and n All

CMA A = A’ None

CMC CY = CY’ CY

STC CY = 1 CY

Rules for comparison:If (A) < (Reg/Mem): CY flag is set and Z flag is reset.If (A) = (Reg/Mem): CY flag is reset and Z flag is set.If (A) > (Reg/Mem): CY flag and Z flag is reset

ROTATE


RLC CY = A7, A = A(6-0), A7 CY

RRC CY = A0, A = A0, A(7-1) CY

RAL CY, A = A, CY CY

RAR A, CY = CY, A CY

RLC

RRC

RAL

RAR

Branch Group:The branching instructions alter normal sequential program flow,

either unconditionally or conditionally. The unconditional branchinginstructions are as follows:

• JMP : Jump• CALL : Call• RET : ReturnConditional branching instructions examine the status of one of four

condition flags to determine whether the specified branch is to beexecuted. The conditions that may be specified are as follows:

• NZ : Not Zero (Z = 0)• Z : Zero (Z = 1)• NC : No Carry (C = 0)• C : Carry (C = 1)• PO : Parity Odd (P= 0)• PE : Parity Even (P= 1)• P : Plus (S = 0)• M : Minus (S = 1)

The conditional branching instructions are specified as follows:

Jumps Calls ReturnsJC CC RC (Carry)

JNC CNC RNC (No Carry)JZ CZ RZ (Zero)

JNZ CNZ RNZ (Not Zero)JP CP RP (Plus)JM CM RM (Minus)JPE CPE RPE (Parity Even)JP0 CPO RPO (Parity Odd)

BRANCH GROUP


JMP addr (unconditional) (PC) <- addr Nil

J conditional addr If condition is true(PC) <- addr

Else(PC)<- (PC) +3

Respective flags will be checked

PCHL PC <- (HL) None

Stack Group:The following instructions affect the Stack

and/or Stack Pointer: • PUSH : Push Two bytes of Data onto

the Stack • POP : Pop Two Bytes of Data off the

Stack • XTHL : Exchange Top of Stack with H

& L • SPHL : Move content of H & L to

Stack Pointer

STACK INSTRUCTIONS

Instruction Operation FlagsLXI SP, n16 (SP) <- n16 None

SPHL (SP) <- (HL) None

XTHL ((SP)) <-> (L)((SP+1)) <-> (H)

None

PUSH Rp SP <- SP -1(SP) <- RpHSP <- SP -1(SP) <- RpL

None

PUSH PSW SP <- SP -1(SP) <- FlagReg

SP <- SP -1(SP) <- (A)

None

POP Rp RpL <- (SP)SP <- SP +1RpH <- (SP)SP <- SP +1

None

POP PSW FlagReg <- (SP)SP <- SP +1

A <- (SP)SP <- SP +1

None

Instruction Operation FlagsCALL addr

(uncondotional)= (PUSH PC + JMP addr)

(SP - 1) <- PCH(SP - 1) <- PCLSP <- SP – 2PC <- addr

None

C conditional addr If True:(SP - 1) <- PCH(SP - 1) <- PCLSP <- SP – 2PC <- addr

False:PC <- PC + 3

None

RET (unconditionally)= (POP PC)

PCL <- (SP)PCH <- (SP + 1)

SP <- SP + 2

None

R condition If True :PCL <- (SP)

PCH <- (SP + 1)SP <- SP + 2

False:PC <- PC + 1

None

Fig: Use of CALL-RET in a subroutine

I/0 instructions:

The I/0 instructions are as follows:• IN : Initiate Input Operation• OUT : Initiate Output Operation

Instruction Operation FlagsIN addr(8) A <- (addr) None

OUT addr (addr) <- A None

Machine Control instructions:The Machine Control instructions are as

follows:• EI : Enable Interrupt System• DI : Disable Interrupt System• HLT : Halt• NOP : No Operation


RST n= (CALL)

(SP -1) <- PCH(SP -2) <- PCLSP <- SP -2

PC <- (n * 8) in Hex

None

Interrupts

• An interrupt is considered to be anemergency signal that may be serviced.– The Microprocessor may respond to it as soon as

possible.

• What happens when uP is interrupted ?– When the Microprocessor receives an interrupt

signal, it suspends the currently executingprogram and jumps to an Interrupt ServiceRoutine (ISR) to respond to the incominginterrupt.

– Each interrupt will most probably have its ownISR.

• Interrupt is a process where an external device can get the attention of the microprocessor.– The process starts from the I/O device – The process is asynchronous.

• Classification of Interrupts – Interrupts can be classified into two types:

• Maskable Interrupts (Can be delayed or Rejected)• Non-Maskable Interrupts (Can not be delayed or

Rejected)

– Interrupts can also be classified into:• Vectored (the address of the service routine is hard-

wired)• Non-vectored (the address of the service routine needs

to be supplied externally by the device)

• There are five (5) interrupt pins of 8085—from pin 6 to pin 10.

• They represent– TRAP,– RST 7.5,– RST 6.5,– RST 5.5 and– INTR interrupts respectively.

• These five interrupts are ‘hardware’interrupts.

• An interrupt which can be disabled bysoftware means, is called a maskableinterrupt, and an interrupt which cannotbe masked is an unmaskable interrupt.

• 8085 has eight (8) software interrupts from RST 0to RST 7. The instructions, hex codes and thevector locations are tabulated

• Instruction HEX code addresses• RST 0 0000H• RST 1 0008H• RST 2 0010H• RST 3 0018H• RST 4 0020H• RST 5 0028H• RST 6 0030H• RST 7 0038HThe vector address for a software interrupt is

calculated as follows:Vector address = interrupt number × 8For example, the vector address for RST 5 is

calculated as 5 × 8 = 4010 = 28HTherefore Vector address for RST 5 is 0028H.

Interrupt Vectors and the Vector Table

• An interrupt vector is a pointer to where theISR is stored in memory.

• All interrupts (vectored or otherwise) aremapped onto a memory area called theInterrupt Vector Table (IVT).– The IVT is usually located in memory page 00

(0000H - 00FFH).– The purpose of the IVT is to hold the vectors

that redirect the microprocessor to the rightplace when an interrupt arrives.

SIM Instruction:

Set Interrupt Mask Instruction

Execution of SIM instruction allows copying of the contents of theaccumulator into the interrupt masks.

RIM Instruction:

Read Interrupt Mask Instruction

When RIM instruction is executed in software, the status of SID,pending interrupts and interrupt masks are loaded into the accumulator.

The 8085 Maskable/Vectored Interrupt Process

• The 8085 has 4 Masked/Vectored interrupt inputs.– RST 5.5, RST 6.5, RST 7.5

• They are all maskable.• They are automatically vectored according to the

following table:

– The vectors for these interrupt fall in between the vectorsfor the RST instructions. That’s why they have nameslike RST 5.5 (RST 5 and a half).

Masking RST 5.5, RST 6.5 and RST 7.5

• These three interrupts are masked at two levels:– Through the Interrupt Enable flip flop

and the EI/DI instructions.• The Interrupt Enable flip flop controls the

whole maskable interrupt process.– Through individual mask flip flops that

control the availability of the individual interrupts.• These flip flops control the interrupts

individually.


1. The interrupt process should be enabledusing the EI instruction.

2. The 8085 checks for an interrupt during theexecution of every instruction.

3. If there is an interrupt, and if the interruptis enabled using the interrupt mask, themicroprocessor will complete the executinginstruction, and reset the interrupt flip flop.

4. The microprocessor then executes a callinstruction that sends the execution to theappropriate location in the interrupt vectortable.


5. When the microprocessor executes the callinstruction, it saves the address of the nextinstruction on the stack.

6. The microprocessor jumps to the specificservice routine.

7. The service routine must include theinstruction EI to re-enable the interruptprocess.

8. At the end of the service routine, the RETinstruction returns the execution to wherethe program was interrupted.

Summary of 8085 Interrupts:

Timing Diagrams:

• Timing Diagrams represent the inter-relationship among the 3 major buses i.e.the address bus, the data bus and thecontrol bus when an instruction is beingexecuted.

• The actual significance of timing diagramsare:– To understand the operation of a processor– To formulate the software timings

Instruction Cycle [IC]:

• It is the time taken by the processor tocomplete the execution of aninstruction.

• An IC consists of Fetch Cycle (FC) andan Execute Cycle (EC). Thus IC = FC +EC.

• In 8085, an IC may consists of 1 to 5machine cycles.

Instruction cycle• When a processor executes a program, the

instructions (1 or 2 or 3 bytes in length) areexecuted sequentially by the system. Thetime taken by the processor to complete oneinstruction is called the Instruction Cycle(IC).

• Depending on the type of instruction, ICtime varies.

Machine Cycle [MC]

• It is the time taken by the processor toaccess a peripheral device.

• Each READ or WRITE operationperformed by the CPU with memory oran I/O device is known as a machinecycle.

• In 8085, a MC may consists of 3 to 6T states.

T-state / T-cycle

• It is one sub-division of the operationperformed in one clock period.

• These subdivisions are internal statessynchronized with system clock.

Fetch Cycle Steps:

• Send the address of instruction onaddress bus.[T1]

• Read the instruction (op-code) frommemory.[T2]

• Transfer the instruction to IR insideuP.[T3]

• Decode the instruction and generatethe necessary control signals.[T4]

Fetch Cycle:• The time required to fetch an opcode from a

memory location is called Fetch Cycle.• A typical FC may consist of 3T states. In the first T-

state, the memory address, residing in the PC, issent to the memory. The content of the addressedmemory (i.e., the opcode residing in that memorylocation) is read in the second T-state, while in thethird T-state this opcode is sent via the data bus tothe instruction register (IR).

Execution Cycle Steps:

• Decode the fetched instructions in ID.• Generate the required control signals

necessary for the next operation.• Fetch the operands and execute the

instruction.

• To differentiate between the differentmachine cycles, 8085 issues 3-statuslines: IO/M, S1 and S0.

IO/M S1 S0 MC0 1 1 Opcode Fetch0 1 0 Memory Read0 0 1 Memory Write1 1 0 IO read1 0 1 IO write1 1 1 INT ACK0 1 0 BI0 0 0 HLT

The lower byte of address (AD0 – AD7) is available on the multiplexedaddress/data bus during T1 state of each machine cycle, except duringthe bus idle machine cycle.

Lower byte address on the multiplexed bus

Higher byte address on A8 – A15

The higher byte of address (A8 – A15) is available during T1 to T3 states of each machine cycle, except during the bus idle machine cycle.

Data transfer from memory or I/O device to microprocessor or the reversetakes place during T2 and T3 states of the machine cycles.In the read machine cycle, data appears at the beginning of T3 state,whereas in the write machine cycle, it appears at the beginning of T2.

Appearance of data in the read and write machine cycles

Status signals during opcode fetch and memory read machine cycles:

The status signals are IO/ M, S0 and S1. Their conditions indicate the typeof machine cycle that the system is currently passing through. These threestatus signals remain active right from the beginning till the end of eachmachine cycle.

RD and WR signals during the Read cycle and Write cycle

When RD is active, microprocessor reads data from either memory or I/O device while when WR is active, it writes data into either memory or I/O device.Data transfer (reading/writing) takes place during T2 and T3 states of read cycle or write cycle.

Opcode Fetch machine cycle

• The first machine cycle of every instruction is the OpcodeFetch. This indicates the kind of instruction to be executedby the system. The length of this machine cycle variesbetween 4T to 6T states—it depends on the type ofinstruction. In this, the processor places the contents of thePC on the address lines, identifies the nature of machinecycle (by IO/M, S0, S1) and activates the ALE signal. Allthese occur in T1 state.

• In T2 state, RD signal is activated so that the identifiedmemory location is read from and places the content on thedata bus (D0 – D7).

• In T3, data on the data bus is put into the instructionregister (IR) and also raises the RD signal thereby disablingthe memory.

• In T4, the processor takes the decision, on the basis ofdecoding the IR, whether to enter into T5 and T6 or to enterT1 of the next machine cycle.

• One byte instructions that operate on eight bit data areexecuted in T4.

• Examples are ADD B, MOV C, B, RRC, DCR C, etc.

Memory Read/Write machine cycle

IO Read/Write machine cycle

For Students:

• Workout on Timing Diagrams relatedto BI cycle and INTA cycle.

• Apply all these to your instruction set.• Also apply the T-states to calculate

delay programs in microprocessor.

Peripheral IC’s• 8255: Programmable Peripheral Interface• 8155/8156: Programmable I/O Ports and Timer• 8355/8755: Programmable I/O Ports with

ROM/EPROM• 8279: Programmable Keyboard/Display

Interface• 8259: Priority Interrupt Controller• 8257: Programmable DMA Controller• 8253/8254 : Programmable Interval Timer• 8251 : USART

PPI: 8255

• Features:• 40 pin parallel I/O devices

(programmable).• 3, 8-bit I/O ports : PA, PB, and PC (CU

+ CL)• One control word register into which

control word is written.

Block Diagram

The two address lines, along with CS signal, determine the selection ofa particular port or control register. This is explained below:

Control Word of 8255:

BSR mode stands for Bit Set Reset mode.The characteristics of BSR mode are:• BSR mode is selected only when D7 = 0 of the Control Word Register

(CWR).• Concerned with bits of port C.• Individual bits of Port C can either be Set or Reset.• At a time, only a single bit of port C can be Set or Reset.• Is used for control or on/off switch.• BSR control word doesn’t affect ports A and B functioning.

BSR Mode I/O Mode

0 1

CW Register in BSR Mode

Problem1

• Write a BSR control word to set bitsPC7 and PC0 and to reset them after 1second delay.

Solution 1• Subroutine Program:BSR: MVIA, 0FH; (Accumulator loaded with 0FH to set PC7 bit of Port

C)OUT 83H; (This sets PC7 bit of Port C)MVIA, 01H; (Accumulator loaded with 01H to set PC0 bit of Port

C)OUT 83H; (This sets PC0 bit of Port C)CALL DELAY; (Assume the DELAY is for 1 second)MVIA, 00H; (Accumulator loaded with 00H to reset PC0 bit of

Port C)OUT 83H; (This resets PC0 bit of Port C)MVIA, 0EH; (Accumulator loaded with 0EH to reset PC7 bit of

Port C)OUT 83H; (This resets PC7 bit of Port C)RET;

I/O Mode

CW Register in I/O Mode

Mode 0:• This is a basic or simple input/output mode,

whose features are:• Outputs are latched.• Inputs are not latched.• All ports (A, B, CU, CL) can be programmed in either

input or output mode.• Ports don’t have handshake or interrupt capability.• Sixteen possible input/output configurations are

possible.

Problem 2• 1. Identify port addresses in following figure.• 2. Identify Mode 0 control word to configure port A & CU as

input ports & port B & CL as output ports.• 3. Write a program to read DIP switches & display the reading

from port B at port A & from CL to port CU.

Solution 2MVI A, 83H ; LOAD ACC with control word.OUT 83H ; Write word in control register to initialize the portsIN 81H ; Read switches at port BOUT 80H : display the reading at port AIN 82H ; Read switches at port CANI 0FH ; Mask the upper 4 bits of port C, these bits are not inputdataRLC ; rotate & place data in the upper half of ACCRLC ;RLC ;RLC ;OUT 82H ; display data at port CU.HLT

Mode 1:• In this mode, input or outputting of data is carried out by

taking the help of handshaking signals, also known asstrobe signals. The basic features of this mode are:

• Ports A and B can function as 8-bit I/O ports, taking the helpof pins of Port C.

• I/Ps and O/Ps are latched.• Interrupt logic is supported.• Handshake signals are exchanged between CPU and

peripheral prior to data transfer.• In this mode, Port C is called status port.• There are two groups in this mode—group A and group B.

They can be configured separately. Each group consists of an8-bit port and a 4-bit port. This 4-bit port is used forhandshaking in each group.

Thank You

Documents

Microprocessor based System Design_1_Lec