Microprocessor 8086 Architecture

8086/8088 Microprocessor

Introduction to the processor and its pin configuration

Topics

• Basic Features

• Pinout Diagram

• Minimum and Maximum modes

• Description of the pins

Basic Features

• 8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus

• 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus

• Both manufactured using High-performance

Metal Oxide Semiconductor (HMOS) technology

• Both contain about 29000 transistors• Both are packaged in 40 pin dual-in-line

package (DIP)

8086/8088 Pinout Diagrams

GNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGND

VCCAD15A16/S3A17/S4A18/S5A19/S6

HOLDHLDA

ALE

READYRESET

BHE/S7MN/MXRD

WRM/IODT/RDEN

INTATEST

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GNDA14A13A12A11A10 A9 A8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGND

VCCA15A16/S3A17/S4A18/S5A19/S6

HOLDHLDA

ALE

READYRESET

SS0MN/MXRD

WRIO/MDT/RDEN

INTATEST

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BHE has no meaning on the 8088 and has been eliminated

Multiplex of Data and Address Lines in 8088

• Address lines A0-A7 and Data lines D0-D7 are multiplexed in 8088. These lines are labelled as AD0-AD7. – By multiplexed we mean

that the same pysical pin carries an address bit at one time and the data bit another time

GNDA14A13A12A11A10 A9 A8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGND

VCCA15A16/S3A17/S4A18/S5A19/S6

HOLDHLDA

ALE

READYRESET

SS0MN/MXRD

WRIO/MDT/RDEN

INTATEST

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Multiplex of Data and Address Lines in 8086

• Address lines A0-A15 and Data lines D0-D15 are multiplexed in 8086. These lines are labelled as AD0-AD15.



HOLDHLDA

ALE

READYRESET

BHE/S7MN/MXRD

WRM/IODT/RDEN

INTATEST

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Minimum-mode and Maximum-mode Systems

• 8088 and 8086 microprocessors can be configured to work in either of the two modes: the minimum mode and the maximum mode

Minimum mode: Pull MN/MX to logic 1 Typically smaller systems and contains a

single microprocessor Cheaper since all control signals for

memory and I/O are generated by the microprocessor.

Maximum mode Pull MN/MX logic 0 Larger systems with more than one

processor (designed to be used when a coprocessor (8087) exists in the system)



HOLDHLDA

ALE

READYRESET

BHE/S7MN/MXRD

WRM/IODT/RDEN

INTATEST

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Lost Signals in Max Mode

Minimum-mode and Maximum-mode Signals



RQ/GT0RQ/GT1

QS0

READYRESET

BHE/S7MN/MXRD

LOCKS2S1S0

QS1TEST

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Max Mode



HOLDHLDA

ALE

READYRESET

BHE/S7MN/MXRD

WRM/IODT/RDEN

INTATEST

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Min Mode

Vcc GND

808

6 C

PU

F/CAEN1AEN2

Clockgenerator

+5V

RES

Wait-StateGenerator

CLKREADYRESET

M/IOINTA

RDWR

PCLK

MN/MX +5V

STB

OE

8282Latch

ALE

AD0-AD 15A16-A19

BHE BHE

D0 - D15

8286

DT/RDEN

TOE

16

A0 - A19

Address Bus

ControlBus

8086 System Minimum mode

8086

CP

U

Clockgenerator

Wait-StateGenerator

CLK

READY

RESET

MN/MX

AD0-AD 15A16-A19 BHE

STB

OE

8282Latch

A0 - A19

Address Bus

+5V

RESS0

S1

S2

CLKS0

S1

S2

DATA

8286Transceiver

T

OE

ALE

Gnd

DEN

DT/R

MRDC

MWTC

IORC

IOW C

AIOW C

AMWC

INTA

8288

Bus

Con

trol

ler

8086 System Maximum Mode

Description of the Pins



RQ/GT0RQ/GT1

QS0

READYRESET

BHE/S7MN/MXRD

LOCKS2S1S0

QS1TEST

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Max Mode



HOLDHLDA

ALE

READYRESET

BHE/S7MN/MXRD

WRM/IODT/RDEN

INTATEST

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Min Mode

Vcc GND

CPU component Contents

Flags Cleared

Instruction Pointer 0000H

CS FFFFH

DS, SS and ES 0000H

Queue Empty

RESET Operation results

AD0 – AD15 Address

Data

AD0 - AD15: Address Data Bus

A17/S4 A16/S3 Function

0

0 Extra segment access

0

1 Stack segment access

1

0 Code segment access

1 1 Data segment access

A17/S4, A16/S3 Address/Status

A18/S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is indicated through this pin

A19/S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus.

A19/S6, A18/S5 Address/Status

S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive State

S0, S1 and S2 Signals

QS1 QS1 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

QS1 and QS2 Signals

IO/M DT/R SSO CHARACTERISTICS

0 0 0 Code Access

0 0 1 Read Memory

0 1 0 Write Memory

0 1 1 Passive

1 0 0 Interrupt Acknowledge

1 0 1 Read I/O port

1 1 0 Write I/O port

1 1 1 Halt

Read Write Control Signals

Data can be accessed from the memory in four different ways:

• 8 - bit data from Lower (Even) address Bank.

• 8 - bit data from Higher (Odd) address Bank.

• 16 - bit data starting from Even Address.

• 16 - bit data starting from Odd Address.

8086 Memory Addressing

HigherAddress

Bank(512K x 8)

ODD

LowerAddress

Bank(512K x 8)

EVEN

A1-A19Address Bus

Data Bus (D0 - D15)

D8-D15 D0-D7

BHE A0

Treating Even and Odd Addresses

A1-A19

D0-D15

BHE = 1D8-D15 D0-D7

A0 = 0

x

x + 2

x + 4

x + 1

x + 3

x + 5

Odd Bank Even Bank

8-bit data from Even address Bank

MOV SI,4000HMOV AL,[SI]

A1-A19

D0-D15

BHE =0 A0 = 1

x

x + 2x + 1x + 3

Odd Bank Even Bank

D 8 -D 1 5D 0 -D 7

8-bit Data from Odd Address Bank

MOV SI,4001HMOV AL,[SI]

A1-A19

D0-D15

BHE =0A0 = 0

x

x + 2x + 1x + 3

Odd Bank Even Bank

D8-D15

D0-D7

16-bit Data Access starting from Even Address

MOV SI,4000HMOV AX,[SI]

A1-A19

Odd Bank Even Bank

D8-D15D0-D7

A1-A9

0005

00070009

000400060008

A1-A19

Odd Bank Even Bank

D8-D15D0-D7

A1-A9

0005

00070009

000400060008

(a) F irst Access from Odd Address (b) Next Access from Even Address

16-bit Data Access starting from Odd Address

MOV SI,4001HMOV AX,[SI]

T1 T2 T3 Twait T4

CLK

AD0-AD15

BHE

ALE

S2 S0-

M /IO

RD

REA DY

DT/R

DEN

W R

Read Timing Diagram

Write Machine Cycle

• INTR is used to request a hardware interrupt.• It is recognized by the processor only when IF =

1, otherwise it is ignored (STI instruction sets this flag bit).

• The request on this line can be disabled (or masked) by making IF = 0 (use instruction CLI)

• If INTR becomes high and IF = 1, the 8086 enters an interrupt acknowledge cycle (INTA becomes active) after the current instruction has completed execution.

INTR (input)Hardware Interrupt Request Pin

• If I/O peripheral wants to interrupt the processor, the “interrupt controller” will send high pulse to the 8086 INTR pin.

• What about if a simple system to be built and hardware interrupts are not needed;

What to do with INTR and INTA?

For Discussion

• The Non Maskable Interrupt input is similar to INTR except that the NMI interrupt does not check to see if the IF flag bit is at logic 1.

• This interrupt cannot be masked (or disabled) and no acknowledgment is required.

• It should be reserved for “catastrophic” events such as power failure or memory errors.

NMI (input) Non-Maskable Interrupt line

8086 External Interrupt Connections

NMI - Non-Maskable Interrupt INTR - Interrupt Request

Interrupt Logic

int intoDivideError

SingleStep

NMI Requesting Device

8086 CPUIntel

8259A

PIC

NMI

INTR

Software Traps

Programmable Interrupt Controller

(part of chipset)

• The TEST pin is an input that is tested by the WAIT instruction.

• If TEST is at logic 0, the WAIT instruction functions as a NOP.

• If TEST is at logic 1, then the WAIT instruction causes the 8086 to idle, until TEST input becomes a logic 0.

• This pin is normally driven by the 8087 co-processor (numeric coprocessor) .

• This prevents the CPU from accessing a memory result before the NDP has finished its calculation

TEST (input)

• This input is used to insert wait states into processor Bus Cycle.

• If the READY pin is placed at a logic 0 level, the microprocessor enters into wait states and remains idle.

• If the READY pin is placed at a logic 1 level, it has no effect on the operation of the processor.

• It is sampled at the end of the T2 clock pulse

• Usually driven by a slow memory device

Ready (input)

CLK

Ready

Reset

+ 5 VR

C

RES

X1

X2

F/C

RDY1RDY2

8284

AEN1AEN2

RESET KEY

8086

Mic

ropr

oces

sor

8284 Connected to 8086 Mp

• The HOLD input is used by DMA controller to request a Direct Memory Access (DMA) operation.

• If the HOLD signal is at logic 1, the microprocessor places its address, data and control bus at the high impedance state.

• If the HOLD pin is at logic 0, the microprocessor works normally.

HOLD (input)

• Hold acknowledge is made high to indicate to the DMA controller that the processor has entered hold state and it can take control over the system bus for DMA operation.

HLDA (output)Hold Acknowledge Output

DMA Operation

Documents

Microprocessor 8086 Architecture