Microelectronics & VLSI at IIT Bombay: Academic Programmes J. Vasi Department of Electrical Engineering Indian Institute of Technology, Bombay 2002

Microelectronics & VLSI at IIT Bombay:

Academic Programmes

J. VasiDepartment of Electrical Engineering

Indian Institute of Technology, Bombay

2002

Overview• The Microelectronics Program is a part of EE

Department at IIT Bombay• Microelectronics includes VLSI Design• Links with the CS&E and ME&MS Departments• Started in 1986; one of the oldest programs in the

country • Main thrust in silicon CMOS design, VLSI CAD, CMOS

technology and devices, MEMS• Group consists of 12 core faculty in EE Department,

plus several others in related Departments

Faculty

• P. R. Apte• A. N. Chandorkar• M. P. Desai• S. Duttagupta• R. Lal• S. Mahapatra• K. V. V. Murthy

• H. Narayanan • R. Parekhji

(adjunct) • M. B. Patil• V. Ramgopal

Rao• D. K. Sharma• J. Vasi

Associated Faculty• A. Karandikar Elec. Engg.• D. Manjunath Elec. Engg.• S. S. S. P. Rao Comp. Sci. & Engg.• S. Chakrabarty Comp. Sci. & Engg.• M. Sohoni Comp. Sci. & Engg.• S. Patkar Maths• R. O. Dusane Met. Eng. & Mat. Sci.• R. Srinivasa Met. Eng. & Mat. Sci.• A. Contractor Chemistry

Teaching Programs

• Ph.D. (graduating ~ 3-4 / year)• M.Tech. with specialization in

Microelectronics (~ 35 / year)• Dual Degree with specialization in

Microelectronics (~ 18 / year)• B.Tech. (~ 55 / year, ~ 15 / year

with projects in Micro-electronics)

Highlights of the Ph.D. Program

• About 15 Ph.D. students at any time• Institute scholarship, industry

fellowship or sponsored project assistantship

• Typical duration 3 – 5 years• Industry fellowships from Intel,

Siemens, GE• Most full-time, some part-time

Intel Sponsored Ph.D. Students

• Nihar Mohapatra: “Device and Circuit Performance Trade-offs with the Use of High-K Dielectrics in Sub-100 nm CMOS Technologies”

• D. Vinay Kumar: “Gate Oxide thickness Scaling in Sub-100 nm MOSFETS and its Effect on Circuit Performance”

• K. Narasimhulu + 1 student: “Impact of Device Scaling on Mixed-Signal CMOS Circuits”

Intel Sponsored Ph.D. Students Publications

(2001-2003)1. D. Vinay Kumar, N. Mohapatra, V. R. Rao, and M. B. Patil,

"Application of the look-up table approach to high-K MOS transistor circuits," submitted to IEEE VLSI Design Conference, 2003.

2. D. Vinay Kumar, R. A. Thakker, M. B. Patil, and V. R. Rao, "Simulation study of non quasi static behaviour of MOS transistors," Proc. 5th International Conference on Modeling and Simulation of Microsystems, San Juan, Puerto Rico, April 22, 2002.

3. D. Vinay Kumar, M. B. Patil, N. R. Mohapatra, V. R. Rao, B. Anand, and M. P. Desai, "A new look-up table circuit simulator," Proc. Chandigarh Symp. on Microelectronics, Panjab University, February, 2001.

4. Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao “Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics” Microelectronics Reliability, Vol. 41, p.1045-1048, 2001

5. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra, V. Ramgopal Rao, "The Effect of High-K Gate Dielectrics on Deep Sub-micrometer CMOS Device and Circuit Performance", IEEE Transactions on Electron Devices, p. 826-831, Vol. 5, 2002.


(2001-2003)6. Nihar.R.Mohapatra, A.Dutta, M.P.Desai and V. Ramgopal Rao,

“Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics” Proceedings of the 4th International Conference on VLSI Design, January 2001, Bangalore, India

7. Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao “Sub 100 nm MOS Circuit Performance with High-K Gate Dielectrics” Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 13-15, 2000, Munich, Germany

8. N.Mahapatra, M.P.Desai, and V.Ramgopal Rao, “Device and Circuit Performance Issues with High-K Gate Dielectrics”, Proceedings of the National seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec 2000.

9. Nihar. R. Mohapatra, M. P. Desai, Narendra Siva, V. Ramgopal Rao, “The Impact of High-K Gate Dielectrics on Sub 100nm CMOS Circuit Performance”, Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.


(2001-2003)10. Nihar Mohapatra, Souvik Mahapatra, V.Ramgopal Rao, “"Study

of Degradation in Channel Initiated Secondary Electron Injection Regime", Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.

11. Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “A Comparative Study of Degradation for NMOSFET's in CHE and CHISEL Injection Regime”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

12. Nihar. R. Mohapatra, M. P. Desai, V. Ramgopal Rao, “Effect of Technology Scaling on MOS Transistors with High-K Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

13. Krishna K. Bhuwalka, Nihar. R. Mohapatra, Siva G.Narendra, V. Ramgopal Rao, “Effective dielectric thickness Scaling for High-K Gate Dielectric MOSFETs”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)


(2001-2003)14. Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal

Rao, “Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

15. N.R Mohapatra, S. Mahapatra and V. Ramgopal Rao, “Bias and Time Dependene of Damage Generation in n-Channel MOS Transistors Operating in the Substrate Enhanced Gate Current Regime” 9th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Some Recent and Ongoing Ph. D. Theses

• S. Vaidya: Neutron radiation effects in MOS systems• J. Meckie: Asynchronous design issues• G. Trivedi: Parallel algorithms for VLSI optimization• N. Mahapatra: High-k dielectrics for 100 nm CMOS• A. Shastry: Microcapillary electrophoresis on silicon• C.A. Betty: Capacitive immunosensor on porous Si• B. Anand: Digital design with dynamic threshold

CMOS• D. Nair: Flash memory design and reliability• D.V.Kumar: Look-up table approach for CMOS circuits

Highlights of the M.Tech. Program

• 2 year program with specialization “Microelectronics”

• Emphasis on both Devices and VLSI Design

• Attracts the top students in the country (GATE percentile > 99%)

• 35 students admitted every year, including 20 TCS scholars

• 18-month-long M.Tech. project• Placement in Indian and international

semiconductor and design companies

Structure of the M.Tech. Microelectronics Program

Semester I

• Physical Electronics• VLSI Technology• VLSI Design• VLSI Design Lab• M.Tech. Seminar• Elective I (one of the

following)1. Foundations of VLSI CAD2. Hardware Description languages3. DSP and Applications

Semester II

• Microelectronics Lab • M.Tech. Project: Stage I

• Electives II, III, IV (3 out of the following)

1. System Design2. Physics of Transistors3. Analog CMOS design4. MEMS Technology and

design5. Embedded Systems6. Hardware test and

verification7. Simulation of circuits and

devices

Structure of the M.Tech. Microelectronics Program

Semester III

• M.Tech. Project : Stage II• Elective V (one out of the

following)1. Foundations of VLSI CAD2. Hardware description

Languages3. DSP and Applications

4. Special topics in Microelectronics

5. RF chip design6. Elective from other

departments

Semester IV

• M. Tech. Project : Stage III

Projects of Graduating Students (2002) - 1

1. Modeling and Simulation of LAC MOSFETS.2. Design and Implementation of Modulator for G.S.M.

Applications on Reconfigurable Hardware3. Study of CMOS Gate Delays4. Simulation of Switched Capacitor Circuits Using SEQUEL5. Design and Behavioral Modeling of CMOS Opamps6. Electromagnetic Field Solver Using Parallel FDTD7. Design of RF Tuner for Cable Modem Application.8. Modeling Gate Leakage Current in VLSI MOSFETS9. Electro-Magnetic Field Solver Using Parallel FDTD10.Ultra-Thin Dielectric Degradation in High Field AC and DC

Fowler Nordheim Stress11.Electro-Magnetic Field Solver Using Parallel FDTDMethod12.Design of Analog Phase Lock Loop


13.Hot Carrier Effects in MOS Transistors14.Radiation Hard Digital Circuit Design15.Radiation Hardening of MOS Devices16.Radiation Hard CMOS Analog Design17.Design of a High Speed Sigma-Delta Analog to Digital

Converter18.Design of a Real-Time FFT Generation IC19.High-K Gate Dielectrics for Sub-100nm CMOS20.Power Analysis and Design of Low Power Multiplier21.Advanced Techniques for Nanolithography22.Reduced-Order Modeling of RC Multiport Networks

using Pade Via Lanczos Algorithm23.Parallelization of Circuits Simulation24.Finite State Machine Realization through Decomposition


25.Linearisation of RF Power Amplifier using Envelope Elimination and Restoration Technique

26.Design of Analog Phase Lock Loop27.Design of SDRAM for Embeded Applications28.Jitter Analysis and Macro Modeling of PLL29.Design and Behavioral Macromodeling of Analog Circuits30.The Co-Design Problem: Cost Estimation, Transformation

and Partitioning of CDFG’s31.VHDL Level Partitioning Tool for Hardware Emulator32.Asynchronous VLSI Design from Synchronous

Specification33.Analysis and Design of SOI-DTMOS Circuits34.Design of Microcontroller Peripherals35.Studies of Boundary Conditions in an FDTD

Electromagnetic Field Solver

Highlights of the Dual Degree (DD) Program

• 5 year program with specialization “Microelectronics”• Students receive both B.Tech. and M.Tech. degrees at

the end of 5 years• Entry through JEE, 3rd most popular branch at IIT

Bombay after B.Tech. (CS&E) and B.Tech. (EE)• Emphasis on both Devices and VLSI Design• 15 students admitted every year• Highlight is emphasis on independent study with 18-

month-long DD project• Placement in Indian and international semiconductor

and design companies as well as for Ph.D.• First DD batch admitted in 1996 – 7th batch admitted in

2002

Structure of the Dual Degree Program

• I year and II year semesters are identical to the B.Tech. (EE) programme

• From III year onwards, M.Tech. level courses are introduced

• Many “independent-study” courses like DD Project, DD Seminar, Miniproject, Lab Techniques, Research Seminar, etc.

• DD Project starts in 8th semester, and continues through the 10th semester (18 months), including 2 summer sesions

Projects of the Graduating DD Students

(2002) -11. Simulation of Latch-up in CMOS Technology2. Dual-Band Receiver Design for Wireless Systems3. FSM Realization through Decomposition4. Electromagnetic Field Solver using Parallel FDTD5. Simulation, Fabrication and Characterization of a Novel Sub-

50nm P-MOSFET6. A Dual Loop Synthesizer for GSM Applications7. Design of Analog Viterbi Decoder8. Asynchronous Circuit Design: Towards Eliminating the Global

Clock in VLSI Circuits

Projects of the Graduating DD Students

(2002) - 29. Mathematical Modeling and Simulation of DNA and other

Polyelectrolytes in free Solution Capillary Electrophoresis10. Reconfigurable Finite State Machine Design for Packet

Router11. CMOS Circuit Design for Sub-1 V Technology using DTMOS12. Decompostion Based Approaches for Synthesis of

Asynchronous Circuits from Signal Transition Graphs13. Theoretical Study of a Quantum Point Contact Model14. Novel Approach Towards DNA Based Molecular Electronics &

Towards Four-Probe I-V Measurements of DNA15. Image: A Scalable, Flexible and High-performance Emulation

System

Areas of R & D and Student Projects

• VLSI modeling and simulation• VLSI design (digital, analog, mixed-

mode)• VLSI CAD tool development• Interaction between VLSI technology

and design• Silicon CMOS physics and technology• MEMS

Facilities

• Class 1000 Clean Room• Excellent characterization facility• SEM; photoluminescence• VLSI design workstations• Simulation workstations• Intel Microelectronics Lab• TCS VLSI Design Lab• Wadhwani Electronics Laboratory

Facilities: Clean Room

Facilities: Photolithography

Facilities: SEM

Facilities: Characterization

Facilities: Intel Lab

Facilities: Intel Lab

Facilities: TCS Lab

Facilities: Wadhwani Electronics Lab

Facilities: Wadhwani Electronics Lab

Industry Collaborations

• Industry sponsorship of Ph.D., M.Tech. and DD students: TCS, Intel, TII, Sasken, Analog, Cypress, Siemens, GE, IME, etc.

• Research Projects with Indian industry: BEL, ITI, Sasken, TII, Cypress, ControlNet, etc

• Research Projects with international industry: Intel, Motorola, GE, Siemens, National, IME, Agere

University Collaborations

• Collaborations with other IITs, Universities of Bombay, Pune

• Collaborations with International universities like– UCLA, UCSB, Yale University (USA)– Hong Kong University of Science & Tech.

(HK)– Delft University (The Netherlands)– University of Bundeswehr (Germany)– Griffith University (Australia)– NTU, NUS (Singapore)

Conclusions

• Most active Microelectronics & VLSI group in India

• Major teaching programs at all levels • 110 – 120 graduate students resident in

Microelectronics and VLSI group at any time

• 35 M.Tech, 18 DD and 3 Ph.D. students graduating every year

• Excellent teaching & research facilities• Student project sponsorships from Indian

& international industry

Contacts• Microelectronics Group

Department of Electrical EngineeringIndian Institute of Technology, BombayPowaiMumbai 400076 India

• Phone: +91-22-572-3655• Fax: +91-22-572-3480• email: [email protected]• website: www.iitb.ac.in/~microel/

Documents

Microelectronics & VLSI at IIT Bombay: Academic Programmes J. Vasi Department of Electrical Engineering Indian Institute of Technology, Bombay 2002