THIT K MICROBLAZE TRN SPARTAN 3E STARTER BOARD1. Gii thiu Microblaze l li x l mm 32-bit RISC (32-bit RISC soft-core synthesizable processor) cho php cc nh pht trin cc h thng nhng iu chnh hiu nng p ng cc yu cu ca cc ng dng mc tiu. Kin trc c bn ca Microblaze gm c 32 thanh ghi chung (generalpurpose registers), mt n v logic-s hc (ALU), 1 n v dch (shift unit), v 2 cp ngt (2 levels of interrupt). Ta c th cu hnh thit k c bn ny vi nhiu c tnh cao cp hn cho php ngi s dng cn bng hiu nng yu cu ca ng dng i vi chi ph ca vng logic ca b x l mm Microblaze. Trong th nghim ny, ta s s dng h thng Microblaze v phn mm iu khin hin th LCD trong Spartan 3E FPGA. Trong phn u ta s xy dng mt h thng Microblaze s dng Xilinx Embedded Development Kit (EDK). Ni chung, thit k mt h thng nhng, ta cn: cc phn cng, bn b nh, v ng dng phn mm (Hardware components, Memory map, and Software application).

Hnh 1: H thng Microblaze

Hnh 2: Processor IP Xilinx EDK cho php nh thit k xy dng mt h thng x l hon chnh trn cc FPGA ca Xilinx. Cc h thng c th c to ra nh s dng EDK c th l t mt kin trc x l n gin n mt h thng a x l phc tp vi nhiu mc tng tc phn cng. EDK h tr ch yu cho 2 loi x l: i) Microblaze l b x l li mm c th cu hnh li c v ii) Power-PC l b x l cng c thc hin trn mt s FPGA ca Xilinx. Ph thuc vo chip FPGA m ta s dng, nhiu Microblazes v Power-PCs c th c tch hp vo vi nhau trong mt thit k. EDK cung cp cc trnh bin dch C/C++ cho c Microblaze v Power-PC cng vi mt s cng c debugging/profiling cc ng dng chy trn tng b x l. Bn cnh , s dng ISE, ta c th thc hin mt s loi m phng (simulation) kin trc. Ni dung ny trnh din qu trnh to v kim tra thit k h thng Microblaze nh s dng EDK v Spartan 3E starter board ca Xilinx. Xc nh thit k phn mm Ti (downloading) thit k

2. Cc yu cu ca h thng Ta cn phi ci t cc phn mm sau y trn PC ca mnh thc hin thit k: Windows 2000 SP2/Windows XP/Windows 7 EDK 10.1i, hoc phin bn cao hn (11.x, 12.x, 13.x). Xilinx ISE Design Suite 10.1i, hoc phin bn cao hn (11.x, 12.x, 13.x). Spartan 3E starter kit v Xilinx USB download cable Ghi ch: cc phn cng khc ca Xilinx c th s dng c vi hng dn ny. Nhng thit k hon chnh ch c so snh trn bng nu trn (Spartan 3E). Cc thay i ca thit k cn phi c nu s dng phn cng khc:

Cp nht pin assignments trong tp system.ucf. Cp nht JTAG chain ca bng xc nh trong download.cmd.

3. M t h thng Microblaze Ni chung, thit k mt h thng nhng, ta cn: Cc phn cng (Hardware components). Bn b nh (Memory map). ng dng phn mm (Software application). 4. Phn cng ca thit k Thit k MicroBlaze bao gm cc phn cng nh sau: MicroBlaze Local Memory Bus (LMB) LMB BRAM controllers for BRAM BRAM PLB_MDM Multi-Port Memory Controller (MPMC) for external DDR_SDRAM memory UART for serial communication GPIOs for LEDs 5. Cc bc thit k Thit k gm 3 bc: 1. To mt Project nh s dng Base System Builder (BSB) ca XPS. 2. Phn tch Project c to ra. 3. Kim tra phn cng ca thit k. 5.1. Bc 1: To mt Project nh s dng Base System Builder ca XPS S dng Spartan 3E starter board. Tt c cc thit b trong h thng MicroBlaze c sp xp theo b nh. Nu h thng ch c mt processor, cc a ch b nh cho cc thit b c th c t ng to ra. xparameter.h file c to ra vi macros ch n cc a ch ca cc thit b. S dng macros trong phm mm ng dng sao cho ta khng cn phi thay i tt c cc a ch trong ng dng ngay c khi thay i cc a ch cc thit b. u tin, s dng Xilinx Platform Studio (XPS) to Project File. XPS cho php iu khin s pht trin phn cng v phn mm ca h thng Microblaze, v bao gm: Editor v Project management interface to v bin son m ngun. Cc la chn cu hnh lung cng c phn mm. Ta c th s dng XPS to cc file sau y: (i) Project Navigator project file cho php iu khin lung thc hin ca phn cng. (ii) Microprocessor Hardware Specification (MHS) file. (iii) Microprocessor Software Specification (MSS) file.

Ghi ch: thm thng tin v cc file MHS v MSS c th tham kho Platform Specification Format Reference Manual. XPS h tr lung cng c phn mm lin kt vi cc ng dng. Ngoi ra, ta c th s dujng XPS t cc th vin, cc drivers, interrupt handlers, dch cc chng trnh bin son. Starting XPS: i) M XPS, chn: Start -> All programs -> Xilinx ISE Design Suite 11.1 -> EDK -> Xilinx Platform Studio (hoc kch chut vo biu tng XPS trn Desktop) c ca s Xilinx Platform Studio (hnh 3).

Hnh 3

ii)

Kch chut ln nt OK, s hin th ca s cho hnh 4.

Hnh 4

iii)

Kch chut nt Browse (hnh 4) chn th mc mong mun to tp tin system.xmp v lu (save). Kt qu hin th ca s cho hnh 5.

Hnh 5

iv)

Kch chut nt OK, xut hin ca s cho hnh 6.

Hnh 6

v)

Chn I would like to create a new design option v kch chut nt Next, hin ca s hnh 7.

Hnh 7: Board Selection Ta chn: Board Vendor: Xilinx Board Name: Spartan-3E Starter board Board Revision: D (xem ghi trn bng Spartan-3E)

vi)

Kch chut nt Next s xut hin ca s System Configuration hnh 7. Chn Single-Processor System v kch chut nt Next xut hin ca s Processor Configuration hnh 8.

Hnh 8: Ca s System Configuration v chn Single-Processor System vii) Trn ca s Processor Configuration , ta chn: Reference Clock Frequency: 50 MHz y l ngun ng h bn ngoi trn bng Spartan-3E ang s dng. ng h ny s c s dng to b x l v cc ng h ca bus. Processor type: MicroBlaze System Clock Frequency-bus Clock Frequency: 50 MHz Local Memorry: 8KB

Debug Interface: On-Chip H/W debug module

Hnh 9: Ca s Processor Configuration viii) Kch chut nt Next sau khi la chn cu hnh cho processor (khng cho php x l du phy ng: Enable Floating Point Unit khng chn). Xut hin ca s Peripheral Configuration (chn cu hnh cho Peripherali) hnh 9. Ta ln lt chn: RS232-DCE: XPS UARTLITE, 115000 baud rate, 8 Data bits, no interrupt, no parity (hnh 9) LEDs_8Bit: XPS GPIO. No interrupt (hnh 10) DDR_SDRAM: MPMC Controller (Multi-Port Memory Controller) (hnh 11)

V thi im ny ta c th kch chut nt Add b xung thm IO Peripherals v internal peripherals, nhng ta s xem mt phng php khc phn sau c th b xung thm peripherals cho project.

Hnh 8: Ca s Peripheral Configuration

Hnh 9: Cu hnh cho RS232_DCE

Hnh 10: Cu hnh cho LEDs_8Bit

ix)

Hnh 11: Cu hnh cho DDR_SDRAM Kch chut nt Next hin th ca s Cache Configuration (hnh 12)

Hnh 12: Ca s Cache Configuration x) Trn ca s Cache Configuration khng c g c chn (khng s dng cache). Ta kch chut nt Next hin th ca s Application Configuration (hnh 13). Kim tra cc thng s va cu hnh trn ca s ny, v kch chut nt Next ca s Summary (hnh 14).

Hnh 13: Ca s Application Configuration

Hnh 14: Ca s Summary xi) Kch chut nt Finish trn ca s Summary xut hin ca s Xilinx Platform Studio H:\FPGAExamples\EDK\system.xmp (System Assembly View) (hnh 15). N ch ra peripherals v buses trong h thng, v kt ni ca h thng (system connectivity).

Hnh 15: Ca s Xilinx Platform Studio (System Assembly View) vi Bus Interfaces

Hnh 16: Bus Interfaces

Hnh 17: Ca s Xilinx Platform Studio (System Assembly View), vi Ports 5.2. Bc 2: Phn tch phn cng To mt s khi ca h thng v nghin cu cc thnh phn v interconnections ca h thng. Xem xt System Assembly View v phn tch bus v cc kt ni bus. Chy PlatGen to system netlists (NGC) v xem xt trong Design Summary. Xem li cc files c to ra. i) Kch chut vo tab Block Diagram hin th s khi ca h thng (hnh 18), trong c cc khi: LMB BRAM + controller lu Data + instructions, khi Microblaze Processor v khi PLB Peripherals ni vi Microblaze Processor. Hnh 19 l cc biu din v mu cho cc thnh phn trn Block Diagram. Hnh 20: c im ca Spartan 3E Starter board, v phin bn ca EDK.

Hnh 18: Block Diagram ca h thng

Hnh 19: Cc k hiu trn Block Diagram ca h thng

Hnh 20: c tnh ca Spartan 3E Starter board v phin bn EDK.

Hnh 21: LMB BRAM + controller lu Data + instructions

Hnh 22: Microblaze

Hnh 23: Clock generator

Hnh 24: PLB Peripherals

Hnh 25: System Assembly View vi Bus Interfaces

ii)

Kch chut vo tab System Assembly View hin th li ca s System Assembly View nh cho hnh 15. Trn ca s ny, Bus Interfaces kch chut vo cc nt + m rng xem cc chi tit (hnh 25). Tng t, ta chn Ports v kch vo cc nt + m rng chi tit ca Ports (hnh 26), chn Address xem chi tit cc a ch cho peripherals trong h thng (hnh 27).

Hnh 26: Ports

Hnh 27: Addresses cho Peripherals trong h thng iii) Chy PlatGen: Hardware Generate Netlist hoc kch chut biu tng trn thc n. r tr li).

(Ch : phi ch khong 5 pht to Netlist: cho n khi no biu tng iv)

Kch chut tab Design Summary xem ton b thng tin v h thng thit k, reports, v messages.

5.3. Bc 3: Kim tra phn cng To Bitstream v ti Bitstream ln Spartan 3E Starter board. Bitstream s c ghi ln B nh lnh (Block RAM ca FPGA). i) To bitstream: Hardware -> Generate Bitstream (hoc kch chut biu tng10 01

trn thc n)10 01

(Ch : phi ch hn 1 gi to Bitstream cho n khi no biu tng ii) Ti Bitstream ln Spartan 3E Starter Board: Device Configuration -> Download Bitstream 6. Ni dung cc File 6.1. NHS File: system.mhs

r tr li)

# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1 # Thu Mar 29 23:23:39 2012 # Target Board: Xilinx Spartan-3E Starter Board Rev D # Family: spartan3e # Device: XC3S500e # Package: FG320 # Speed Grade: -4

# Processor number: 1 # Processor 1: microblaze_0 # System clock frequency: 50.0 # Debug Interface: On-Chip HW Debug Module # ############################################################################## PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DTE_RX_pin = fpga_0_RS232_DTE_RX_pin, DIR = I PORT fpga_0_RS232_DTE_TX_pin = fpga_0_RS232_DTE_TX_pin, DIR = O PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX_pin, DIR = I PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX_pin, DIR = O PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7] PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3] PORT fpga_0_Buttons_4Bit_GPIO_IO_I_pin = fpga_0_Buttons_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3] PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A_pin_vslice_8_31_concat, DIR = O, VEC = [8:31] PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN_pin, DIR = O PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN_pin, DIR = O PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN_pin, DIR = O PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ_pin, DIR = IO, VEC = [0:7] PORT fpga_0_FLASH_BEN_pin = net_gnd, DIR = O PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0] PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0] PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0] PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IO PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0] PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1

BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_FAMILY = spartan3e PARAMETER C_AREA_OPTIMIZED = 1

PARAMETER C_INTERCONNECT = 1 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER HW_VER = 7.20.a BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_mdm_bus PORT MB_RESET = mb_reset END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER C_FAMILY = spartan3e PARAMETER HW_VER = 1.04.a PORT PLB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER C_FAMILY = spartan3e PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port

BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_DTE PARAMETER C_FAMILY = spartan3e PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER HW_VER = 1.01.a PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_DTE_RX_pin PORT TX = fpga_0_RS232_DTE_TX_pin END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_DCE PARAMETER C_FAMILY = spartan3e PARAMETER C_BAUDRATE = 115200 PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER HW_VER = 1.01.a PARAMETER C_BASEADDR = 0x84020000 PARAMETER C_HIGHADDR = 0x8402ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_DCE_RX_pin PORT TX = fpga_0_RS232_DCE_TX_pin END BEGIN xps_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER C_FAMILY = spartan3e PARAMETER C_ALL_INPUTS = 0 PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin END BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER C_FAMILY = spartan3e PARAMETER C_ALL_INPUTS = 1 PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81420000 PARAMETER C_HIGHADDR = 0x8142ffff

BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin END BEGIN xps_gpio PARAMETER INSTANCE = Buttons_4Bit PARAMETER C_FAMILY = spartan3e PARAMETER C_ALL_INPUTS = 1 PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81440000 PARAMETER C_HIGHADDR = 0x8144ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_I = fpga_0_Buttons_4Bit_GPIO_IO_I_pin END BEGIN xps_mch_emc PARAMETER INSTANCE = FLASH PARAMETER C_FAMILY = spartan3e PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_NUM_CHANNELS = 0 PARAMETER C_MEM0_WIDTH = 8 PARAMETER C_MAX_MEM_WIDTH = 8 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 PARAMETER C_SYNCH_MEM_0 = 0 PARAMETER C_TCEDV_PS_MEM_0 = 110000 PARAMETER C_TAVDV_PS_MEM_0 = 110000 PARAMETER C_THZCE_PS_MEM_0 = 35000 PARAMETER C_TWC_PS_MEM_0 = 110000 PARAMETER C_TWP_PS_MEM_0 = 70000 PARAMETER C_TLZWE_PS_MEM_0 = 15000 PARAMETER HW_VER = 3.00.a PARAMETER C_MEM0_BASEADDR = 0x89000000 PARAMETER C_MEM0_HIGHADDR = 0x89ffffff BUS_INTERFACE SPLB = mb_plb PORT RdClk = clk_50_0000MHz PORT Mem_A = 0b00000000 & fpga_0_FLASH_Mem_A_pin_vslice_8_31_concat PORT Mem_CEN = fpga_0_FLASH_Mem_CEN_pin PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin END BEGIN mpmc PARAMETER INSTANCE = DDR_SDRAM PARAMETER C_FAMILY = spartan3e PARAMETER C_NUM_PORTS = 1 PARAMETER C_SPECIAL_BOARD = S3E_STKIT PARAMETER C_MEM_TYPE = DDR PARAMETER C_MEM_PARTNO = MT46V32M16-6 PARAMETER C_MEM_BANKADDR_WIDTH = 2 PARAMETER C_MEM_DATA_WIDTH = 16 PARAMETER C_MEM_DM_WIDTH = 2 PARAMETER C_MEM_DQS_WIDTH = 2

PARAMETER C_PIM0_BASETYPE = 2 PARAMETER HW_VER = 5.00.a PARAMETER C_MPMC_BASEADDR = 0x8c000000 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff BUS_INTERFACE SPLB0 = mb_plb PORT MPMC_Clk0 = clk_100_0000MHzDCM0 PORT MPMC_Clk90 = clk_100_0000MHz90DCM0 PORT MPMC_Rst = sys_periph_reset PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin END BEGIN xps_ethernetlite PARAMETER INSTANCE = Ethernet_MAC PARAMETER C_FAMILY = spartan3e PARAMETER HW_VER = 2.01.a PARAMETER C_BASEADDR = 0x81000000 PARAMETER C_HIGHADDR = 0x8100ffff BUS_INTERFACE SPLB = mb_plb PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 100000000 PARAMETER C_CLKOUT0_PHASE = 90 PARAMETER C_CLKOUT0_GROUP = DCM0 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT1_FREQ = 100000000 PARAMETER C_CLKOUT1_PHASE = 0 PARAMETER C_CLKOUT1_GROUP = DCM0 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT2_FREQ = 50000000 PARAMETER C_CLKOUT2_PHASE = 0 PARAMETER C_CLKOUT2_GROUP = NONE

PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER HW_VER = 3.00.a PORT CLKIN = dcm_clk_s PORT CLKOUT0 = clk_100_0000MHz90DCM0 PORT CLKOUT1 = clk_100_0000MHzDCM0 PORT CLKOUT2 = clk_50_0000MHz PORT RST = net_gnd PORT LOCKED = Dcm_all_locked END BEGIN mdm PARAMETER INSTANCE = mdm_0 PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER HW_VER = 1.00.e PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER HW_VER = 2.00.a PORT Slowest_sync_clk = clk_50_0000MHz PORT Ext_Reset_In = sys_rst_s PORT MB_Debug_Sys_Rst = Debug_SYS_Rst PORT Dcm_locked = Dcm_all_locked PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT Peripheral_Reset = sys_periph_reset END

6.2. MSS File: system.mssPARAMETER VERSION = 2.2.0 BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 2.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER STDIN = RS232_DTE PARAMETER STDOUT = RS232_DTE END

BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.11.c PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar

END

BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = lmb_bram END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.14.a PARAMETER HW_INSTANCE = RS232_DTE END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.14.a PARAMETER HW_INSTANCE = RS232_DCE END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.13.a PARAMETER HW_INSTANCE = LEDs_8Bit END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.13.a PARAMETER HW_INSTANCE = DIP_Switches_4Bit END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.13.a PARAMETER HW_INSTANCE = Buttons_4Bit END BEGIN DRIVER PARAMETER DRIVER_NAME = emc PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = FLASH END

BEGIN DRIVER PARAMETER DRIVER_NAME = mpmc PARAMETER DRIVER_VER = 3.00.a PARAMETER HW_INSTANCE = DDR_SDRAM END BEGIN DRIVER PARAMETER DRIVER_NAME = emaclite PARAMETER DRIVER_VER = 1.14.a PARAMETER HW_INSTANCE = Ethernet_MAC END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = clock_generator_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.14.a PARAMETER HW_INSTANCE = mdm_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = proc_sys_reset_0 END

Start XPS Using the Base System Builder Wizard and include following hardware components:

MicroBlaze on Xilinx Spartan-3E Starter Board revision D, running in 50MHz Build the hardware system using "Hardware" > "Generate Bitstream". Step B. Hello World Click the "Application" tab in the left box and start a new application. Set the other application to "inactive" Write a hello world application and print a string using the statement xil_printf("hello world\n"); /* xil_printf() is a light-weight version of printf() */ Open a hyperterminal and connect it to the serial port. (Programs > Accessories > Communications > HyperTerminal), set it to connect to the serial port (COM1), 9600 bit rate, 8 bit data and no parity Connect the Spartan 3E FPGA to the USB port and serial port. Build the software and download the bitstream to the FPGA Part 2. Using LEDs via GPIO and input from UART Step A. Use GPIO to control the LED The microblaze processor is configured in part 1 ti connect to the LED via GPIO. You can read from the GPIO and write to the GPIO. In this case, only writing is necessary. Include header file "xgpio_1.h" to use the GPIO functions. When using the GPIO, first you have to specify whether a bit is for input or output. Use the following to set it: XGpio_Initialize(BASEADDR, DEVICE_ID); XGpio_mSetDataDirection(BASEADDR, 1, 0x00000000); The first parameter is the address mapped to the GPIO. The second parameter is the GPIO channel, which is 1 in this case. The third parameter is for setting the read/write mode of individual bit, 1 means for read and 0 means for write. You can then write to the GPIO using the following function: XGpio_mSetDataReg(BASEADDR, 1, data); Write an application that turn on the LED lights one at a time from left to right (or any pattern of your choice). The lights should change every half a second. You can use a busy waiting loop here to wait for time. Step B.Use Timer and Interrupt Handler

Timer can be used to generate interrupt in regular intervals. A timer is setup in part 1 with interrupt enabled. When the timeout expired, a interrupt will be generated to your microblaze processor. To setup a interrupt handler, use the following function: #include "xtmrctr_1.h" #include "xintc_1.h" /* Enable MicroBlaze interrupts */ microblaze_enable_interrupts(); /* Register the interrupt handler in the vector table */ XIntc_RegisterHandler(INTC_BASEADDR, INTR, (XInterruptHandler)handler, (void*)BASEADDR); /* Start the interrupt controller */ XIntc_mMasterEnable(INTC_BASEADDR); to set the timer: /* Set the number of cycles the timer counts before interrupting */ XTmrCtr_mSetLoadReg(BASEADDR, 0, time_tick); /* Reset the timers, and clear interrupts */ XTmrCtr_mSetControlStatusReg(TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); /* Enable interrupt requests in the interrupt controller */ XIntc_mEnableIntr(INTC_BASEADDR, TIMER_INTERRUPT_MASK); /* Start the timers */ XTmrCtr_mSetControlStatusReg(TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); interruptHander is a function with the following function declaration: void handler(void * baseaddr_p); and for timer interrupt, you can use the following template: void timer_int_handler(void * baseaddr_p) { unsigned int csr; /* Read timer 0 CSR to see if it requested the interrupt */ csr = XTmrCtr_mGetControlStatusReg(BASEADDR, 0); if (csr & INT_OCCURED_MASK) { /* handler interrupt here*/ } /* Clear the timer interrupt */ XTmrCtr_mSetControlStatusReg(BASEADDR, 0, csr); }

Copy your code from step A and modify it to use the timer instead of busy-waiting loop. Step C.Use UART to read character from serial port The microblaze processor is configured in part 1 to connect to the serial port via UART and use interrupt. When a character is entered into hyperterminal, the character is sent to the UART and an interrupt is generated. You can setup a interrupt handler for UART interrupt just like you did for timer interrupt, and read the characters one by one from the UART using the following function: #include "xuartlite_1.h" XUartLite_mIsReceiveEmpty(BASEADDR) is false when there is data waiting to be read XUartLite_RecvByte(BASEADDR) return one character (char)

enable UART interrupt /* Enable interrupt requests in the interrupt controller */ XIntc_mEnableIntr(INTC_BASEADDR, TIMER_INTERRUPT_MASK | UART_INTERRUPT_MASK); /* Enable UART interrupts */ XUartLite_mEnableIntr(BASEADDR); Copy your code from step B and modify it to decrease the time between LED changes by half if a '[' is received and increase the time two times if a ']' is received.

CS122B, Winter 2007

Part 3. Write Characters to the LCD Display (Software) In this part you will need to display characters in the 12 x 2 character LCD monitor on the FPGA. You should connect your Microblaze processor to the LCD using a GPIO. Your job is to add necessary hardwares to your Microblaze system, write software to correctly initialize the LCD and update the characters in the LCD according to the inputs from hyperterminal. The specification of the LCD is here. [ Although not necessary, it is recommended to set (SF_OE[C18]) (SF_WE[D17]) (SF_CE0[D16]) to '1'] Step A. Configure the hardware

Add a GPIO instance to your Microblaze system Update the memory map Modify the hardware description (MHS) manually or using the XPS interface Edit the UCF file to map GPIO pins to the corresponding pins for LCD Step B. Write software to initialize the LCD Follow the specification, initialize the LCD and clear the LCD monitor. You can use busy waiting loop or timer. Test your initialize sequence Step C. Write software to update the LCD You need to write a software to display the characters [a-zA-Z ,.] you enter in the hyperterminal to the LCD. Configure the LCD to automatically advance the curser. Use arrows to control the curser position. (the characters you will receive are a sequence of 3 characters: [1B 5B 41] to [1B 5B 44] in the order of up, down, right, left) Use '' to rotate the displayCS122B, Winter 2007

Q1. What is the design flow when developing a Microblaze system? Q2. How does Microblaze processor access other peripherals? Q3. Compare the software and hardware approaches to display characters in the LCD. How would you design a LCD display controller in VHDL. List the pros and cons of each approach.