MicroBlaze 32-bits Softcore CPU

implementation in Fractional Divider

January 29th, 2019

Stéphane Rey – BE-RF-FB

Nathan Pittet – BE-RF-FB

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• 32-bits RISC CPU running up to 200 DMIPS (600 MHz clock on Spartan-6)

• 32-bits Address bus extensible to 64-bits

• Scalable peripherals and memory

• AXI Interface (Advanced eXtensible Interface) with FPGA logic

• I²C, QSPI, ethernet, UART, DMA, Timers, Interrupts, FPU,

• C/C++ toolchain, RTOS capable (FreeRTOS, Linux, RREX…)

FEATURES

MicroBlaze

32-bits

Processor Core

Timer

Interrupt

Controller

SPI

I²C

DMA

UART

Cache

DDR controler

Ethernet

GPIO

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CPU ARCHITECTURE

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• Easy to read and understand software (C/C++ langage)

• Fast debug

• Already made peripherals drivers (I²C, SPI, timers, ethernet, DMA, …)

• Especially suitable for low-speed protocols and HMI peripherals (Displays, I/O

devices, …), control and state machine applications

BENEFITS

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INTEGRATION

µBlazeGPIOs

SPI, I²C

Ethernet

…

• Communication between MicroBlaze and VHDL achieved through AXI interface

AXI

Memmap

slave

AXI

VME

Submap

VME

Submap

Submap

AXI

Memmap

slaveA

XI

VHDL

processing

MEMMAPVME

Interface

FEC

FPGA

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TOOLCHAIN

Visual

Elite

XPS

ISE

SDK

iMPACT

Cheby

Chiptop.vhd

chiptop.bit

sourcecode.elf

*.bit, *.mcs

memap.vhd

memap.xml

sfd make

sfd make

To FPGA

Debug

download.bit

*.c

*.h

sfd make

update_VisualWrappers

uBlaze_wrapper.vhd

Ublaze_top.vhd

Ublaze.xmp

Sourcecode.elfsfd make

update_SDKHWPlatform

sfd make

update_uBlaze_top

sfd make import_memmap

42,6

3

1

5

7

89

10

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XPS – MICROBLAZE DEFINITION

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MICROBLAZE IN VISUAL ELITE

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SFD – MICROBLAZE SOFTWARE

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EXAMPLE : I²C USING VISUAL ELITE

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EXAMPLE : I²C USING VISUAL ELITE

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EXAMPLE : I²C USING VISUAL ELITE

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EXAMPLE : I²C USING MICROBLAZE

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• Compilation and access to debug in few seconds

DEBUG WITH MICROBLAZE

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• Front-end to Microblaze bridge implementation

• FPGA to Microblaze bridge implementation

• OS (FreeRTOS, RREX) implementation

NEXT STEPS

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Thank you for your attention