Machine Language

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Machine Language. ELEC 330 Digital Systems Engineering Dr. Ron Hayne. The 68HC11 Microcomputer. Programming Model Memory Model Microprocessor Model Internal Computer Operations Instruction Fetch Instruction Execution Machine Language Programming. Programming Model. - PowerPoint PPT Presentation

Text of Machine Language

  • Machine LanguageELEC 330Digital Systems EngineeringDr. Ron Hayne

    330_02

  • 330_02*The 68HC11 MicrocomputerProgramming ModelMemory ModelMicroprocessor ModelInternal Computer OperationsInstruction FetchInstruction ExecutionMachine Language Programming

    330_02

  • 330_02*Programming ModelMotorola 68HC11 Microcomputer

    7 A 07 B 08-bit Accumulators A & B15 D 016-bit Double Accumulator D

    15 X 0Index Register X

    15 Y 0Index Register Y

    15 SP 0Stack Pointer

    15 PC 0Program Counter

    SXHINZVCCondition Code Register

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  • 330_02*Memory Model

    0000C329B6C23AC1C23B33

    FFFF22

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  • 330_02*Instruction FormatLoad Accumulator ALDAA $C200

    C100B6 Op Code of LDAAC101C2 Address of DataC10200C20044 Data number

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  • 330_02*Microprocessor ModelProgram CounterInstruction RegisterAccumulators

    PC

    IR

    A

    B

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  • 330_02*Computer OperationExample Instruction (LDAA)Register and Memory contents

    PCC100B6C100C101C2IRC10200A22BC2004433

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  • 330_02*Instruction FetchPC to Memory as AddressRead

    PCC100B6C100C101C2IRC10200A22BC2004433

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  • 330_02*Instruction FetchMemory sends number at address to IRIncrement PC

    PCC100B6C101C101C2IRC10200B6A22BC2004433

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  • 330_02*Instruction FetchPC to Memory as AddressRead

    PCC100B6C101C101C2IRC10200B6A22BC2004433

    330_02

  • 330_02*Instruction FetchMemory sends number at address to IRIncrement PC

    PCC100B6C102C101C2IRC10200B6C2A22BC2004433

    330_02

  • 330_02*Instruction FetchPC to Memory as AddressRead

    PCC100B6C102C101C2IRC10200B6C2A22BC2004433

    330_02

  • 330_02*Instruction FetchMemory sends number at address to IRIncrement PC

    PCC100B6C103C101C2IRC10200B6C200A22BC2004433

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  • 330_02*Instruction FetchRegister Contents after Fetch

    PCC100B6C103C101C2IRC10200B6C200A22BC2004433

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  • 330_02*Instruction ExecutionData Address to MemoryRead

    PCC100B6C103C101C2IRC10200B6C200A22BC2004433

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  • 330_02*Instruction ExecutionMemory sends data at address to A

    PCC100B6C103C101C2IRC10200B6C200A44BC2004433

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  • 330_02*Instruction ExecutionFinal Register Contents

    PCC100B6C103C101C2IRC10200B6C200A44BC2004433

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  • 330_02*Instruction Set TableOperandhh llhigh and low bytes of address

    Source FormOperationBoolean ExpressionMachine CodeBytesOp CodeOperandADDAAdd Memory to AA + M ABBhh ll3LDAALoad Accumulator AM AB6hh ll3STAAStore Accumulator AA MB7hh ll3STOPStop Program3F1

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  • 330_02*Machine Language ProgrammingN1 + N2 SUM

    PCLDAAC200B6C200C201C2AC2020BADDAC203BBBC204C2C2050CSTAAC206B7C207C2N1C20B02C2080DN2C20C29STOPC2093FSUMC20DFFC20A

    330_02

  • 330_02*Machine Language ProgrammingN1 + N2 SUM

    PCLDAAC200B6C203C201C2AC2020B02ADDAC203BBBC204C2C2050CSTAAC206B7C207C2N1C20B02C2080DN2C20C29STOPC2093FSUMC20DFFC20A

    330_02

  • 330_02*Machine Language ProgrammingN1 + N2 SUM

    PCLDAAC200B6C206C201C2AC2020B2BADDAC203BBBC204C2C2050CSTAAC206B7C207C2N1C20B02C2080DN2C20C29STOPC2093FSUMC20DFFC20A

    330_02

  • 330_02*Machine Language ProgrammingN1 + N2 SUM

    PCLDAAC200B6C209C201C2AC2020B2BADDAC203BBBC204C2C2050CSTAAC206B7C207C2N1C20B02C2080DN2C20C29STOPC2093FSUMC20D2BC20A

    330_02

  • 330_02*Machine Language ProgrammingN1 + N2 SUM

    PCLDAAC200B6C20AC201C2AC2020B2BADDAC203BBBC204C2C2050CSTAAC206B7C207C2N1C20B02C2080DN2C20C29STOPC2093FSUMC20D2BC20A

    330_02

  • 330_02*SummaryProgramming ModelMemory ModelMicroprocessor ModelInternal Computer OperationsInstruction FetchInstruction ExecutionMachine Language Programming

    330_02

  • 330_02*Instructions and AddressingAddressing ModesExtended AddressingDirect AddressingInherent AddressingImmediate AddressingIndexed AddressingRelative Addressing

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  • 330_02*AddressingEffective AddressAddress formed by microprocessor as part of instruction executionAddressing ModesVarious ways addresses are formedMemory MapVisual technique for understanding implications of addressing modes

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  • 330_02*Extended AddressingComplete 16-bit Address of Data

    PCLDAAC200B6C200 EXTC201C2AC2020BADDAC203BBB EXTC204C2C2050CSTAAC206B7 EXTC207C2N1C20B02C2080DN2C20C29STOPC2093FSUMC20DFFC20A

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  • 330_02*Direct AddressingShortened 8-bit AddressMost-significant byte 00Address Range0000 through 00FFZero Page AddressingShorter and Faster InstructionsUse less memoryFetched faster

    N1001002N2001129SUM0012FFLDAAC20096 DIRC20110ADDAC2029B DIRC20311STAAC20497 DIRC20512STOPC2063F

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  • 330_02*Inherent (Implied) AddressingSome instructions operate on microprocessor registers onlyNo memory address neededExampleABAA + B A

    N1001002N2001129SUM0012FFLDAAC20096 DIRC20110LDABC202D6 DIRC20311ABAC2041BSTAAC20597 DIRC20612STOPC2073F

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  • 330_02*Double-Byte DataSome registers hold 16-bit (double-byte) dataD, X, Y, SPExampleLDXM:(M+1) XBig-endian conventionHigh byte at first (lower) addressLow byte at second (higher) address

    LDXFE EXTC234XC234565678C23578

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  • 330_02*Immediate AddressingConstant data placed inside an instructionNo memory addressFewer bytes of memoryData immediately available at end of fetch phaseFaster execution

    LDAA86A IMM2222LDXCEX IMM12123434

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  • 330_02*Indexed AddressingOp Code and Offset ByteEffective AddressOffset (unsigned) added to Index Register (pointer)Index Register unchangedExampleLDAA 2,XM[2+X] A

    LDAAA6AINDX0247C20022XC20133C200C20247C203B7

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  • 330_02*Relative AddressingBranch InstructionsMake decisionsAlter program flowCondition Code RegisterReports test results

    SXHINZVCCondition Code Register

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  • 330_02*Condition Code BitsC (Carry)Carry-out from the most-significant bitV (Overflow)Twos complement overflow errorZ (Zero)Result contains all zerosN (Negative)Result is negativeH (Half-carry)Carry from halfway (bit 3)Generally used only with BCD numbersS, X, IHardware control bits (later...)

    330_02

  • 330_02*ExampleADDA

    CH111110101010A = N1+10111100M = N201100110A = SUMN

    xx1x0011CCRSXHINZVC

    330_02

  • 330_02*Condition Code NotationNot all instructions affect all the condition code bitsAlways use the instruction set table to determine how the bits workDont assume!

    SymbolOperation-Bit is unaffected by this instruction0Bit is always cleared to 0 by this instruction1Bit is always set to 1 by this instructionBit is set or cleared depending on instruction

    330_02

  • 330_02*Branch InstructionsMay alter program flow based on the condition code bitsProgram CounterRelative AddressingSigned OffsetEffective AddressPC plus OffsetBranch Range?

    Op Code27PCOffset04xxxxNo BranchBranch

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  • 330_02*Branch Not Equal to ZeroBNEBranch if Not = Zero? Z = 0

    Example LDAA N1LOOP ADDA #-1 BNE LOOP STOP

    N1001004LDAAC20096 DIRC20110ADDAC2028B IMMC203FFBNEC20426 RELC205FCSTOPC2063FC273

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  • 330_02*Addressing Mode Summary

    INHERENTOp Code

    IMMEDIATEOp CodeOp CodeDataData-highData-low

    DIRECTOp CodeEffective AddressAddress-low00dd

    EXTENDEDOp CodeEffective AddressAddress-highhhllAddress-low

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  • 330_02*Addressing Mode Summary

    INDEXEDOp CodeEffective AddressOffset +

    Index Register

    RELATIVEOp CodeEffective AddressRelative offset +

    Program Counter

    330_02

  • 330_02*Basic InstructionsArithmetic and LogicLoad and StoreInput and OutputTesting and Branching

    330_02

  • 330_02*Programming ModelMotorola 68HC11 Microcomputer

    7 A 07 B 08-bit Accumulators A & B15 D 016-bit Double Accumulator D

    15 X 0Index Register X

    15 Y 0Index Register Y

    15 SP 0Stack Pointer

    15 PC 0Program Counter

    SXHINZVCCondition Code Register

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  • 330_02*Instruction Set TableSource FormInstruction mnemonicType of operand(opr)data or data address (rel)relative offsetOperationShort word descriptionBooelan ExpressionDetailed description of register transfersAddressing Mode

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  • 330_02*Instruction Set TableOp CodeMachine code for corresponding addressing modeOperandii8-bit immediate dataddlow byte of direct addresshh llhigh and low bytes of extended addressffunsigned 8-bit offset for indexed addressingjj kkhigh and low bytes of 16-bit immediate datarrsigned 8-bit relative offset for branch

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  • 330_02*Instruction Set TableBytesNumber of bytes of memory (op code + operand)CyclesNumber of clock cycles to fetch and executeCondition Codes

    SymbolOperation-Bit is unaffected by this instruction0Bit is always clear