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B. E. Boser 1
Advanced Analog Integrated Circuits
Device Models
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – Device Models
B. E. Boser 2
The Problem With MOS Transistor Models
EE240B – Device Models
B. E. Boser 3
Simulator Models (BSIM, …)
EE240B – Device Models
180nm NMOS model parameters:
B. E. Boser 4
Square Law Model
EE240B – Device Models
180nm NMOSSquare LawBJT
[ B. Murmann ]
Huge discrepancyat large current
Does not modelsubthreshold region (weak inversion)
B. E. Boser 5
Middle of the Road: EKV Model
C. Enz and E. A.Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design, Wiley, 2006.
EE240B – Device Models
180nm NMOSSquare LawEKV
[ B. Murmann ]
In saturation region:
𝐼" = 2𝑛𝑉'( ) 𝜇𝐶,-𝑊𝐿 𝑞1( + 𝑞1
𝑉34 − 𝑉67 = 𝑛𝑉' 2 𝑞1 − 1 + ln 𝑞1
• Only 3 parameters: 𝑉67, 𝑛, 𝜇𝐶,-;<
(functions of 𝐿, …)• Parametric in 𝑞1, normalized source
charge density• Good agreement except at high 𝐼"• Still impractical for hand calculations
B. E. Boser 6
Designer’s Wish list
EE240B – Device Models
B. E. Boser 7
240B Approach
EE240B – Device Models
B. E. Boser 8
Basic Transistor Model for Design
EE240B – Device Models
B. E. Boser 9
Transistor FOMs
EE240B – Device Models
B. E. Boser 10
FOMs for 180nm Process
EE240B – Device Models
B. E. Boser 11
Subthreshold Conduction (Weak Inversion)
EE240B – Device Models
Channel potential is higher than source à
forward bias
B. E. Boser 12
gm/ID or V*
𝑔>𝐼"[1/V] 𝑉∗[mV]
38.5 2Vt = 5230 6725 8020 10016 125
12.5 16010 200
EE240B – Device Models
𝑉∗ =2𝐼"𝑔>
𝑔 > 𝐼 "=2 𝑉∗
Interchangeable, use whichever you prefer
B. E. Boser 13
𝑓6 versus 𝑉∗ (not 𝑉34)
EE240B – Device Models
B. E. Boser 14
Relative Power Efficiency
EE240B – Device Models
Same data, but horizontal axis shows current efficiency relative to 𝑉∗ = 120mV HI
JK= 16.7S/A .
For the 180nm device, the 𝑓6decreases by more than 20x when 𝑉∗ is lowered to 80mV for a 50% higher current efficiency.
Increasing 𝑉∗ to 180mV decreases the current efficiency by 50% but boosts 𝑓6 only by a factor 2.5.
Devices are rarely operated with 𝑉∗ outside the range 80mV … 200mV.
B. E. Boser 15
Composite 𝑭𝑶𝑴 = 𝒇𝑻 )𝒈𝒎𝑰𝑫
EE240B – Device Models
B. E. Boser 16
Noise Model
EE240B – Device Models
A. J. Scholten et al., “Noise modeling for RF CMOS circuit simulation,” IEEE Trans. Electron Dev., pp. 618-632, Mar. 2003.
𝑖[,]( = 4𝑘`𝑇bHI∆𝑓
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Extracting 𝛾 with Simulator
EE240B – Device Models
B. E. Boser 18
Intrinsic Gain
EE240B – Device Models
B. E. Boser 19
“Saturation”
EE240B – Device Models
B. E. Boser 20
av versus VDS
EE240B – Device Models
V*
𝑉 "4=𝑉∗
𝑉 "4=2𝑉
∗
B. E. Boser 21
Advanced Analog Integrated Circuits
Extrinsic Elements
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – Device Models
B. E. Boser 22
Extrinsic Circuit Elements
EE240B – Device Models
B. E. Boser 23
MOS Capacitances
EE240B – Device Models
Carusone, Johns, Martin, Analog Integrated Circuit Design, 2nd Edition, Wiley, 2011, p. 31.
Get parameters from technology file
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Source and Drain Junctions – Layout
EE240B – Device Models
B. E. Boser 25
Complete Small Signal Model
EE240B – Device Models
[ B. Murmann ]
B. E. Boser 26
Gate Capacitance Summary
EE240B – Device Models
Subthreshold Triode Saturation
CGS Col CGC/2 + Col 2/3 CGC + Col
CGD Col CGC/2 + Col Col
CGB CGC // CCB 0 0
𝐶,e = 𝑊𝐶,ef𝐶3g = 𝑊𝐿𝐶,-
𝐶g` =1𝐶h1
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Well Capacitance
EE240B – Device Models
Dbsub not part of 4-terminal SPICE transistor model!
[ B. Murmann ]
B. E. Boser 28
Extrinsic Capacitances
EE240B – Device Models
B. E. Boser 29
Extrinsic Capacitance versus L
EE240B – Device Models
[ B. Murmann ]
B. E. Boser 30
Advanced Analog Integrated Circuits
Design Flow
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – Device Models
B. E. Boser 31
Generic Design Flow
EE240B – Device Models
B. E. Boser 32
Current Density à W
EE240B – Device Models
