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  • Low Voltage Intel Pentium III Processor with 512KB L2 Cache

    Datasheet

    Product Features

    The LV Intel Pentium III processor 512K is designed for high-performance computing applications. It is binary compatible with previous Intel Architecture processors. The processor provides great performance for applications that run on advanced operating systems such as Microsoft* Windows* NT, Microsoft Windows 2000, Microsoft Windows XP and Linux. This is achieved by integrating the best attributes of Intel processorsthe dynamic execution, Dual Independent Bus architecture plus Intel MMX technology, and Internet Streaming SIMD Extensionsto bring a new level of performance to system designs. The LV Intel Pentium III processor with 512 Kbytes of L2 cache extends the power of the Intel Pentium III processor with performance headroom for applied computing and communications applications, and for high density Web serving and other front-end operations. Systems based on the LV Intel Pentium III Processor 512K also include the latest features to simplify system management and lower the cost of ownership.

    Available at 800, 933, and 1000 MHz with a 133 MHz system bus frequency at 1.15 V (LV)

    512-Kbyte Advanced Transfer Cache (on-die, full speed level two (L2) cache with Error Correcting Code (ECC))

    Dual Independent Bus (DIB) architecture: separate dedicated external system bus and dedicated internal high-speed cache bus

    Internet Streaming SIMD Extensions for enhanced video, sound and 3D performance

    Binary compatible with applications running on previous members of the Intel microprocessor line

    Dynamic execution micro architecture Power Management capabilities

    System Management modeMultiple low-power states

    Optimized for 32-bit applications running on advanced 32-bit operating systems

    Micro-FCBGA packaging technologySupports small form factor designsExposed die enables more efficient heat

    dissipation Integrated high performance 16 Kbyte

    instruction and 16 Kbyte data, nonblocking, level one cache

    Quad Quadword Wide (256-bit) cache data bus provides extremely high throughput on read/store operations

    8-way cache associativity provides improved cache hit rate on reads/store operations

    Error-correcting code for system bus data Dual processor capable

    Order Number: 273673-005Jan 2003

  • 2

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    AlertVIEW, i960, AnDM3, EtherExpressIntelDX2, IntelDX4,NetBurst, Intel NetSIntel WebOutfitter, Ilogo, OverDrive, PaRemoteExpress, ScTokenExpress, Trilliother countries.

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    Datasheet

    ocument is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual anted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability el disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not medical, life saving, or life sustaining applications.

    nges to specifications and product descriptions at any time, without notice.

    rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

    tel Pentium III processor 512K may contain design defects or errors known as errata that may cause the product to deviate from tions. Current characterized errata are available on request.

    tional standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled ire licenses from various entities, including Intel Corporation.

    ntel sales office or your distributor to obtain the latest specifications and before placing your product order.

    ts that have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling by visiting Intel's website at http://www.intel.com.

    orporation, 2003

    yPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, , ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel tructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, ntel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer ragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, reamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, um, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and

    rands may be claimed as the property of others.

  • Contents

    Contents1.0 Introduction....................................................................................................................................7

    1.1 Overview...............................................................................................................................71.2 Terminology ..........................................................................................................................81.3 Related Documents ..............................................................................................................9

    2.0 Processor Features .....................................................................................................................102.1 512-Kbyte On-Die Integrated L2 Cache .............................................................................102.2 Data Prefetch Logic ............................................................................................................102.3 Processor System Bus and VREF.............................................................................................................. 102.4 Differential Clocking............................................................................................................112.5 Clock Control and Low Power States .................................................................................11

    2.5.1 Normal StateState 1...........................................................................................122.5.2 AutoHALT Power Down StateState 2 ................................................................122.5.3 Stop-Grant StateState 3.....................................................................................132.5.4 HALT/Grant Snoop StateState 4........................................................................132.5.5 Sleep StateState 5 .............................................................................................132.5.6 Clock Control .........................................................................................................14

    2.6 Power and Ground Balls .....................................................................................................142.7 Processor System Bus Clock and Processor Clocking ......................................................142.8 Processor System Bus Unused Balls .................................................................................152.9 LV Intel Pentium III Processor 512K CPUID.......................................................................15

    3.0 Electrical Specifications .............................................................................................................163.1 Processor System Bus Signal Groups................................................................................16

    3.1.1 Asynchronous vs. Synchronous for System Bus Signals ......................................173.1.2 System Bus Frequency Select Signals ..................................................................17

    3.2 Single-Ended Clocking BSEL[1:0] Implementation.............................................................173.3 Differential Host Bus Clocking Routing...............................................................................18

    3.3.1 Differential Clocking BSEL[1:0] Implementation ....................................................183.4 Signal State in Low-Power States ......................................................................................19

    3.4.1 System Bus Signals ...............................................................................................193.4.2 CMOS and Open-Drain Signals.............................................................................193.4.3 Other Signals .........................................................................................................19

    3.5 Test Access Port (TAP) Connection ...................................................................................203.6 Power Supply Requirements ..............................................................................................20

    3.6.1 Decoupling Guidelines......................................................

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