low power techniques in vlsi

M.S.Ramaiah School of Advanced Studies, Bangalore 1

Name : Rama Krishna P.Reg No : CGB0911012Course : M.Sc. [Engg.] in VLSI System DesignModule : Integrated Circuit Analysis and DesignModule Leader : Prof. Cyril Prasanna Raj P.

LOW POWER TECHNIQUES IN NANOMETER TECHNOLOGY


Discussion

Why low power?

Types of power consumption

• Dynamic power

• Static power

Low power techniques

• Clock gating

• Multi vdd

• Multiple vth

• Power gating

Trade off

Future scope

Conclusion

References


Why low power...?

Desirability of portable devices.

Advent of hand held battery operated devices.

Large power dissipation requires larger heat sinks hence increased area.

Cost of providing power has resulted in significant interest in power reduction

of non portable devices.

Lowering transistor threshold voltage.

Pavg=Pswitching+Pshort-circuit + Pleakage

=α0 1CL Vdd2 fclk + Vdd Isc +Ileakage Vdd


Types of Power Consumption

Dynamic power

During the switching of transistors

Depends on the clock frequency and switching activity

Consists of switching power and internal power.

Static Power

Transistor leakage current that flows whenever power is applied to the device

Independent of the clock frequency or switching activity.


PMOS

NMOS

VoutCdrain+

Cinterconnect+Cinput

Vdd

A

BCload

Dynamic power( Pswitching =CL Vdd

2 fclk )

capacitance

1) Output node capacitance of the logic gate: due to the drain

diffusion region.

2) Total interconnects capacitance: has higher effect as technology

node shrinks.

3) Input node capacitance of the driven gate: due to the gate

oxide capacitance.

Input voltage

Internal node voltage swing can be only Vi which can be smaller than

the full voltage swing of Vdd leading to the partial voltage swing.

Frequency

F increases then power automatically increases.

Fig 1:cmos inverter


(Pshort-circuit =Vdd Isc )

To get equal rise/fall balance transistor sizing

2.5V

2.5V

0V

Vin

Vout

Vthn

Vdd- |Vthp|

More rise/fall time more short circuitLower threshold voltage more short

circuit

Vthn<Vin<Vdd-|Vthp|

NMOScurve

PMOScurve

Vdd<Vthn+|Vthp|

Both PMOS and NMOS are conducting

for a short duration of time

short between supply power and ground

Fig 2:shorte circuit Fig 3:Trance analysis of cmos


Static power(Pleakage =Ileakage Vdd)

1). Diode reverse bias–I1 2). Sub threshold current – I2

Fig 4:Diode reverse bias

3). Gate induced drain leakage – I3 4).Gate oxide tunneling – I4

Vgs <~ Vth carrier diffusion causes sub threshold leakage.

Vgs <=0 accumulation mode.0< Vgs << Vth depletion mode.Vgs ~ Vth weak inversion.Vgs > Vth Inversion.

Higher supply voltage.

thinner oxide.

increase in Vdb and Vdg.

high electric field across a thin gate

oxide.Direct tunneling through the

silicon oxide layer if it is less than

3–4 nm thick. Fig 5:leakage currents


Low power design techniques

Table 1:low power design techniques


× Clock tree consume more than 50 % of dynamic power

Used for synchronous circuits

Clock gating works by taking the enable conditions attached to registers, and uses them to

gate the clocks.

Save significant die area as well as power.

Clock gating logic is generally in the form of "integrated clock gating" (ICG) cells.

Logic added into the design

Coded into the RTL code as enable conditions--clock gating logic (fine grain clock gating).

Inserted into the design manually by the RTL designers (typically as module level clock gating)

Semi-automatically inserted into the RTL by (automated clock gating tools)

Clock gating


Two types of clock gating styles

Latch-based clock gating Latch-free clock

Uses a simple AND or OR gate

Glitches are inevitable

Less used

D Q

CK

D Q

CK

En

clk

Gatedclock

Level-sensitive latch

Less glitch

Easy adoption by EDA tools

Fig 6:Latch-based clock gating Fig 6:Latch-free clock gating


Multi Vdd (Voltage)

Different but fixed voltage is applied to different blocks or subsystems of the SoC design.

SVS

When high speed of operation is required voltage is increased

Voltage as well as frequency is dynamically varied as per the different working modes of the design

DVFS AVS

Voltage areas with variable VDD.Voltage is controlled using a control loop.


CMOS LogicLow/Nom Vt

Vdd

standby

standby

HighVt

HighVt

Prevents leakagein standby mode

Prevents leakagein standby mode

High speedoperation

Use Hvt and Lvt cells

Called as “sleep transistor”

Multiple threshold

Extensively used inPower gating

Fig 6:Sleep transistor


VddVbias1

Vbias2

Vdd

variable substrate bias voltage from a control circuitry to

vary threshold voltage

General design:

substrate is tied to power

or ground

Pros

Considerable power reduction

Negligible area overhead

Cons

Requires either twin well or triple well technology to achieve different substrate bias

voltage levels at different parts of the IC

Variable threshold

Fig 7:substrate bias voltage in cmos


Power gating

Circuit blocks that are not in use are temporarily turned off

Affects design architecture more compared to the clock gating

It increases time delays as power gated modes have to be safely entered and exited

CMOSlogic

High Vt NMOSFooter switch

Power switchingcontrol signal

A power switch (header or footer) is added to supply rails to

shut-down logic(MTCMOS switches)

CMOSlogic

High Vt PMOSHeader switchPower switching

control signal

Fig 8:power gating by sleep transistor


Add a sleep transistor to every cell

Switching transistor as a part of the

standard cell logic

~10X leakage reduction

Fine-grain power gating Coarse-grain power gating

Less sensitive to PVT variation Introduces less IR-drop variation Imposes a smaller area overhead

Ring based methodology Column based methodology

Fig 9:Fine grain power gating Fig 10:Coarse grain power gating


Low-power design requires new cells with multiple power pinsAdditional modeling information in “.lib” is required to

automatically handle these cells

Fig 11:switces for reducing the power


Table 2:trade-off analysis of power reducing techniques

Trade –off for low power techniques


Future low power strategy…?

Asynchronous Design - Solution to Dynamic Power?

› Let’s get rid of the clock

› Micro pipeline: A Simple Asynchronous Design Methodology

Is Hi-k sufficient for 22nm and 16nm?

Whether this type of transistor structure (hi-k, metal gate) will continue to scale to the

next two generations—22 nm and 16 nm—is a question for the future.

Is there a simple, coherent power strategy that unifies the best of DVFS, power gating,

asynchronous ?

How do we represent and verify very complex power intent such as asynchronous ?

Carbon nano tubes…….?

Spintronics…..?


conclusion

Power is becoming the restraining factor in further miniaturization and

scaling. Various methodologies available but still a lot of scope for improvement.

Need for developing of infrastructure. Combining of discrete power saving

techniques into a single integrated system.


References

[1] Keshava Murali, “Low power techniques”, SNUG 2007 and 2008

presentations on low power, Retrieved on 17 oct 2011.

[2] Jan.M.Rabey and Massoud Pedram Kluwer academic publishers, “low

power design methodologies”, Retrieved on 17 oct 2011.


Thank you…….

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low power techniques in vlsi