Low Power Cmos Ckt Basic Slides1

7/30/2019 Low Power Cmos Ckt Basic Slides1

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Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan

Massachusetts Institute of Technology


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Basics of Low Power Circuit and Logic Design Anantha Chandrakasan 1997 2

High Performance Processors

75 80 85 90 95Year

0

10

20

30

Power(Watt)

Microprocessor Power

(source ISSCC)


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Portable Devices

(40+ lbs)

Battery

Radio transceiver

Modem

Voice I/O

Pen Input

Text/Graphics Processing

Text/Graphics display

Video decompression

Full-motion video display

Portable Functions

Required

How to get 8 hours of operation ???


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5/61Basics of Low Power Circuit and Logic Design Anantha Chandrakasan 1997 5

Where Does Power Go in CMOS?

Short-circuit or direct-path currents

Leakage currents

- Charging and discharging parasitic capacitors

- Sub-threshold conduction

- Reverse bias diode leakage

Dynamic or switching currents

- Direct path between supply rails during switching

Static currents


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Dynamic Power of a CMOS Gate

Vdd

Vout

isupply

CL

E0->1 = CLVdd2

PMOS

NETWORK

NMOS

A1

AN

NETWORK

E0 1

P t( )dt

0

T

Vdd isupply t( )dt

0

T

Vdd CLdVout0

Vdd

CL Vdd2= = = =

Ecap

Pcap

t( )dt

0

T

Vouticap t( )dt

0

T

CLVoutdVout0

Vdd

1

2---C

LV

dd

2= = = =


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Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd-Vt

E0 1

CL

Vdd

Vdd

Vt

( )=

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)


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Physical Capacitance of an Inverter

0.8 1.0 1.2 1.4 1.6 1.80.0

10.0

20.0

30.0

40.0

50.0

Cgate

Cjunction

Cjunction + Cgate

Cap

acitance,f

F

2.0

VDD

Important to account for capacitive non-linearities

in power estimation


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Node Capacitance is a Function of Voltage

0.8 0.9 1.0 1.1 1.2 1.3 1.450

60

70

80

90

100

110

S

witchedCapacitance

,fF

C2MOS

TSPCR

1.5

LCLR

VDD, V


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Node Transition Activity and Power

Consider switching a CMOS gate forNclock cycles

EN

CL

Vdd

2 n N( )=

n(N): the number of 0->1 transition inNclock cycles

EN: the energy consumed forNclock cycles

Pavg

N lim EN

N-------- f

clk= n N( )

N------------

N lim C

LV

dd 2 f

clk=

0 1

n N( )

N

------------

N

lim=

Pavg

= 0 1

CL

Vdd

2 fclk


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Factors Affecting Transition Activity, 0->1

Dynamic or timing dependent component

Type of Logic Function (NOR vs. XOR)

Static component (does not account for timing)

Circuit Topology

Type of Logic Style (Static vs. Dynamic)

Signal Statistics

Inter-signal Correlations

Signal Statistics and Correlations


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Type of Logic Function: NOR vs. XOR

A B Out

0 0 1

0 1 0

1 0 01 1 0

Truth Table of a 2 input NOR gate

Example: Static 2 Input NOR Gate

Assume:

p(A=1) = 1/2p(B=1) = 1/2

p(Out=1) = 1/4

p(01)

= 3/4 1/4 = 3/16

Then:

=p(Out=0).p(Out=1)

0->1 = 3/16


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Type of Logic Function: NOR vs. XOR

A B Out

0 0 0

0 1 1

1 0 11 1 0

Truth Table of a 2 input XOR gate

Example: Static 2 Input XOR Gate

Assume:

p(A=1) = 1/2p(B=1) = 1/2

p(Out=1) = 1/2

p(01)

= 1/2 1/2 = 1/4

Then:

=p(Out=0).p(Out=1)

0->1 = 1/4


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Type of Logic Style: Static vs. Dynamic

Vdd

CL

CLK

A B

CL

A

B

A B

Vdd

CLK

STATIC NOR DYNAMIC NOR

0->1 = 3/16 0 1

N0

2

N-------

3

4---= =

Power is only dissipated when Out=0!


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Another Logic Style: Dynamic DCVSL

Vdd

I

I

Vdd

IN

INB

OUTBOUT

Guaranteed transition for every operation!

0->1 = 1


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Influence of Signal Statistics on 0->1

0

0.2

0.4

0.6

0.8

PA

0

0.2

0.4

0.6

0.8

1

PB

0

.1

2

0

0.2

0.4

0.6

0.8

PA

0

0.2

0.4

0.6

0.8

1

PB

0

.1

2

B

B

A

ACL

pb

0

1

0

1pa

p0->1

0->1 is a strong function of signal statistics

p1 = (1-pa) (1-pb)

p0->1 =p0p1 = (1-(1-pa) (1-pb)) (1-pa) (1-pb)


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Inter-signal Correlations

(a) Logic circuit without

reconvergent fanout

(b) Logic circuit with

reconvergent fanout

A

B

Z

CA

Z

C

B

p0->1 = (1-papb)papb = 3/16

p0->1 = 0

pZ=p(C=1|B=1) p(B=1)

Need to use conditional probabilities to modelinter-signal correlations!

CAD tools required for such analysis


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0 5 100.0

2.0

4.0

Time, ns

SumOu

tputVoltage,Volts

Cin

S15

S10

6

5

4

3

2S1

Add0 Add1 Add2 Add14 Add15

S0 S1 S2 S14 S15

Cin

0->1 can be > 1 due to glitching!

Dynamic or Glitching Activity in CMOS


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Glitch Reduction Using Balanced Paths

A7

F

A6A5A4A3A2A1

A0

A0

A1

A2A3

A4A5

A6

A7

F

Ripple

Lookahead


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Comparison of Adder Topologies

from [Callaway92]

16 bit 32 bit 64 bit

Ripple Carry 3.09 0.81 0.27

Carry Lookahead 10.0 3.54 1.76Carry Bypass 5.45 2.39 0.99

Carry Select 4.44 2.08 1.00

Conditional Sum 3.82 1.23 0.42

Power-Delay-Product-1

Logic Transition Histogram

(VLSI Signal Processing, V)


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Glitching at the Datapath Level

Tree vs. Chain

A B

C

D+ +

+

A B C D+

++

+

(A + B) + C + D(A + B) + (C + D)

Can be reduced by reducing the logic depth and balancing

ChainTreeInputs

4

8

1.45

2.5

1

1

Normalized # of Transitions

signal paths


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Short-circuit Component of Power

Vin Vout

CL

Vdd

IVDD(mA)

0.15

0.10

0.05

Vin (V)

5.04.03.02.01.00.0


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Short-Circuit Current vs. Load Capacitance

from [Veendrick84]

(IEEE Journal of Solid-State Circuits, August 1984)


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Minimizing Short-circuit Power

Keep the input and output rise/fall times the same(< 10% of Total Consumption)

IfVdd

0ON

standby

Techniques for Burst Mode Computation

Needs large body factors - large well capacitances

Triple well process needed

from [Seta95] (ISSCC 1995)

SOI ith A ti S b t t (SOIAS)


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SOI with Active Substrate (SOIAS)

n+ n+p np+ p+

p+ n+i-poly

tfoxt

tsi

box

Loverlap

Backgate Control EnablesDynamically Varying Threshold Voltages

from [Yang95]

NMOS D i Ch t i ti


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NMOS Device Characteristics

-0.2 0 0.2 0.4 0.6 0.8 1

Vgf (V)

10-13

10-12

10-11

10-10

10-910

-8

10-7

10-6

10-510

-4

10-3

10-2

Id(mA/um)

0

0.01

0.02

0.03

Id(mA/um)

~ 4 Dec

1.8x

VDS=1.0 Vtbox=100 nmtfox=9 nm

tsi=4.5 nmLeff=0.44 um

Vt=0.448 V (Vgb=0.0 V)Vt=0.184 V (Vgb=3 V)

Ri O ill t Ch t i ti


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Ring Oscillator Characteristics

Varied VTPonlyVTN= 0.512V

Varied VTNonlyVTP= - 0.2V

Processor speed is adjustable on demand

0.0 0.1 0.2 0.3 0.4 0.5 0.66

8

10

12

0.7RingOscil

latorFrequency(MHz)

Backgate Controlled Variable |VT| (V)

Architectural Model & Activity Parameters for SOIAS


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Architectural Model & Activity Parameters for SOIAS

ADD ON ADD ONADD OFF

fga= Module Activity Factor

CLK

ADD

CLK

BACKGATELOW VT HIGH VT LOW VT

bga= Backgate Switching Activity

Add15

0

0.2

0.4

0.6

0.8PA

0

0.2

0.4

0.6

0.8

1

PB

0

.2

4

0

0.2

0.4

0.6

0.8PA

0

0.2

0.4

0.6

0.8

1

PB

0

.2

4

1x

CLK ADD CLK BACKGATE

Add1

01pa

0 pb

Circuit Node Transition Activity

ab

x

G i A hit t M d l f All T h l i


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Generic Architecture Model for All Technologies

Technology

Leakage Control

Mechanism(hence affecting bga)

Multiple Threshold Technology Switching the High VT

devices ON/OFF

Substrate Bias Control Controlling theSubstrate Voltages

Silicon On Insulator Active Substrate Switching the

Backgate Voltage

Hierarchy of Profilers and Statistical Models

Required for Virtual Prototyping

Energy Estimation Models for SOI and SOIAS


46/61


Energy Estimation Models for SOI and SOIAS

ESOI= fga CfgVdd2

ESOIAS= fga CfgVdd2

fga = Module Activity Factor

bga = Backgate Switching Activity

= Node Transition Activity Factor

+ fga Ileak_lowVTVddTcycle+ (1-fga)Ileak_highVTVddTcycle

+ bgaCbgVbg2

+ Ileak_lowVT

Vdd

Tcycle

Architectural Profiling to Determine fga and bga


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Architectural Profiling to Determine fgaand bga

Table 1. SPEC benchmark espresso

Number fga bga

Total Instructions 900158847 - -

Additions 543616709 0.6039 0.1954

Shifts 57000715 0.0633 0.0541

Multiplications 172883 0.0002 0.0002

Table 2. SPEC benchmark Li

Number fga bga

Total Instructions 1737729538 - -Total Additions 661236960 0.6023 0.2233

Total Shifts 52224367 0.0087 0.0086


Table 3. Data Encryption (IDEA)

Number fga bga

Total Instructions 2125 - -

Additions 1250 0.5882 0.2635

Shifts 186 0.0875 0.0753


SOI vs SOIAS Technology Evaluation


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SOI vs. SOIAS Technology Evaluation

43.5

32.5

21.5

10.5 4

3.5

3

2.5

2

1.5

1

2

1

0

1

o

*

.

o

.

*

Adder

log(ba

ck-gateacti

vity

factor)

*

*

Shifter

Mult.

0.0

-0.5

-1.0

0.5

log(front-gateactivityfactor)

l

og(ESOIAS/E

SOI)

Transistor Sizing for Low-Power


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Transistor Sizing for Low-Power

Minimum sized devices are usually optimal for low-power

Small W/Ls

Large W/Ls

Higher Voltage

Lower Voltage

Lower Capacitance

Higher Capacitance

Larger sized devices are useful only when interconnect dominated

Transistor Sizing for Fixed Throughput


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Transistor Sizing for Fixed Throughput

= 0

adder

0.5

0.7

1.0

1.5

2

3

45

7

10

1 3 10

= 0.5

= 1

= 1.5

= 2

W/L

NORMALIZEDENER

GY

CP = Cwiring + CDF

Cg = W/L CMINI W/L CMIN

CMIN = Minimum sized gate (W/L=1)

W /L after sizing

HIGH PERFORMANCE

W/L >> CP / (K CMIN)

LOW POWER

W/L = 2 CP / (K CMIN)

(if CP K CMIN)

W/L = 1ELSE

= CP / (K CMIN)

from [Chandrakasan92]

(IEEE JSSC, 1992)

Capacitance Breakdown


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Capacitance Breakdown

MODULE LEVEL

DATAPATH LEVEL

MODULE GATE DIFFUSION INTERCONNECT

ADDER (Conventional Static) 30% 45% 25%

ADDER (Carry Select) 37% 31% 32%

TSPC COUNTER 32% 26% 36%

LOG SHIFTER (8 bit shift by 4) 15% 42% 43%

COMPARATOR 33% 38% 29%

MODULE GATE DIFFUSION INTERCONNECT

ADDER CHAIN ( 7 adders ) 38% 38% 24%

WAVE DIGITAL FILTER 31% 29% 40%

ADDRESS GENERATION (STD CELL) 56% 24% 20%

VIDEO SYNC GENERATOR

(STD CELL)

45% 25% 30%

Choice of Logic Style


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A

B

A

B

B

CIN CIN

B

VDD VDDPRE

CO CO

A

CIN

A

CIN

CIN

B B

CIN

VDD VDDPRE

SUMSUMBB

CONVENTIONAL CMOS Adder

CPL AdderDCVSL Adder

GND

AA

BB

P

CINGEN

CIN PROP

GEN

VDDGND

A

B

A B

VDD

GEN

CINSUM

CIN

CIN

P

P

B

P

B

A

P

A

B

COUT

GND

CIN

PGEN

CIN P

GEN

VDD

COUT

OPTIMIZED static Adder

A

A

B

B

C C

GND

VDD

A

A

B

B

A

B

A

B

A

B

A

B

Sum

B

C

AB

A

VDD

A

B

A

B

VDD

CoutA B C

A

A

B B

C

C

Sum Sum

ACC

B

CoutCout

B

A

A

A A



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Power-delay product improves as voltage decreases.

The best logic style minimizes power-delay for a given

delay constraint.

3

5

7

10

15

20

30

50

70

100

150

200

10 30 100

8-bit adders in 2.0m

POWER-

DELAYPRODUC

T(pJ)

DELAY (ns)

Decreasing Vdd

CPL - LOW Vt

Optimized

Standard Cell

CSA

DCVSL

ConventionalStatic

Static

Reducing the Energy/Operation at a Fixed Vdd


54/61



oo 6/2 3/9

7/2

9/2

4/2

< >

o

Vdd(=1.5V)

Ceff= 5pF

Vin

Vout

HeavilyLoadedBit-line

0 20 40 60 80 1000

0.5

1.0

1.5

v(line)

v(out)v(out)v()

t (ns)

Volts

SignalAmplification

M1 M2

M3M4

M5

V(out)

Reduced Signal Swing Example: FIFO Memory

Power Reduction Over Rail-to-Rail Swing = Vdd/(Vdd-Vt)



55/61


R

Ctr

E = (RC/tr)CV2 (for tr>> RC)

Applying slow input slopes reduces E below CV2

Useful for driving large capacitors (Buffers)

Power reduction > 4 for pad drivers (1 MHz) ISI

ADIABATIC CHARGING


Example: Stepwise Adiabatic Driver


56/61


p p

CL

V1 1

2

N

V2

VN

0

Estep Q Vavg CL

Vdd

N----------

Vdd

2N----------

1

2--- C

LV

dd2

N2---------------------------------= = =

Etotal

N

1

2--- C

LV

dd2

N2

---------------------------------E

conventional

N----------------------------------------= =

RC charging steps

from [Svensson94]

Vi = (i/N) V

(IEEE Symposium on Low Power Design, 1994)

Activity Driven Logic Level Power Down


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y g

MSBREG

REG

CLK

COMPARATOR

forbits

0->N-2

MSBA[N-1]

B[N-1]

COMPARATOR

for

bits 0->N-2

REG

forbits

0->N-2

GATED_CLK

A >B

A[N-2:0]

B[N-2:0]

A >BREG

CLK

MODIFIED REGISTER

COMBINATIONAL

LOGIC

CONDITIONALLY

SWITCHED

BLOCK

50% reduction possible for random inputs

from [Alidina94](1994International Workshop on Low-power Design)

Activity Reduction in Shift Registers


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y g

fCLK

Data In Data Out

fCLK/2

Data In Data Out

N Length Shift Register

N/2 Length Shift Register

Pserial= NCregV2fclk

Pparallel= 2 x (N/2 CregV2fclk/2) + Poverhead

Shift Register Power for Various Lengths


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0 8 16 24 32

Degree of Parallelism

0.0

0.2

0.4

0.6

0.8

1.0

N

ormalizedP

owerDissip

ation

32-bit

64-bit

128-bit

256-bit

Summary


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Power dissipation is a prime design constraint for

portable systems

Low Power design requires optimization at all Levels

Sources of power dissipation have been analyzed

Technology, circuit, and logic design techniques have

been described


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Documents

Low Power Cmos Ckt Basic Slides1