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TSI Semiconductors - 2018 TSI Semiconductors - 2018 INNOVATION @ SCALE
Leveraging 0.18um Foundry Technologies with Heterogeneous Integration of Novel Devices in a
ITAR/Trusted Foundry
The 16th International System-on-Chip (SoC) Conference, Exhibit, & Workshops
October 2018, Irvine, California www.SoCconference.com
Wilbur Catabay
Jim Hunter, Alex Payne, Lars Eng
TSI Semiconductors - 2018 2
Outline
• Overview of TSI Semiconductors Specialty Foundry
• Why Monolithic (Heterogeneous) Integration of CMOS with Novel Devices?
• Case Study – Silicon Light Machines iGLV Technology
‒ Leveraging 0.18um CMOS technology
‒ Validate CMOS Device stability vs. MEMS processing temperatures
‒ Process Integration of MEMS with CMOS
‒ Lithography stitching to form large MEMS Devices
‒ Commercialization from “Lab to Fab”
• Summary
TSI Semiconductors - 2018 3
TSI Semiconductors at a Glance
Business Segments
Automotive
Industrial & Power Management
Mil-Aero
IOT
Strong customer technology collaboration with a flexible model for Foundry and Development with novel materials
World Class Foundry
Over 30 years of continuous operations
24/7 Operations, Clean room 150,000 Sq/ft
Logic, High Voltage, Mix Signal, Analog, RF
Novel Materials Integration
IP Secure Environment
ISO & Automotive Certification
DMEA Trusted & ITAR
Globally Connected
Roseville, California, USA
Foundry, Custom Foundry & Development
Capacity of 10,000 wafers per month
Clean room capacity at 50%
Customers Technology Revenues
N. America Medical $50B
N. America Industrial $25B
Japan Automotive $10B
Japan Industrial $26B
N. America Memory $19B
Customers Technology Revenues
N. America Consumer Start-up
N. America ATE Start-up
Asia MEMS Start-up
N. America MEMS Start-up
N. America Sensors Start-up
TSI Semiconductors - 2018 4
Why Monolithic Integration?
• MEMS Sensors typically control or sense physical, chemical, and optical characteristics by way of electrical measurements that interface with the environment or people
• Most Sensors needs a dedicated controller or ASIC to drive the signal, communications and storage of what it’s trying to achieve
• Integrating both the CMOS and MEMS Device has its advantages:
o Small Form Factor: important for today’s mobile devices
o Increased Performance: high density, less parasitic
o Cost savings at the system level e.g. reduced component count
• Disadvantages:
o Area ratio of the Sensor versus CMOS
o Potential Yield mis-match resulting to expensive chips
TSI Semiconductors - 2018 5
MEMS Integration Types
• Two approaches for MEMS integration:
o Multi-chip packaging solutions by way of wire bond
o Monolithic integration by way of single chip
• Case Study – Silicon Light Machines iGLV Technology
o Monolithic Integration of TSI 0.18um CMOS with unique MEMS Device
o SLM iGLV – integrated Grating Light Valve (CMOS integrated with MEMS)
PCB
MEMS
Die
Driver
Die
Driver
Die
Multi-chip Module
CMOS
MEMS
Die
Interconnect
Monolithic Integration
10mm 100um
TSI Semiconductors - 2018 6
Silicon Light Machines Case Study
• Silicon Light Machines is building their next-generation spatial light modulator monolithically on TSI’s 0.18um CMOS platform
o 8192-channel MEMS light modulator with 20V x 250kHz drive capability
o 37 Gb/s data rate to chip
o Used in high-throughput laser-based direct-write (mask-less) lithography tools
o Direct integration of MEMS with CMOS required due to tight channel pitch (5um)
o MEMS fabricated on top of final CMOS metal (i.e. no modification to CMOS flow)
o Impact of MEMS thermal cycles on CMOS devices has been characterized
o Large device size (>40mm) – requires image stitching
• Courtesy of Silicon Light Machines
o Lars Eng, CEO
o Alex Payne, Chief Scientist
o Jim Hunter, Director of Process Technology
TSI Semiconductors - 2018 7
SLM – integrated Grating Light ValveTM
Spatial Light Modulation based on Diffraction
SLM iGLV Chip Package Die Size 43mm x 10mm
TSI Semiconductors - 2018 8
Outline
• Overview of TSI Semiconductors Specialty Foundry
• Why Monolithic (Heterogeneous) Integration of CMOS with Novel Devices?
• Case Study – Silicon Light Machines iGLV Technology
‒ Leveraging 0.18um CMOS technology
‒ Validate CMOS Device stability vs. MEMS processing temperatures
‒ Process Integration of MEMS with CMOS
‒ Lithography stitching to form large MEMS Devices
‒ Commercialization from “Lab to Fab”
• Summary
TSI Semiconductors - 2018 9
TSI Semiconductors Technology Platforms
Images may be subject to copyright
Automotive
Medical
Lighting
Telecom /Networking
Mil-Aero
Industrial
0.18µ HV Vgs=1.8V, 3.3V, 5V
Vgs = 20V Vds=12V, 20V, 50V, 120V
0.18µ Logic Vgs/Vds=1.8V,
3.3V, 5V
0.8µ UHV up to 700V
Low Voltage 1.8V, 3.3V, 5V - 20V
Display, Optics, Drivers, Medical, Automotive, Wireless Charging
Medium Voltage 12V - 120V
Automotive, Industrial, Medical, Networks, Lighting
Ultra High Voltage Up to 700V
LED, IGBT, MOSFET
SMART Homes
Appliances
Cell Phones Aerospace
TSI Semiconductors - 2018 10
CMOS High Voltage Transistor Comparison
• TSI’s HV NMOS transistor is 4X smaller than current device (Viper)
o Compact, 20V high voltage transistor fits in 9.9um channel width
o 20V HV NFET used in current Viper is four time larger: 38.8um
‒ It required a unique 4X pixel hierarchy which can be avoided with TSI process
Viper (current device) CMOS (0.35um)
HVNMOS_20
Habu (next generation) TSI cmhv7sf CMOS (0.18um)
nfet20mh
39
.8 u
m 9.9
um
TSI Semiconductors - 2018 11
Module Electronics 0.35um versus TSI 0.18um
• SLM has the ability to minimize the PCB board level components by designing to a 0.18um technology node from previous 0.35um node
TSI Semiconductors - 2018 12
0.18um iGLV – High Level CMOS and MEMs
Circu
itry
TSI Semiconductors - 2018 13
Outline
• Overview of TSI Semiconductors Specialty Foundry
• Why Monolithic (Heterogeneous) Integration of CMOS with Novel Devices?
• Case Study – Silicon Light Machines iGLV Technology
‒ Leveraging 0.18um CMOS technology
‒ Validate CMOS Device stability vs. MEMS processing temperatures
‒ Process Integration of MEMS with CMOS
‒ Lithography stitching to form large MEMS Devices
‒ Commercialization from “Lab to Fab”
• Summary
TSI Semiconductors - 2018 14
Impact of MEMS thermal cycles on CMOS Devices
• MEMS films are furnace-based with long processing times
• Utilized 0.18um test vehicle to study the impact of MEMS thermal cycles on CMOS devices performance
o 1.8V FETs, 5V FETS, high voltage FETs, and resistors
• Zero to 2% shifts for all device parameters after simulated MEMS thermal cycles
• Integration of MEMS films does not adversely shift/impact critical device parameters
Standard
Post MEMS
Thermal Cycles
TSI Semiconductors - 2018 15
Impact of MEMS thermal cycles on CMOS Devices • No significant shifts for 1.8V, 5V devices, and resistors after MEMS thermal cycles
Devices Parameters Units % Shift post MEMS thermal stressing
Wafer #1 Wafer #2
1.8V Isolated DN NFET
[5 x 0.18]
VTSat [V] 0% 0%
Gm gm -2% 1%
Ioff Log [A] 0% 0%
Gate Leakage Log [A] 2% 0%
IDSat uA/um 0% 0%
1.8V Isolated DN PFET
[5 x 0.18]
VTSat [V] -2% -2%
Gm gm 2% 3%
Ioff Log [A] 0% -1%
Gate Leakage Log [A] 2% 1%
IDSat uA/um 2% 2%
5V NFET
[5 x 5]
VTLin [V] 0% 0%
Gm gm 0% 0%
Ioff Log [A] -1% 0%
Gate Leakage Log [A] -2% -3%
IDSat uA/um 0% 0%
5V PFET
[5 x 5]
VTLin [V] -1% -1%
Gm gm 2% 2%
Ioff Log [A] 1% -1%
Gate Leakage Log [A] 1% 2%
IDSat uA/um 2% 2%
Process Monitors
Non Silicided N Diff Rs ohm/sq 0% 0%
Non Silicided N Poly Rs ohm/sq 4% 4%
Non Silicided P Diff Rs ohm/sq 0% 0%
Non Silicided P Poly Rs ohm/sq 1% 1%
RP Poly Rs ohm/sq 1% 0%
RR Poly Rs ohm/sq -2% -2%
N+Poly Sheet Resistance ohm/sq 0% 0%
P+Poly Sheet Resistance ohm/sq 0% 0%
NDIff Sheet Resistance ohm/sq 0% 0%
PDIff Sheet Resistance ohm/sq 0% 0%
TSI Semiconductors - 2018 16
Impact of MEMS thermal cycles on CMOS Devices
• No significant shift in high voltage devices after MEMS thermal cycles
Devices Parameters Units % Shift post MEMS thermal stressing
Wafer #1 Wafer #2
1.8Vg / 50Vd NFET
VTLin [V] 0% 0%
RON ohms 0% 2%
IDSat uA/um 0% 0%
BVDSS [V] 0% 0%
1.8Vg / 50Vd PFET
VTLin [V] -1% -1%
RON ohms -2% -2%
IDSat uA/um 2% 3%
BVDSS [V] 0% 0%
5.0Vg / 50Vd NFET
VTLin [V] 0% 0%
RON ohms 0% 1%
IDSat uA/um 0% -1%
BVDSS [V] 0% 0%
5.0Vg / 50Vd PFET
VTLin [V] -1% -1%
RON ohms -2% -2%
IDSat uA/um 2% 2%
BVDSS [V] 0% 0%
20 Vg / 20 Vd NFET
VTLin [V] 0% 0%
RON ohms -1% -1%
IDSat uA/um 0% 0%
BVDSS [V] 0% 0%
20 Vg / 20 Vd PFET
VTLin [V] -1% -1%
RON ohms -2% -3%
IDSat uA/um 1% 1%
BVDSS [V] 0% 0%
TSI Semiconductors - 2018 17
Outline
• Overview of TSI Semiconductors Specialty Foundry
• Why Monolithic (Heterogeneous) Integration of CMOS with Novel Devices?
• Case Study – Silicon Light Machines iGLV Technology
‒ Leveraging 0.18um CMOS technology
‒ Validate CMOS Device stability vs. MEMS processing temperatures
‒ Process Integration of MEMS with CMOS
‒ Lithography stitching to form large MEMS Devices
‒ Commercialization from “Lab to Fab”
• Summary
TSI Semiconductors - 2018 18
Integration of Novel Devices with 3rd party Foundry’s
Interconnect Solutions
CMP
Lithography Materials
Electrical
Incoming Foundry Wafers
Device Products
Customers Foundry Technology
G, H, I TSI Semiconductors MEMS, Life Sciences
A TSMC, SMIC Memory
B SilTerra, Skywater Memory
C TSMC, UMC Life Sciences
D Tower Jazz MEMS
E Skywater Life Sciences
F IBM Memory
Enabling interconnect to CMOS Foundry wafers to integrate novel devices; enables secure split processing
Build Devices on CMOS
SiC
SiC
SiC
SiC
M1 Cu
M2 Cu
M1
Via1
M2
HDP PSG W Plug
Low-k
Low-k
Low-k
SiC
Via2 W Plug
Via2
M1
Via1
M2
Via2 USG
Via2 Via2 AlCu Via2
Cu Interconnect Al Interconnect
Interconnect CMOS to Novel Devices
TSI Semiconductors - 2018 19
• MEMS Grating Light Modulator is built on top of last CMOS metal layer requiring planar surface and good electrical contact
• Customized Top Metal and Via modules for connection of CMOS with MEMS
o Designed a CMP test vehicle to determine if top metal fill is beneficial under Ribbon arrays
o Developed tungsten plug in dual dielectric stack over top metal as electrical connection to MEMS modulator
Process Integration of MEMS with CMOS
MEMS Grating Light Modulator
TSI 0.18um CMOS
W-plug
Top Metal
Dielectric
Customized Top Metal and Via Plug modules
Dielectric
TSI Semiconductors - 2018 20
CMP Process Challenges
20
• Incoming process requirements prior to MEMS process integration
Planar surface below the “iGLV Ribbons”
Optically perfect surfaces required
• Mitigations to reduce Dishing
Dummy Fill in open areas of Dielectric and large Metal lines
Optimize Pad and Slurry conditions
Customize CMP head by incorporating selective pressure zones
Oxide Dishing
Top Metal
Top Metal
Ideal CMP Planarity Post CMP Oxide Dishing
TSI Semiconductors - 2018 21
CMP Test Mask – Tiling vs. No Tiling
21
4 um
1 um
• MEMS can be built directly over metallization if necessary
• Last metal layer (ML) is a ~8500Å aluminum CMOS metallization layer
• Minimum CD of ML layer is 1.0um gap between features
• Test mask compares use of ML minimum feature tiling vs. no tiling in large MEMS area
ML tiling No ML tiling
ML tiling No ML tiling
CMOS last metal (ML)
TSI Semiconductors - 2018 22
CMP Test Mask Results
22
• Oxide uniformity across MEMS area (between ML features) with no metal tiling less than 7 nm
19500
19700
19900
20100
20300
20500
20700
20900
21100
21300
21500
Edge 1 Center Edge 2
Res
idu
al O
xid
e, P
ost
CM
P
CMP Study ResultsOxide Thickness Across MEMS Array Location
Site 1
Site 2
Site 3
Site 4
Site 5ML – Last Feature Edge
Oxide surface
TSI Semiconductors - 2018 23
Outline
• Overview of TSI Semiconductors Specialty Foundry
• Why Monolithic (Heterogeneous) Integration of CMOS with Novel Devices?
• Case Study – Silicon Light Machines iGLV Technology
‒ Leveraging 0.18um CMOS technology
‒ Validate CMOS Device stability vs. MEMS processing temperatures
‒ Process Integration of MEMS with CMOS
‒ Lithography stitching to form large MEMS Devices
‒ Commercialization from “Lab to Fab”
• Summary
TSI Semiconductors - 2018 24
Lithography Stitching using I-line Stepper
• Two-reticle stitching was completed using I-line stepper to achieve final die size of 43mm x 10mm.
• Litho test vehicle was designed to evaluate overlay alignment performance
Within wafer and wafer-to-wafer
Across different I-line steppers
Lens Distortion and reticle rotation
• Overlay performance is well within customer’s specification limit (<100nm)
• Repeatable across lot and across steppers
Parameters Targets
MEMS die Size 43mm x 10mm
Max I-line Field Size
22mm x 22 mm
Stitch die size 21.5mm x 10mm
Overlay spec <100nm
Product Stitching Requirements Measurement shots across wafer Measurement sites across shot
Right Left
8 box-in-box measurement locations within a shot
TSI CONFIDENTIAL - © 2018
Examples of Good and Bad Stitching
Measurement sites across shot
Right Left
8 box-in-box measurement locations within a shot
Box-in-Box & Stitched Bar Overlay Example of Good Alignment
Stitch Bar
Box-in-Box & Stitched Bar Overlay Example of Bad Alignment
Box-in-Box
TSI Semiconductors - 2018
Misalignment in X (nm) Misalignment in X (nm)
Mis
alig
nm
ent
in (
nm
)
Mis
alig
nm
ent
in (
nm
)
Specification limits
Overlay measurements before rotation correction Overlay measurements with rotation correction
Improvements to Stitching Overlay
Overlay Performance Before After
Maximum Misalignment 83nm 43nm
Average Misalignment 31nm 14nm
TSI CONFIDENTIAL - © 2018
Outline
• Overview of TSI Semiconductors Specialty Foundry
• Why Monolithic (Heterogeneous) Integration of CMOS with Novel Devices?
• Case Study – Silicon Light Machines iGLV Technology
‒ Leveraging 0.18um CMOS technology
‒ Validate CMOS Device stability vs. MEMS processing temperatures
‒ Process Integration of MEMS with CMOS
‒ Lithography stitching to form large MEMS Devices
‒ Commercialization from “Lab to Fab”
• Summary
TSI Semiconductors - 2018 28
Early Definition
Functional Test Chips
Fully Functional Prototypes
Qualified Product Designs
Released Products to Market
Paper Study
Initial Integrated Flow
Validated Integrated Flow
Established Baseline
Frozen Baseline
Target Specification
Performance Specification
Product
Proof of Concept
Validated Process
Robust Process
Volume Process
Research Development Production
Product Outlier
Test Vehicle Qualification Vehicle Product Qualification Product Release
Co
mm
erc
ializ
atio
n R
amp
Y
ield
Imp
rove
me
nts
Commercialization Methodology
TSI Semiconductors - 2018 29
Application: Ultra-Violet Direct Imaging
• GLV modulator used SCREEN’s UV direct imaging tool advanced packaging
o 355nm exposure wavelength
o 2um minimum features on 0.5um placement grid
o 65 wafers per hour @ 100mJ/cm2 dose
• Kyoto city map shown printed onto wafer using DW3000
29
2um features
300mm wafer
TSI Semiconductors - 2018 30
Summary
• We are positioned to provide technology development services (TDCS) for innovative and disruptive architectural & materials development not found in typical Production Foundry Fabrications
• TSI is also positioned as a US-based Specialty Foundry with a technology platform supporting Industrial, Automotive, Mil-Aero, Life Sciences and Novel Disruptive Markets
• Customer IP is safe and secure – Trusted Accreditation, ITAR Registered
• We are based in Northern CA location, close to Silicon Valley eco-system
• Our services business model and collaboration enables faster and cost effective time to market for these technologies
TSI Semiconductors - 2018
Thank You
Wilbur Catabay TSI Semiconductors Corporation 1900 McCarthy Blvd Milpitas, CA 95035 ------------------------------ 7501 Foothills Blvd. Roseville, CA 95747 Tel: 408-218-9771 [email protected]