Lecture Physical Synthesis

8/3/2019 Lecture Physical Synthesis

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Physical Design and Synthesis

Li-Rong Zheng

Professor of Media Electronics, [email protected]


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OUTLINE

Introduction Floorplanning and placement

Routing

Elmore Delay

Clock distribution and power distribution

Summary


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Navigation ASIC Design in DSM Technology


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Some last synthesis steps...

Partition your design Save design in a suitable net list format

Insert scan-chains

Insert pads

Insert boundary scan and JTAG

Do place and route

Yet need some special circuits design analog/RF,

I/O and communication schemes, clock distribution,power distribution etc


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Physical Compiler Based Design Flow

Architechtural Specs, RTL coding & Simulation

Floorplanning

Physical Synthesis,Optimization &Scan Insertion

Formal Verification(RTL Vs Gates)

Pre-layout STA (basedon Steiner Route)

Timing OK?

Detailed Routing

Tape Out

Post-layout STA

Timing OK?

No

Formal Verification(Scan Inserted Netlist

VsCT Inserted Netlist)

Concept + Market Research

Yes

No

CT Insertion

Yes

Source: Advanced ASIC Chip

Synthesis. 2ndEd. Himanshu

Bhatnagar. Kluwer Academic

Publishers


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Clock Tree Routing

Scan-FF insertion

Place & Route Steps

Place

Route

DRC Check

LVS Check

Gate Netlist

RC Extraction

SDF

SPEF

Noise Analysis

Timing Analysis

Logic Design

Back annotate anddesign iteration


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Floorplanning...

Macroblock (IP)

Horizontal channel

Vertical channelClock spine

Standard cell area

Goal: Calculate the sizes of all blocks and assign them locations

Objectives: keep the highly connected blocks physically close to each other


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Pad Limitations...

Pad limited ASIC Core limited ASIC


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Cope with Pad Limitations

Pad limited ASIC Core limited ASIC

VddVss

I/O PadsVdd & Vss for core


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I/O Pad with ESD Protection

Diode

PAD

VDD

RD1

D2

X

C


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Power and Clock Planning

Power and GND Use separate metal layers for Power and GND

Global power/GND in top metal layers

Clock

Use separate metal layers for clock routing

Minimize Clock skew

C1 C2 C3

Ci+1

Ci= e

Load ratio for fastest switching

FO3


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Advanced On-Chip Power Distribution Schemes

Single Layer Grid Double Layer Mesh(with high speed signal

distribution)

Solid Planes(large decap, many vias)

Distributed at top-most metal layers (thicker, low R metals)

Power Ground Signal


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I/Os and Bonding Pads


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Placement Goals and Objectives

Guarantee that the routing algorithm cancomplete the routing step

Minimize the critical net delays

Make the chip as dense as possible

Minimize power dissipation

Minimize crosstalk between signals


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Routing steps

Global routing Detailed routing

Special routing

Circuit extraction and DRC


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Global Routing objectives

Minimize the total interconnect length Maximize the probability that the detailed router

can complete the routing

Minimize the critical path delay

Network of PLAs,

4 layers OTC

River PLA,

2 layers no additional routingStandard cell,

2 layers channel routing

Standard cell,

3 layers OTC


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Wiring Hierarchy

Passivation

Dielectric

Etch stoplayer

Dielectricdiffusion

barrier

Copperconductorwith metal

barrier liner

Pre-metaldielectric

Tungstencontact

plug

Source: SIA Roadmap 1999

Global

10 100 1,000 10,000 100,000

Length (mm)

NumberofNets(LogScale)

Pentium Pro

Pentium II

Pentium (MMX)

Pentium

Pentium II

Intermediate

Local


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Wire delay estimation

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

v

oltage

(V)

x= L/10

x = L/4

x = L/2

x= L

Diffused signalpropagation

Delay ~ L2

CN-1 CNC2

R1 R2

C1

Tr

Vin

RN-1 RN

The distributed RC-line


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Elmore delay model

A B

C

1 mm 2 mm

3 mm

3 mm

V1 V2

V3 V4

t4=R14C1+R24C2+R34C3+R44C4


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Elmore delay (ctd.)

t4=R14C1+R24C2+R34C3+R44C4

Rpd R1

C1

V1

R2

C2

V2

R3

C3

V3R4

C4

V4V0


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Elmore delay (ctd.)

Use the resistance that the nodes has in common Use the wire segment lengths to calculate the

capacitances

t4=R14C1+R24C2+R34C3+R44C4

R14=Rpd+R1 R24=Rpd+R1 (NB!!!)

R34=Rpd+R1+R3 R44=Rpd+R1+R3+R4


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Detailed Routing

Design rules - wire pitch Via-to-Via

Via-to-line

line-to-line

3l

4l

7l 6.5l 6l


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Detailed routing objectives

Minimize Total interconnect length and area

The number of layer changes (# of vias)

The delay of the critical path


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Special Routing

Clock Tree Routing Minimize Skew and reduce Jitter

Jitter caused by power supply noise

Power Routing

Calculate wire widths to carry the current

Depends on MTTF (Mean Time To Failure)

MTTF = AJ-2exp(-E/kT) > 10 years


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Setup- and Hold-times

tjitter thold

Data bus

Clock line

tjitter tsetup


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Clock skew factors

Clock skew is increased by number of buffers in the path

differences in length from clock source to end nodes

Clock skew is decreased by wider buffers in the path

phase compensators (PLLs, DLLs)


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Retiming Local Clock Skew

R1 R2 R3

33 1 ,5

5 4 7

What is the critical path of this circuit?


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Synchronization is the goal

The purpose of the clock is to provide

a way to synchronize the latches in the chip with the

external world

a way to synchronize the latches in the chip with eachother


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Classes of Synchronization

There are five classes of synchronization

Synchronous

Mesochronous

Plesiochronous

Periodic

Asynchronous

(More details in 2B1428: Advanced VLSI Design )


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General Clock Distribution Tree

ClockSource

Root Trunk

Branches

Leave

PLL

S t i Cl k Di t ib ti


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Symmetric Clock DistributionNetworks

a) H-tree b) X-tree


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Common Buffered Trees

a) Tapered H-tree b) Mesh


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DEC Alpha Clock Distribution

GCLK Grid

21064

21264


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PVT variations

Process variations Insulator thickness differences

Voltage variations

Voltage drops because power lines are resistive andhave to support the peak currents

Temperature variations

Local hot-spots have higher temperatures which makesthe chip slower


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Clock skew and jitter

Die size (D)

BC (Fast) Corner

WC (Slow) Corner

PVT (Process Voltage Temperature) variations

PVT Gradient

tskew=tslow-tfast


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Switching Activity

P

t

Peak power

Average power

By pass capacitance prevents rail


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CapGATE

By-pass capacitance prevents railvoltage from jumping

GATE

VR

GND

I

a) active gate b) passive gate c) by-pass capacitance

Power Distribution and Decoupling Strategy


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MicroprocessorWACC

Heat Slug

389 Signal - 198 VDD/VSS Pins

389 Signal Bondwires395 VDD/VSS Bondwires

320 VDD/VSS Bondwires

Example: EV6

34nF of effective switchingcapacitance

320nF of de-couplingcapacitance -- not enough!

(More details in 2B1428: Advanced VLSI Design )

S


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Summary

Floorplanning & placement

Routing, DRC and LVS check Clock-tree routing and power distribution

Post-layout verifications

- If you are lucky, youll probably get a working chip aftersome logic-physical design iterations

- More advanced design issues (lower power, higherperformance, such as advanced m-processors and

communication circuits design), continue in course2B1428.

Follow up Course 1 2B1428 Advanced VLSI Design


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Follow up Course 1 2B1428 Advanced VLSI Design

Focus on Advanced System and Circuits Level Design for

Low power & high-performance on-chip communications

Current-mode vs voltage mode driving, LVDS, bi-directional signaling,receivers, equalization, x-talk and noise budget etc

Timing and synchronization techniques

Different timing circuits, PLL, DLL, synchronizers (synchronous,mesochronous plesiochronous, periodic, asynchronous design) etc

Power and clock distribution

Power supply network, decoupling allocation, multiple supply distributionand isolation, clock generators, advanced clock distribution schemesetc

Examples


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CLD Q D Q

transmitter

D Q D Q LoopFilter

/2

receiver

matcheddelay

AD BDDin Dout

AClk

BClk

RClk

PC

FRDFTD

FT

QClk

Logic

PhaseComparator

Bundled Closed-Loop Timing

Current-mode driving circuits

Follow up Course 2 2B1450 Electronic System


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p yPackaging (mixed-signal system design)

2B1450- with focus on system and product


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level design of electronic systems

HiperLANmodule: Intarsial

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Lecture Physical Synthesis