10
E cient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform Gab Cheon Jung 1 , Seong Mo Park 2 , and Jung Hyoun Kim 3 1 Dept. of Electronics Engineering, Chonnam National University, 300 Youngbong-Dong, Puk-Gu, Gwangju 500-757, Korea 2 Dept. of Computer Engineering, Chonnam National University, 300 Youngbong-Dong, Puk-Gu, Gwangju 500-757, Korea 3 Dept. of Electrical Engineering, North Carolina A&T State University, 1601 East Market Street, Greensboro, NC 27411, USA Abstract. This paper presents e cient VLSI architectures for real time process- ing of separable convolution and lifting based 2-D discrete wavelet transform (DWT). Convolution based architecture uses partitioning algorithm based on the state space representation method and lifting based architecture applies pipelin- ing to each lifting step. Both architectures use recursive pyramid algorithm(RPA) scheduling that intersperses both the row and column operations of the second and following levels among column operations of the first level without using additional filter for row operations of the second and following levels. As a re- sult, proposed architectures have smaller hardware complexity compared to that of other conventional separable architectures with comparable throughput. 1 Introduction Having studied the method of replacing local Fourier analysis in geophysical signal processing, discrete wavelet transform(DWT) is widely utilized in digital signal fields these days. The wavelet transform not only provides high resolution in time and fre- quency but also has merit of representing images similar to human optical characteris- tics. However, since the DWT is implemented using filter banks, it requires extensive operations. To reduce these extensive operations, a lifting scheme was proposed[1] and has been used widely. Nevertheless, a dedicated hardware is indispensable in such a 2-D DWT case owing to huge operations both in row and column directions. In order to meet the computational requirements for real time processing of 2-D DWT, many VLSI architectures have been proposed and implemented[2-9]. For convo- lution based approach, Parhi and Nishitani[2] proposed two architectures which com- bine word-parallel and digit-serial methodologies. Vishwansth et al. [3] presented a systolic-parallel architecture. Chakrabarti and Mumford [4] presented the folded archi- tecture which consists of two parallel computation units and two storage units. This work was supported by the RRC-HECS, CNU under R0202. The support of IDEC CAD tools and equipment in this research is also gratefully acknowledged. T. Srikanthan et al. (Eds.): ACSAC 2005, LNCS 3740, pp. 795–804, 2005. c Springer-Verlag Berlin Heidelberg 2005

[Lecture Notes in Computer Science] Advances in Computer Systems Architecture Volume 3740 || Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform

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Page 1: [Lecture Notes in Computer Science] Advances in Computer Systems Architecture Volume 3740 || Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform

EÆcient VLSI Architectures for Convolution andLifting Based 2-D Discrete Wavelet Transform

Gab Cheon Jung1, Seong Mo Park2, and Jung Hyoun Kim3

1 Dept. of Electronics Engineering, Chonnam National University,300 Youngbong-Dong, Puk-Gu, Gwangju 500-757, Korea

�������������������� �2 Dept. of Computer Engineering, Chonnam National University,

300 Youngbong-Dong, Puk-Gu, Gwangju 500-757, Korea���� ��������� �

3 Dept. of Electrical Engineering, North Carolina A&T State University,1601 East Market Street, Greensboro, NC 27411, USA

���������

Abstract. This paper presents eÆcient VLSI architectures for real time process-ing of separable convolution and lifting based 2-D discrete wavelet transform(DWT). Convolution based architecture uses partitioning algorithm based on thestate space representation method and lifting based architecture applies pipelin-ing to each lifting step. Both architectures use recursive pyramid algorithm(RPA)scheduling that intersperses both the row and column operations of the secondand following levels among column operations of the first level without usingadditional filter for row operations of the second and following levels. As a re-sult, proposed architectures have smaller hardware complexity compared to thatof other conventional separable architectures with comparable throughput.

1 Introduction

Having studied the method of replacing local Fourier analysis in geophysical signalprocessing, discrete wavelet transform(DWT) is widely utilized in digital signal fieldsthese days. The wavelet transform not only provides high resolution in time and fre-quency but also has merit of representing images similar to human optical characteris-tics. However, since the DWT is implemented using filter banks, it requires extensiveoperations. To reduce these extensive operations, a lifting scheme was proposed[1] andhas been used widely. Nevertheless, a dedicated hardware is indispensable in such a2-D DWT case owing to huge operations both in row and column directions.

In order to meet the computational requirements for real time processing of 2-DDWT, many VLSI architectures have been proposed and implemented[2-9]. For convo-lution based approach, Parhi and Nishitani[2] proposed two architectures which com-bine word-parallel and digit-serial methodologies. Vishwansth et al. [3] presented asystolic-parallel architecture. Chakrabarti and Mumford [4] presented the folded archi-tecture which consists of two parallel computation units and two storage units.

This work was supported by the RRC-HECS, CNU under R0202. The support of IDEC CADtools and equipment in this research is also gratefully acknowledged.

T. Srikanthan et al. (Eds.): ACSAC 2005, LNCS 3740, pp. 795–804, 2005.c� Springer-Verlag Berlin Heidelberg 2005

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796 G.C. Jung, S.M. Park, and J.H. Kim

Chakrabarti and Vishwanath[5] proposed the parallel filter architectures for 2-D non-separable DWT. Yu and Chen[6] developed a parallel-systolic filter structure to improvehardware complexity of [5].

Convolution based architectures have easy scalability according to filter length butthey generally require larger amount of hardware. On the other hands, lifting basedarchitectures have a diÆculty of scaling the structure but have smaller hardware amountcompare to convolution based architectures. For lifting based approach, Andra et al. [7]and G. Dillen et al.[8] presented architectures which conduct DWT operations in levelby level mode. They require an external RAM module with size of N2�4 for N�N image.Huang et al. [9] presented architecture which implements 2-D lifting based DWT onlywith line memories by using recursive pyramid algorithm(RPA)[10].

In this paper, we proposed eÆcient line based VLSI architectures for separable con-volution and lifting based 2-D DWT. The rest of the paper is organized as follows.Algorithm decomposition of 2-D DWT is presented in section 2. Section 3 presentsthe proposed architectures. Comparison of various DWT architectures is described insection 4. Finally, concluding remarks are summarized in Section 5.

2 Algorithm Decomposition

2.1 Convolution Based Algorithm

A separable 2-D DWT can be seen as a 1-D wavelet transform along the rows and a 1-Dwavelet transform along the columns[11]. Thus, 2-D DWT can be computed in cascadeby filtering rows and columns of an image with 1-D filters. Fig. 1 illustrates a decom-position algorithm of 2-D DWT, where g represents a high pass filter and h represents alow pass filter. At the first level of decomposition, input image is decomposed into twosubbands(H, L) by filtering along the rows and H, L subbands are decomposed againinto four subbands(HH, HL, LH, LL) by filtering along the columns. The multi-leveldecomposition is performed with LL subband instead of input image.

In fact, this algorithm is the same as a separable conjugate mirror filter decomposi-tion, and can be viewed as the pyramid structure for 2-D product separable filter banks.

Fig. 1. Decomposition algorithm for 2-D DWT

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EÆcient VLSI Architectures for Convolution and Lifting Based 2-D DWT 797

A 2-D product separable filter can be represented as follows:

�(n�m) �L2�1�

i�0

L1�1�

j�0a(i� j)x(n � i�m � j)

�L2�1�

j�0a( j)

L1�1�

i�0a(i)x(n � i�m � j)�

(1)

where a(i,j) is an impulse response of the product separable 2-D filter and L1 and L2

are length of the filter in the horizontal and vertical direction respectively. The secondequation of equation(1) indicates a row-column decomposition for 2-D filtering.

The 2-D DWT can be computed by decomposing equation(1) into a set of statespace equations using horizontal state variables (q1

H, q2H ,..., qk

H) and vertical state vari-ables (q1

V , q2V ,..., qk

V ) in consideration of 2:1 decimation operation as follows:

y(n,m)�a(0)x(2n,m)�a(1)x(2n-1,m)�q1H(n-1,m),

qk1H (n,m)�a(2k1)x(2n,m)�a(2k1�1)x(2n-1,m)�qk1�1

H (n-1,m),

H(n,m)� �(n,m) for a(L1)� �(L1)�

L(n,m)� �(n,m) for a(L1) � h(L1)�

for n � 0,1,. . . ,(N�2)- 1, m� 0,1,. . . ,N-1, k1 � 1,2,. . . ,(�L1�2�-1).

(2)

w(n,m)�a(0)y(n,2m)�a(1)y(n,2m-1)�q1V(n,m-1),

qk2V (n,m)�a(2k2)y(n,2m)�a(2k2�1)y(n,2m-1)�qk2�1

V (n,m-1),

HH(n,m)�w(n,m) for a(L2)� �(L2) and y(n,m)�H(n,m),

HL(n,m)�w(n,m) for a(L2)� h(L2) and y(n,m)�H(n,m),

LH(n,m)�w(n,m) for a(L2)� �(L2) and y(n,m)�L(n,m),

LL(n,m)�w(n,m) for a(L2)� h(L2) and y(n,m)�L(n,m),

for n� 0,1,. . . ,(N�2)-1, m � 0,1,. . . ,(N�2)- 1, k2 � 1,2,. . . ,(�L2�2�-1).

(3)

Equation(2) represents row operations in horizontal direction and uses inputs x(2n,m),x(2n-1,m) and previous horizontal state variables qH(n-1,m) for the computation, wherea(0), a(1), a(2),. . . ,a(L1-1) denote high pass filter coeÆcients(�(0), �(1),. . . ,�(L1-1))or low pass filter coeÆcients (h(0), h(1),. . . ,h(L1-1)). Equation (3) represents columnoperations in vertical direction and uses results (y(n,2m), y(n,2m-1)) of equation (2) andprevious vertical state variables qV (n,m-1). In equation(2)and(3), each output and statevariable uses two inputs and one previous state variable and requires two multiplicationsand three additions. Thus, it can be computed with critical path having 1 multiplicationand 2 additions regardless of wavelet filer length.

2.2 Lifting Scheme

Daubeches and Sweldens[1] proposed the lifting scheme in order to reduce exten-sive operations of filter bank. The lifting scheme decomposes every DWT operationsinto finite sequences of simple filtering steps. The lifting steps are consists of three

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798 G.C. Jung, S.M. Park, and J.H. Kim

Fig. 2. Lifting Step

steps(splitting, prediction, and update) as shown in fig. 2. In splitting step, input signalsare split into even samples and odd samples. The prediction step predicts odd samplesfrom even samples and computes high pass coeÆcients(d) by calculating the di�er-ence between the odd samples and the prediction values. In update step, the low passcoeÆcients(s) are computed from high pass coeÆcients.

The lifting scheme has many advantages such as a fast computation, in place cal-culation, integer-to-integer, easiness of inverse implementation, etc. Because of thesemerits, the JPEG2000 standard supports lifting scheme as well as convolution methodfor DWT operations. It adopts integer (5,3) filter for reversible transform and biorthog-onal (9,7) filter for irreversible transform as default mode[12,13]. While high pass andlow pass results for (5,3) filter are computed by predict and update step once, results for(9,7) filter require one more predict and update step.

The lifting equations for biorthogonal (9,7)�(5,3) filter of the separable 2-D DWTcan be represented by equation(4) and equation(5) where K is a scaling factor and is1.0 for (5,3) filter. Each predict step with filter coeÆcient �, � produces high passresults. And update steps with filter coeÆcient �, Æ produce low pass results. In thisequation, we can consider s0(n), d1(n), s1(n), and d2(n) inputs of each lifting stepto be state variables since the present state of these inputs are used for next liftingoperations.

d0H(n,m)�x(2n�1,m),

s0H(n,m)�x(2n,m),

d1H(n,m)�d0

H(n,m)�� (s0H(n,m)�s0

H(n�1,m)),

s1H(n,m)�s0

H(n,m)�� (d1H(n�1,m)�d1

H(n,m)),

d2H(n,m)�d1

H(n,m)�� (s1H(n,m)�s1

H(n�1,m)),

s2H(n,m)�s1

H(n,m)�Æ (d2H(n�1,m)�d2

H(n,m)),

H(n,m)�d1H(n,m), L(n,m)�s1

H(n,m) for (5,3)filter

� (1�K)d2H(n,m) � Ks2

H(n,m) for (9,7) filter,

for n� 0,1,� � �,(N�2)-1, m � 0,1,� � �,N- 1.

(4)

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EÆcient VLSI Architectures for Convolution and Lifting Based 2-D DWT 799

d0V (n,m)�H(n,2m�1) or L(n,2m�1),

s0V (n,m)�H(n,2m) or L(n,2m),

d1V (n,m)�d0

V(n,m)�� (s0V (n,m)�s0

V(n,m�1)),

s1V (n,m)�s0

V(n,m)�� (d1V(n,m�1)�d1

V(n,m)),

d2V (n,m)�d1

V(n,m)�� (s1V (n,m)�s1

V(n,m�1)),

s2V (n,m)�s1

V(n,m)�Æ (d2V(n,m�1)�d2

V(n,m)),

HH(n,m)�Hd1V(n,m), HL(n,m)�Hs1

V(n,m) for (5,3)filter

�H(1�K)d2V(n,m) �H(K)s2

V (n,m) for(9,7)filter

LH(n,m)�Ld1V(n,m), LL(n,m)�Ls1

V(n,m) for (5,3)filter

�L(1�K)d2V(n,m) �L(K)s2

V(n,m) for(9,7)filter,

for n� 0,1,� � �,(N�2)-1, m � 0,1,� � �,(N�2)- 1.

(5)

3 Proposed Architectures

This section describes the proposed VLSI architectures for convolution and lifting based2-D DWT. For consistency in description of our architectures, we use the biorthogonal(9,7) filter. The proposed architecture for 2-D convolution based DWT consists of a hor-izontal(HOR) filter, signal memory(SIG MEM), and a vertical(VER) filter as shown infig. 3. The architecture for 2-D lifting based DWT also has the same structure as in fig. 3.

3.1 HOR Filter

The HOR filter conducts DWT operation along the rows with two columns of imagefrom the internal serial-to-parallel converter which splits serial input image data intoparallel column data(odd, even) at every other clock cycle. For convolution based ar-chitecture, symmetric characteristic of biorthogonal filter coeÆcients is used. That is,two same multiplications of filter coeÆcient and input in equation(2) share one multi-plier. Thus, the number of multiplier is reduced to a half. The HOR filter for convolutioncontains 5 multipliers, 8 adders, and 4 S.V(State Variable) registers as shown in fig. 4and outputs high pass result or low pass result at every clock cycle.

Fig. 3. Block diagram of proposed architecture for 2-D DWT

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800 G.C. Jung, S.M. Park, and J.H. Kim

Fig. 4. HOR filter structure: convolution based DWT

The HOR filter for lifting scheme computes equation (4). Fig. 5 shows HOR fil-ter for lifting based DWT. For (9, 7) filter, the PE0 computes predict steps and PE1computes update steps. The lifting based architecture contains 3 multipliers, 4 adders,2 S.V(State Variable) registers, 6 registers for pipelining each lifting step.

3.2 Signal Memory

The signal memory is used to store intermediate results and to send these results to theVER filter. It includes odd and even line bu�ers as shown in fig. 6. Odd line bu�erstores one odd row of (LL)JH and (LL)JL (J�0) subbands or odd column for one rowof (LL)J (J�1) subbands. And even line bu�er stores even row of (LL)JH and (LL)JL(J�1) subbands. One register in even line bu�er is used to store present output from theHOR filter for even row of image.

3.3 VER Filter

For the operational scheduling in our scheme, the VER filter conducts column opera-tions at the first level when the HOR filter outputs H, L results for even row of image.

Fig. 5. HOR filter structure: lifting based DWT

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EÆcient VLSI Architectures for Convolution and Lifting Based 2-D DWT 801

Fig. 6. The signal memory for intermediate results

Fig. 7. Timing diagram of VER filter for odd rows

On the other hands, when the HOR filter outputs H, L results for odd row of image, itconducts both row operations and column operations at the second and following levelsas showin in fig. 7. These operations were scheduled with consideration of the comput-ing time and data dependency. Since the VER filter computes high pass and low passoutputs concurrently, the computing time of column operation for one single line at theJ level(J0) is N�(2)J�1 and the computing time of row operations for single line at theJ level(J1) is (1�2)�(N�(2)J�1)�N�(2)J. Fig. 8 shows data flow of the VER filter withsignal memory according to above scheduling.

The VER filter for convolution consists of two processing units as shown in fig. 9. Itcomputes equation(2) for row operations with two columns of (LL)J�1 (J1) subbandsand equation(3) for column operations with two rows of H(LL)J , L(LL)J (J0) sub-bands. The VER filter for lifting scheme consists of 4 processing elements as shown infig. 10 and computes equation(4) for row operations and equation(5) for column opera-tions. Each processing element conducts each lifting step.

The internal structure of each PU and PE in a VER filter is identical to that of HORfilter except for filter coeÆcients(PU:low-pass, high-pass, PE: PE0-� , PE1-�, PE2-�, PE3-Æ) and state variable(S.V) bu�ers. Each horizontal state variable(qH) in VER

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802 G.C. Jung, S.M. Park, and J.H. Kim

(a) (b)

Fig. 8. Data flow of VER filter at (a)even rows and (b)odd rows of image

Fig. 9. The VER filter structure: convolution based DWT

Fig. 10. The VER filter structure: lifting base DWT

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EÆcient VLSI Architectures for Convolution and Lifting Based 2-D DWT 803

filter requires 1 register for row operations. And each vertical state variables for verti-cal filtering are stored in bu�ers with size of 2N(N�(N�2)�(N�4). . .�N�2J�1) becausevertical state variables for one row at all the decomposition level must be stored for thecomputation of next row.

4 Performance and Comparisons

While conventional 2-D architectures that implement RPA have 50%�66.7% hardwareutilization, proposed architectures have higher hardware utilization. Contrary to the con-ventional RPA based architectures in [4][5] which have independent filter for row op-erations of the second and following levels, proposed architectures make the VER filtercompute not only all levels along columns but also the second and following levels alongrows. This leads that proposed architectures have 66.7%�88.9% hardware utilizations.

Table 1 shows comparisons of proposed architectures and previous conventional 2-D DWT architectures, where Tm is the latency of multiplication and Ta is the latency ofaddition. Comparison is performed with the number of multipliers, adders, storage size,and critical path. Note that the scaling factors are involved in multipliers and pipelin-ing is not applied to critical path, and symmetric characteristic of biorthogonal filteris considered for convolution based architectures. In table 1, architectures in [4], [5]and proposed architecture(convolution) use convolution method and architectures in [9]and proposed(lifting) use lifting scheme. When compared with architectures in [4], [5],proposed one(convolution) has not only less amount of hardware but can reduce crit-ical path. While architectures in [4], [5] have the critical path having Tm�

�Lo�2L

�Ta,

the proposed one(convolution) has critical path having Tm� 2Ta regardless of filterlength. When compare the proposed architecture(lifting) with [9], we know that pro-posed one(lifting) has less amount of hardware such as multipliers and adders throughthe improvement of hardware utilization.

5 Conclusion

In this paper, RPA based 2-D DWT architectures for convolution and lifting schemewere described. Proposed architectures do not use additional independent filter for row

Table 1. Comparison of various 2-D architectures for (9,7) filter

Multipliers Adders Storage size Computing time Critical path

Proposed(Convolution)

14 22 18N �N2 Tm�2Ta

Systolic-Parallel[5]

19 30 22N �N2 Tm�4Ta

Folded[4] 19 30 18N�(3�2)N � N2 Tm�4Ta

Proposed(Lifting)

9 12 12N � N2 4Tm�8Ta

Lifting[9] 12 16 14N � N2 4Tm�8Ta

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804 G.C. Jung, S.M. Park, and J.H. Kim

operations of the second and following levels. As a result, regarding biorthogonal (9,7)filter, convolution based architecture has 14 multipliers, 22 adders, and 18N line mem-ories for N�N image. And lifting based one requires 9 multipliers, 12 adders, and 12Nline memories. With the reduction of hardware cost, convolution based architecture hascritical path having 1 multiplication and 2 additions regardless of wavelet filter lengthby state space representation method. Proposed architectures are very suitable for singlechip design due to small hardware cost and regularity.

References

1. I. Daubechies and W. Sweldens.: Factoring wavelet transforms into lifting schemes. TheJournal of Fourier Analysis and Applications, Vol. 4, (1998) 247-269

2. K. K . Parhi and T. Nishitani.: VLSI Architectures for Discrete Wavelet Transforms. IEEETrans. VLSI Systems. Vol. 1, No. 2, (June 1993) 191-202

3. M. Vishwanath, R. M. Owens, and M. J. Irwin.: VLSI architectures for the discrete wavelettransform. IEEE Trans. Circuits and Systems II, Analog and digital Signal Processing, Vol.42, No. 5, (May 1995) 305-316

4. C. Chakrabarti and C. Mumford.: EÆcient Realizations of encoders and decoders based onthe 2-D Discrete Wavelet Transform. IEEE Trans. VLSI Systems, (September 1999) 289-298

5. C. Chakrabarti and M. Vishwanath.: EÆcient Realizations of the Discrete and ContinuousWavelet Transforms: from Single Chip Implementations to Mappings on SIMD array Com-puters. IEEE Trans. Signal Processing Vol. 43, No. 3, (Mar. 1995) 759-771

6. Chu Yu and Sao-Jie Chen.: VLSI Implementation of 2-D Discrete Wavelet Transform forReal-Time Video Signal Processing. IEEE Trans. Consumer Electronics, Vol. 43, No. 4, (No-vember 1997) 1270-1279

7. K. Andra, C. Chakrabarti, and T. Acharya.: A VLSI Architecture for Lifting-Based Forwardand Inverse Wavelet Transform. IEEE Trans. Signal Processing, Vol. 50, No. 4, (April 2002)966-977

8. G. Dillen, B. Georis, J.D. Legat, and O. Cantineau.: Combined Line-Based Architecture forthe 5-3 and 9-7 Wavelet Transform of JPEG2000. IEEE Trans. Circuits and Systems forVideo Technology, Vol. 13, No. 9, (September 2003) 944-950

9. C. T. Huang, P. C. Tseng, and L.G. Chen.: EÆcient VLSI architectures of Lifting-BasedDiscrete Wavelet Transform by Systematic Design Method. IEEE International Symp. onCircuits and Systems, vol. 5, (May 2002) 26-29

10. M. Vishwanath.: The Recursive Pyramid Algorithm for the Discrete Wavelet Transform.IEEE Trans. Signal Processing, Vol.42, No.3, (March 1994) 673-677

11. S. G. Mallet.: A theory of multiresolution signal decomposition : the wavelet representation.IEEE Trans. on Pattern Recognition and Machine Intelligence, Vol. 11, No. 7, (July 1989)674-693

12. ISO�IEC JTC1�SC29�WG1 (ITU-T SG8) N2165.: JPEG2000 Verification Model 9.1 (Tech-nical Description), (June 2001)

13. C. Christopoulos, A. Skodras and T. Rbrahimi.: The JPEG2000 Still Image coding System:An Overview. IEEE Trans. On Consumer Electronics, Vol. 46, No. 4, (November 2000)1103-1127