Upload
shanna-jackson
View
241
Download
0
Embed Size (px)
Lecture 10:
Circuit Families
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 2
Outline Pseudo-nMOS Logic (Ratioed Logic) Dynamic Logic Pass Transistor Logic
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 3
Introduction What makes a circuit fast?
– I = C dV/dt -> tpd (C/I) V
– low capacitance– high current– small swing
Logical effort is proportional to C/I pMOS are the enemy!
– High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this…
B
A
11
4
4
Y
CMOS VLSI DesignCMOS VLSI Design 4th Ed.4
Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
CMOS VLSI DesignCMOS VLSI Design 4th Ed.5
Ratioed LogicVDD
VSS
PDN
In1
In2
In3
F
RLLoad
ResistiveN transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
CMOS VLSI DesignCMOS VLSI Design 4th Ed.6
Active LoadsVDD
VSS
In1In2In3
F
VDD
VSS
PDN
In1In2In3
F
VSS
PDN
Depletion
LoadPMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 7
Pseudo-nMOS In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON
– Ratio issue– Make pMOS about ¼ effective strength of
pulldown network
Vout
Vin
16/2
P/2
Ids
load
0 0.3 0.6 0.9 1.2 1.5 1.8
0
0.3
0.6
0.9
1.2
1.5
1.8
P = 24
P = 4
P = 14
Vin
Vout
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Pseudo-nMOS
10: Circuit Families 8
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Pseudo-NMOS VTC
10: Circuit Families 9
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Pseudo-nMOS Design
Size of PMOS VOLStatic Power Dissipation
tpLH
4 0.693 V 564 W 14 ps
2 0.273 V 298 W 56 ps
1 0.133 V 160 W 123 ps
0.5 0.064 V 80 W 268 ps
0.25 0.031 V 41 W 569 ps
10: Circuit Families 10
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 11
Pseudo-nMOS Gates Design for unit current on output
to compare with unit inverter. pMOS fights nMOS Iout = 4I/3 – I/3
Inverter NAND2 NOR2
AY
B
AY
A B
gu =gd =gavg =pu =pd =pavg =
Y
gu =gd =gavg =pu =pd =pavg =
gu =gd =gavg =pu =pd =pavg =
finputs
Y
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 12
Pseudo-nMOS Gates Design for unit current on output
to compare with unit inverter. pMOS fights nMOS
Inverter NAND2 NOR2
4/3
2/3
AY
8/3
8/3
2/3
B
AY
A B 4/34/3
2/3
gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9
Y
gu = 8/3gd = 8/9gavg = 16/9pu = 10/3pd = 10/9pavg = 20/9
gu = 4/3gd = 4/9gavg = 8/9pu = 10/3pd = 10/9pavg = 20/9
finputs
Y
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 13
Pseudo-nMOS Design Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N = 2 D = NF1/N + P =
In1
Ink
Y
Pseudo-nMOS1
1 H
4 2 8 13
3 9
H k
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 14
Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0
– Called static power P = IDDVDD
– A few mA / gate * 1M gates would be a problem– Explains why nMOS went extinct
Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use
A BY
C
en
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 15
Ratio Example The chip contains a 32 word x 48 bit ROM
– Uses pseudo-nMOS decoder and bitline pullups– On average, one wordline and 24 bitlines are high
Find static power drawn by the ROM
– Ion-p = 36 A, VDD = 1.0 V
Solution:pull-up pull-up
static pull-up
36 μW
(31 24) 1.98 mW
DDP V I
P P
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Pseudo-NMOS Design Pseudo-nMOS gates will not operate correctly if
VOL>VIL of the driven gate.
This is most likely in the SF corner. Conservative design requires extra weak pMOS. Another choice is to use replica biasing. Idea comes from analog design. Replica biasing allows 1/3 the current ratio rather
than the conservative ¼ ratio of earlier.
10: Circuit Families 16
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Replica Biasing
10: Circuit Families 17
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Ganged CMOS
10: Circuit Families 18
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Ganged CMOS
A B N1 P1 N2 P2 Y
0 0 OFF ON OFF ON 1
0 1 OFF ON ON OFF ~0
1 0 ON OFF OFF ON ~0
1 1 ON OFF ON OFF 0
10: Circuit Families 19
CMOS VLSI DesignCMOS VLSI Design 4th Ed.20
Improved Loads
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
Adaptive Load
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Improved Loads
10: Circuit Families 21
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22
Improved Loads (2)
Differential Cascode Voltage Switch Logic (DCVSL)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.23
DCVSL Example
B
A A
B B B
Out
Out
XOR-NXOR gate
CMOS VLSI DesignCMOS VLSI Design 4th Ed.24
DCVSL Example
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
DCVSL Transient Response
10: Circuit Families 25
CMOS VLSI DesignCMOS VLSI Design 4th Ed.26
Pass-Transistor LogicIn
puts
Switch
Network
OutOut
A
B
B
B
• N transistors
• No static consumption
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Example: AND Gate
10: Circuit Families 27
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
NMOS-Only Logic
10: Circuit Families 28
CMOS VLSI DesignCMOS VLSI Design 4th Ed.29
NMOS-Only Switch
CMOS VLSI DesignCMOS VLSI Design 4th Ed.30
NMOS Only Logic: Level Restoring Transistor
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Restorer Sizing
10: Circuit Families 31
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 32
LEAP LEAn integration with Pass transistors Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high– Ratio constraint
B
S
S
AYL
CMOS VLSI DesignCMOS VLSI Design 4th Ed.33
Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=AÝ
F=AÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 34
CPL Complementary Pass-transistor Logic
– Dual-rail form of pass transistor logic– Avoids need for ratioed feedback– Optional cross-coupling for rail-to-rail swing
B
S
S
S
S
A
B
AY
YL
L
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Alternative CPL
10: Circuit Families 35
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Transmission Gate
10: Circuit Families 36
CMOS VLSI DesignCMOS VLSI Design 4th Ed.37
Resistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce
, oh
ms
Rn
Rp
Rn || Rp
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 38
Pass Transistor Circuits
Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates
CMOS + Transmission Gates:– 2-input multiplexer– Gates should be restoring
A
B
S
S
S
Y
A
B
S
S
S
Y
CMOS VLSI DesignCMOS VLSI Design 4th Ed.39
Pass-Transistor Based Multiplexer
AM2
M1
B
S
S
S F
VDD
GND
VDD
In1
In2
S S
S S
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Transmission Gate XOR
10: Circuit Families 40
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Delay in Transmission Gate Networks
10: Circuit Families 41
CMOS VLSI DesignCMOS VLSI Design 4th Ed.42
Delay Optimization
CMOS VLSI DesignCMOS VLSI Design 4th Ed.43
Transmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 44
Other Pass Transistor Families
DPTL (Differential Pass Transistor Logic) DPL (Double Pass Transistor Logic) EEPL (Energy Economized Pass Transistor Logic) PPL (Push-Pull Pass Transistor Logic) SRPL (Swing Restored Pass Transistor Logic) DCVSPG (Differential Cascode Voltage Switch with
Pass Gate Logic)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 45
Pass Transistor Summary
Researchers investigated pass transistor logic for general purpose applications in the 1990’s– Benefits over static CMOS were small or negative– No longer generally used
However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Single Clock 2-Phase System
10: Circuit Families 46
T/2 T 3T/2
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Shift Register
10: Circuit Families 47
A
PHI
PHIBAR
PHIBAR
PHI
VDD VDD
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Shift Register When = 1, data move through the first
transmission gate to the inverter.
10: Circuit Families 48
€
τTG = RTGCL
CL = CTG + Cinv + Cline
When VA =1,
Vin t( ) = VDD 1 − e− t
τ TG ⎛ ⎝ ⎜
⎞ ⎠ ⎟
When VA = 0,
Vin t( ) = VDDe− t
τ TG
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Leakage
10: Circuit Families 49
A
PHI
PHIBAR
CL
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Leakage
10: Circuit Families 50
€
IL = ILn − ILp
CdVin
dt= −IL
dQstore
dt= ILp − ILn
Cstore =dQstore
dV
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Leakage Both Q and I are nonlinear Assume that I’s are constant.
10: Circuit Families 51
€
Qstore = CstoreV
Cstore
dV
dt= ILp − ILn
V t( ) =ILp − ILn
Cstore
t +V 0( )
tmax =CstoreΔV
IL
fmin ≈1
2tmax
=IL
2CstoreΔV
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Sharing
10: Circuit Families 52
PHI
PHIBAR
C2C1
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Sharing We can write
The more general case:
10: Circuit Families 53
€
At t = 0, V1 = VDD ,V2 = 0, QT = C1VDD
At t = t f , QT = C1 + C2( )V f
V f =C1
C1 + C2
VDD
€
QT = CiVi 0( )i=1
N
∑ , QT = Cii=1
N
∑ ⎛
⎝ ⎜
⎞
⎠ ⎟V f
V f =
CiVi 0( )i=1
N
∑
Cii=1
N
∑
CMOS VLSI DesignCMOS VLSI Design 4th Ed.54
Dynamic CMOS In static circuits at every point in time (except
when switching) the output is connected to either GND or VDD via a low resistance path.– fan-in of n requires 2n (n N-type + n P-type)
devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.– requires on n + 2 (n+1 N-type + 1 P-type)
transistors
CMOS VLSI DesignCMOS VLSI Design 4th Ed.56
Dynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.57
Conditions on Output Once the output of a dynamic gate is
discharged, it cannot be charged again until the next precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
CMOS VLSI DesignCMOS VLSI Design 4th Ed.58
Properties of Dynamic Gates
Logic function is implemented by the PDN only– number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the logic levels
Faster switching speeds– reduced load capacitance due to lower input capacitance (Cin)
– reduced load capacitance due to smaller output loading (Cout)
– no Isc, so all the current provided by PDN goes into discharging CL
CMOS VLSI DesignCMOS VLSI Design 4th Ed.59
Properties of Dynamic Gates
Overall power dissipation usually higher than static CMOS– no static current path ever exists between VDD and
GND (including Psc)– no glitching– higher transition probabilities– extra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
– low noise margin (NML)
Needs a precharge/evaluate clock
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 60
Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate
1
2A Y
4/3
2/3
AY
1
1
AY
Static Pseudo-nMOS Dynamic
Precharge Evaluate
Y
Precharge
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 61
The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight.
AY
foot
precharge transistor
Y
inputs
Y
inputs
footed unfooted
f f
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 62
Logical Effort
Inverter NAND2 NOR2
1
1
AY
2
2
1
B
AY
A B 11
1
gd = 1/3pd = 2/3
gd = 2/3pd = 3/3
gd = 1/3pd = 3/3
Y
2
1
AY
3
3
1
B
AY
A B 22
1
gd = 2/3pd = 3/3
gd = 3/3pd = 4/3
gd = 2/3pd = 5/3
Y
footed
unfooted
32 2
CMOS VLSI DesignCMOS VLSI Design 4th Ed.63
Issues in Dynamic Design 1: Charge Leakage
CL
Clk
Clk
Out
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dominant component is subthreshold current
CMOS VLSI DesignCMOS VLSI Design 4th Ed.64
Solution to Charge Leakage
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Same approach as level restorer for pass-transistor logic
Keeper
CMOS VLSI DesignCMOS VLSI Design 4th Ed.65
Issues in Dynamic Design 2: Charge Sharing
CL
Clk
Clk
CA
CB
B=0
A
OutMp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
CMOS VLSI DesignCMOS VLSI Design 4th Ed.66
Charge Sharing Example
CL=50fF
Clk
Clk
A A
B B B !B
CC
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
CMOS VLSI DesignCMOS VLSI Design 4th Ed.67
Charge Sharing
Mp
Me
VDD
Out
A
B = 0
CL
Ca
Cb
Ma
Mb
X
CLVDD CLVout t Ca VDD VTn VX – +=
or
Vout Vout t VDD–CaCL-------- VDD VTn VX
– –= =
Vout VDD
CaCa CL+----------------------
–=
case 1) if Vout < VTn
case 2) if Vout > VTnB 0
Clk
X
CL
Ca
Cb
A
Out
Mp
Ma
VDD
Mb
Clk Me
CMOS VLSI DesignCMOS VLSI Design 4th Ed.68
Solution to Charge Redistribution
Clk
Clk
Me
Mp
A
B
OutMkp
Clk
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.69
Issues in Dynamic Design 3: Backgate Coupling
CL1
Clk
Clk
B=0
A=0
Out1Mp
Me
Out2
CL2
In
Dynamic NAND Static NAND
=1=0
CMOS VLSI DesignCMOS VLSI Design 4th Ed. 70
Backgate Coupling Effect
-1
0
1
2
3
0 2 4 6
Vol
tage
Time, ns
Clk
In
Out1
Out2
CMOS VLSI DesignCMOS VLSI Design 4th Ed.71
Issues in Dynamic Design 4: Clock Feedthrough
CL
Clk
Clk
B
A
OutMp
Me
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
CMOS VLSI DesignCMOS VLSI Design 4th Ed.72
Clock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In1
In2
In3
In4
Out
In &Clk
Out
Time, ns
Vol
tage
Clock feedthrough
Clock feedthrough
CMOS VLSI DesignCMOS VLSI Design 4th Ed.73
Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.74
Cascading Dynamic Gates
Clk
Clk
Out1
In
Mp
Me
Mp
Me
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2V
VTn
Only 0 1 transitions allowed at inputs!
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 75
Monotonicity Dynamic gates require monotonically rising inputs
during evaluation– 0 -> 0– 0 -> 1– 1 -> 1– But not 1 -> 0
Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicity during evaluation
A
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 76
Monotonicity Woes But dynamic gates produce
monotonically falling outputs during evaluation
Illegal for one dynamic gate to drive another!
AX
Y
Precharge Evaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
AX
Y
Precharge Evaluate
X
Precharge
A = 1
Y
CMOS VLSI DesignCMOS VLSI Design 4th Ed.77
Domino Logic
In1
In2 PDN
In3
Me
Mp
Clk
ClkOut1
In4 PDN
In5
Me
Mp
Clk
ClkOut2
Mkp
1 11 0
0 00 1
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 78
Domino Gates Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate– Produces monotonic outputs
Precharge Evaluate
W
Precharge
X
Y
Z
A
BC
C
AB
W XY Z =
XZH H
A
W
B C
X Y Z
domino AND
dynamicNAND
staticinverter
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 79
Domino Optimizations Each domino gate triggers next one, like a string of
dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic
S0
D0
S1
D1
S2
D2
S3
D3
S4
D4
S5
D5
S6
D6
S7
D7
YH
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 80
Dual-Rail Domino Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem
– Takes true and complementary inputs – Produces true and complementary outputs
sig_h sig_l Meaning
0 0 Precharged
0 1 ‘0’
1 0 ‘1’
1 1 invalid
Y_h
f
inputs
Y_l
f
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 81
Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = AB, Y_l = AB Pulldown networks are conduction complements
Y_h
Y_l
A_h
B_hB_lA_l
= A*B= A*B
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 82
Example: XOR/XNOR Sometimes possible to share transistors
Y_h
Y_l
A_l
B_h
= A xor B
B_l
A_hA_lA_h= A xnor B
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
np-CMOS
10: Circuit Families 83
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
NORA Logic
10: Circuit Families 84
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
NP Domino
10: Circuit Families 85
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Zipper CMOS The NP-Domino or NORA logic is very susceptible to
noise and leakage. Zipper Domino has the same structure, but the
precharge transistors are left slightly ON during evaluation.
10: Circuit Families 86
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 87
Leakage Dynamic node floats high during evaluation
– Transistors are leaky (IOFF 0)
– Dynamic value will leak away over time– Formerly miliseconds, now nanoseconds
Use keeper to hold dynamic node– Must be weak enough not to fight evaluation
A
H
2
2
1 kX
Y
weak keeper
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 88
Charge Sharing Dynamic gates suffer from charge sharing
B = 0
AY
x
Cx
CY
A
x
Y
Charge sharing noise
Yx Y DD
x Y
CV V V
C C
A
x
Y
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 89
Secondary Precharge Solution: add secondary precharge transistors
– Typically need to precharge every other node Big load capacitance CY helps as well
B
AY
x
secondaryprechargetransistor
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 90
Noise Sensitivity Dynamic gates are very sensitive to noise
– Inputs: VIH Vtn
– Outputs: floating output susceptible noise Noise sources
– Capacitive crosstalk– Charge sharing– Power supply noise– Feedthrough noise– And more!
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 91
Power
Domino gates have high activity factors– Output evaluates and precharges
• If output probability = 0.5, = 0.5– Output rises and falls on half the cycles
– Clocked transistors have = 1
– For a 4 input NAND, CMOS = 3/16, Dynamic = 1/4
Leads to very high power consumption However, glitching does not occur in dynamic logic. The load capacitances are lower.
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Completion Detection
10: Circuit Families 92
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Keepers Keeper design is not trivial. Many alternatives have been suggested.
10: Circuit Families 93
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Conventional Keeper
10: Circuit Families 94
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Weak Keepers
10: Circuit Families 95
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Differential Keeper
10: Circuit Families 96
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Burn-in Conditional Keeper
10: Circuit Families 97
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Adaptive Keeper
10: Circuit Families 98
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Leakage Current Replica Keeper
10: Circuit Families 99
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Footed and Footless Domino
10: Circuit Families 100
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
8-input Domino AND
10: Circuit Families 101
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
8-input Domino AND
10: Circuit Families 102
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
MODL It is often necessary to compute multiple functions
where one is a subfunction of the other or shares a subfunction.
One very typical example is the carry in addition:
10: Circuit Families 103€
c1 = g1 + p1c0
c2 = g2 + p2 g1 + p1c0( )
c3 = g3 + p3 g2 + p2 g1 + p1c0( )( )
c4 = g4 + p4 g3 + p3 g2 + p2 g1 + p1c0( )( )( )
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
MODL Carry Chains
10: Circuit Families 104
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
MODL Beware of sneak paths. Certain inputs must be mutually exclusive.
10: Circuit Families 105
CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Circuit Families 106
Domino Summary Domino logic is attractive for high-speed circuits
– 1.3 – 2x faster than static CMOS– But many challenges:
• Monotonicity, leakage, charge sharing, noise Widely used in high-performance microprocessors in
1990s when speed was king Largely displaced by static CMOS now that power is
the limiter Still used in memories for area efficiency
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
2-input MUX
10: Circuit Families 107
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Which Logic Style? Ease of design Robustness Area Speed Power
10: Circuit Families 108
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Which Logic Style?
Ease of Design
Robust-ness
Area Speed Power
Static Very good Very good Bad Bad Good
Pseudo-nMOS
Average Average Good Good Very bad
Pass transistor
Difficult Average Good (for specific circuits)
Good (for specific circuits)
average
Dynamic logic
Very difficult
Very bad Good Good average
10: Circuit Families 109
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Circuit Pitfalls Threshold drops Ratio failures Charge sharing Power supply noise Coupling Minority carrier injection Back-gate coupling Diffusion input noise sensitivity Race conditions Delay matching
10: Circuit Families 110
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Circuit Pitfalls Metastability Hot spots Soft errors Process sensitivity
10: Circuit Families 111
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Threshold Drops
10: Circuit Families 112
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Ratio Failures
10: Circuit Families 113
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Power Supply Noise
10: Circuit Families 114
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Hot Spots Caused by nonuniform power dissipation even when
the overall power consumption is within budget. Causes variation in delay between gates. Full-chip temperature simulation is required.
10: Circuit Families 115
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Minority Carrier Injection
10: Circuit Families 116
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Minority Carrier Injection
Sometimes, a node voltage can momentarily exceed power supply voltages.
Then, the drain-body junction becomes forward biased.
Noise tools can identify potential problems.
10: Circuit Families 117
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion Input Noise Sensitivity
10: Circuit Families 118
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion Input Noise Sensitivity
Exposed diffusion inputs are particularly sensitive to noise.
Standard cell latches should be built with buffered inputs.
In data paths, one can still utilize exposed diffusion inputs since one knows the structure.
10: Circuit Families 119
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Domino Noise Budgets Charge leakage Charge sharing Capacitive coupling Back-gate coupling Minority carrier injection Power supply noise Soft errors Noise feedthrough Process corner effects
10: Circuit Families 120
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Domino Noise Budgets
Source Dynamic Output Dynamic Input
Charge Sharing 10 n/a
Coupling 17 7
Supply Noise 5 5
Feedthrough Noise 5 7
Total 37% 19%
10: Circuit Families 121
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Silicon-on-Insulator Circuit Design
SOI technology has been around for decades as research.
It was adopted by IBM for PowerPC in 1998. Potential for higher performance and lower power
consumption. Higher manufacturing cost and more complicated
circuit design due to unusual transistor behavior. There is no bulk, but insulator. Body is floating, thus changes in Vt.
10: Circuit Families 122
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SOI Inverter Cross Section
10: Circuit Families 123
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SOI Process Electron Micrograph
10: Circuit Families 124
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SOI Circuit Design SOI devices are characterized as
– Partially Depleted (PD)– Fully Depleted (FD)
In FD SOI, the body is thinner than the channel depletion width, so the body charge is fixed. Thus, the body voltage does not change.
In PD SOI, the body is thicker and its voltage can vary depending on how much charge is present. This varying body voltage changes Vt.
FD SOI is difficult to manufacture.
10: Circuit Families 125
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Paths in SOI Body
10: Circuit Families 126
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Charge Paths There are two paths through which charge can build up in the
body:
– Reverse biased drain-to-body (Ddb) and possibly source-to-body (Dsb) junctions.
– High-energy carriers causing impact ionization, creating electron-hole pairs. Some electrons are injected into the gate or gate oxide, leaving holes behind.
The charge can exit the body through two paths:
– As body voltage increases, Dsb becomes slightly forward biased. Eventually, this cancels the first mechanism above.
– A rising gate or drain voltage capacitively couples the body voltage upward, too. This strongly forward biases Dsb junction and charge spills out.
10: Circuit Families 127
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SOI Advantages Lower diffusion capacitance.
– Smaller parasitic delay and lower power consumption.
Potential for lower threshold voltages.
– Vt is dependent on channel length for bulk CMOS. Thus, worst case conditions are selected in determining Vt. In SOI, variations are smaller, thus smaller Vt can be chosen.
Lower n, hence better subthreshold slope.– n decreases from 1.5 to about 1.2.
SOI is immune to latchup.10: Circuit Families 128
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SOI Disadvantages PD SOI suffers from history effect.
– 8% variation in gate delay.– Can be a problem for sensitive analog circuits.
Presence of a parasitic bipolar transistor.– If the source and drain are held high for an
extended period of time while the gate is low, the base will float high due to leakage.
– If the source is pulled low, the npn turns ON, creating a pulse of current.
– This is sometimes called pass-gate leakage. Self-heating => oxide is an insulator for heat as well.10: Circuit Families 129
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Parasitic BJT in SOI
10: Circuit Families 130
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Implications for Circuit Styles
SOI is attractive for fast CMOS logic.– Lower delay, lower power consumption.
Standard CMOS design suffers slightly from history effect.
Dynamic circuits suffer from pass-gate leakage. Many precautions must be taken.
Analog circuits suffer from threshold mismatches.
10: Circuit Families 131
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Subthreshold Circuit Design
As discussed earlier, the minimum energy point is at a region where VDD < Vt.
Typically, around 300 mV. Frequency is in the high kHz or low MHz region. Vt variations are very important, use large transistors
where possible. Use standard CMOS, but avoid complex gates. Not
more complex than NAND3. Due to variations, ON current in one branch may be smaller than OFF current in the series stack.
10: Circuit Families 132
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Pitfalls and Fallacies Failing to plan for advances in technology Comparing a well-tuned new circuit to a poor
example of engineering practice Ignoring driver resistance when characterizing pass-
transistor circuits. Reporting only part of the delay of a circuit Making outrageous claims about performance Building circuits without adequate verification tools. Sizing subthreshold circuits for speed
10: Circuit Families 133
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Historical Perspective Ratioed and dynamic circuits are actually earlier
than CMOS. In an NMOS process, PMOS transistors were not
available. Dynamic gates were proposed in early 1970’s. Even with CMOS, domino gates were still used for
area and power advantages, for example in BELLMAC-32A from Bell Labs.– The world’s first 32-bit microprocessor
10: Circuit Families 134
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Historical Perspective By the time of Alpha 21264, leakage had become so
important that keepers had to be used. – 1996, superscalar, out-of-order execution
180 nm Pentium 4 used self-resetting domino. 90 nm Pentium 4 used extraordinarily complex LVS
logic. Custom design of 6.8M transistors. Japanese engineers favored pass transistor logic all
through 1990’s. IBM has always relied on static CMOS. Hundreds of logic families in academic literature, but
very few have found application in industry.
10: Circuit Families 135