1. nMOS TRANSISTOR ANALYSIS

1.1. ObjectiveThe objective of this project is to design and simulate a nMOS transistor using Cadence (IC design software). The design will be in the form of a logic circuit and to study the VTC .

1.2 . Schematic of nMOS transistor:

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Figure 1: nMOS transistor Schematic Simulated Waveform

2. nMOS TRANSISTOR ANALYSIS

2.1. Objective

The objective of this project is to design and simulate a nMOS pass transistor using Cadence (IC design software). The design will be in the form of a logic circuit and to study the VTC.

1.2 . Schematic of nMOS transistor:

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Figure 2: nMOS pass transistor Schematic Simulated Waveform

3. NOR GATE ANALYSIS3.1. ObjectiveThe objective of this project is to design and simulate a nor gate using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

3.2. Schematic of nMOS transistor:

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Figure 3: NOR gate Schematic Simulated Waveform

Figure 4: NOR gate layout

4. NOR GATE ANALYSIS4.1. ObjectiveThe objective of this project is to design and simulate a nor gate using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

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4.2. Schematic of nMOS transistor:

Figure 5: OR gate layout

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Figure 6: NOR gate Schematic Simulated Waveform

5. NAND GATE ANALYSIS5.1. ObjectiveThe objective of this project is to design and simulate a nand gate using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

5.2. Schematic of nand gate:

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Figure 7: NAND gate Schematic Simulated Waveform

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Figure 8: NAND gate layout

6. AND GATE ANALYSIS6.1. ObjectiveThe objective of this project is to design and simulate a and gate using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

6.2. Schematic of and gate:

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Figure 9:AND gate layout

Figure 10: AND gate Schematic Simulated Waveform

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7. INVERTER ANALYSIS7.1. ObjectiveThe objective of this project is to design and simulate an inverter using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

7.2. Schematic of inverter:

Figure 11:Inverter layout

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Figure 12: INVERTER voltage transfer characteristics

Figure 13 :Parametric Analysis to determine size of transistors

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8. XOR GATE ANALYSIS8.1. ObjectiveThe objective of this project is to design and simulate a xor gate using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

8.2. Schematic of xor gate using standard cells.

Figure 14: XOR gate Schematic Simulated Wavefor

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Figure 3: Schematic of xor gate using custom cells

Figure 15:XOR layout

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Figure 16: Schematic of xor gate using transistors

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Figure 17: Schematic of xor gate using 5 transistors

Figure 18: XOR gate Schematic Simulated Waveform

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9. D LATCH ANALYSIS9.1. ObjectiveThe objective of this project is to design and simulate a D latch using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

9.2. Schematic of D latch using standard cells.

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Figure 19: D latch Schematic Simulated Wavefor

10. Flip-Flop Design

A Flip-flop is the name given to two-state devices which offer basic memory for sequential logic operations. Flip-flops are synchronous bistable devices that operate as memory elements. A flip-flop circuit contains two outputs, one is for the normal value and the other is for the complement value of the stored bit. Flip-flops are used for digital data storage and transfer and are commonly used in banks called "registers" for the storage of binary numerical data.

10.1 ObjectiveThe objective of this project is to design and simulate a J-K Flip-Flop and a D-Flip Flop using Cadence (IC design software). The design will be in the form of a logic circuit and a layout

10.2. J-K Flip Flop I will be designing a J-K flip flop with a set/reset option. The outputs will only change state on the falling edge of the CLK signal, and the J and K inputs will control the future output. If both the J and K inputs are held at logic 1 and the CLK signal continues to change, the Q and Q' outputs will simply change state with each falling edge of the CLK signal.

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10.3. D Flip Flop I also will be designing a negative edge triggered D Flip-Flop. The outputs’ states to change only when the clock signal falls from logic ‘1’ to logic ‘0’.

10.4. Design Implementation and SimulationI designed the J-K Flip Flop and the D Flip-Flop using Cadence IC Design Software.

10.5. Schematic Design10.5.1. D FLIP FLOP

Figure 20: D Flip Flop Schematic

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Figure 21: D Flip Flop Schematic stimulated waveform

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Figure 22: D Flip Flop Schematic using Blocks

Figure 23: D Flip Flop Schematic stimulated waveform

10.5.2. JK FLIP FLOP

Figure24: J-K Flip Flop Schematic

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Figure 25: J-K Flip Flop Schematic Simulated Waveform

10.5.3. T FLIP FLOP

The implementation of the flip flop consists of the following steps: Designing the schematic

Performing pre layout simulations

Designing the layout Obtaining the extracted view

Performing LVS

Performing post layout simulations

SCHEMATIC OF T FLIP FLOP:

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PRELAYOUT SIMULATION RESULTS:

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LAYOUT OF T FLIP FLOP:

POST LAYOUT SIMULATION RESULTS:

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11. D LATCH ANALYSIS11.1. ObjectiveThe objective of this project is to design and simulate a D latch using Cadence (IC design software). The design will be in the form of a logic circuit and its waveform is observed.

1.1. Schematic of D latch using standard cells.

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Figure 26: BUFFER Simulated Waveform

12. DESIGN OF COUNTERS

12.1. Objective:

The objective of this project is to design a 8-bit counter and implement it into a chip with the help of Cadence (custom IC design tool) following necessary steps and rules dependent on selected process technology.

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Figure 27. Schematic of 8-bit counter:

Figure 28: 8-Bit Counter Simulated Waveform-1

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Figure 29: 8-Bit Counter Simulated Waveform-2

Schematic of 4-bit counter:

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Figure 30: Schematic of 4-bit counter:

Figure 31: 4-Bit Counter Simulated Waveform

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Required Basic building blocks:

J K Flip-flop: Master slave JK flip flop used in for this circuit for reliable

operation and stability. The flip flop triggers at negative edge of the clock cycle.

Truth table for the JK flip flop is given below:

Schematic of JK flip flop:

Figure 32: Schematic diagram of JK flip flop with set and reset assembly

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Simulated output:

13. ADDER DESIGN13.1. Objective

The objective of this project is to design and simulate a half and full adder using Cadence (IC design software). The design will be in the form of a logic circuit.

13.2. HALF ADDER

An implementation of an adder is shown below:

S=A ⊕ B

Cout=AB

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Figure33. Schematic of half adder

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13.3. FULL ADDER

An implementation of an adder is shown below:

S=A ⊕ B ⊕ Cin

Cout=AB+ (A ⊕ B) Cin

Figure 34. Schematic of a Full Adder.

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