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Lab 6 Program Control. Mano & Kime Sections 7-9, 7-10, 8-1. Lab6 Fall 2002 Pcontrol. Richard E. Haskell Oakland University Rochester, MI 48309. Program Controller, Pcontrol. library IEEE; use IEEE.std_logic_1164. all ; use IEEE.std_logic_arith. all ; use work.opcodes. all ;. - PowerPoint PPT Presentation
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Lab 6 Program Control
Mano & Kime
Sections 7-9, 7-10, 8-1
mux4
Tregclkclr
Nregclkclr
Funit1
T
N
tload
nload
tin
Pcontrol
Prom
pinc
M
P
nload
tload
icodemsel(1:0)
DigDisplay
A(1:4) AtoG(6:0)
SW(1:8)
LD(1:8)
clk
clr
T
T
N
digload
fcode(5:0)
BTN4
iregclkclr iload
digload
iloadfcode(5:0)
pinc
mclk clkdiv
clr
clk
M
clr
clk
PCclkclr pload
pload
y
yM
abcd
bn
cclk
IBUFG
ab
T
ldg‘1’
led
Lab6
debounce
cclk
Lab6Fall 2002Pcontrol
Richard E. HaskellOakland UniversityRochester, MI 48309
Program Controller, Pcontrol
library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.opcodes.all;
Note: working directory
opcodes package
entity Pcontrol is port ( icode: in STD_LOGIC_VECTOR (15 downto 0); M: in STD_LOGIC_VECTOR (15 downto 0);
T: in STD_LOGIC_VECTOR (15 downto 0); clr: in STD_LOGIC; clk: in STD_LOGIC; BTN4: in STD_LOGIC; fcode: out STD_LOGIC_VECTOR (5 downto 0); msel: out STD_LOGIC_VECTOR (1 downto 0); pinc: out STD_LOGIC; pload: out STD_LOGIC; tload: out STD_LOGIC; nload: out STD_LOGIC; digload: out STD_LOGIC; iload: out STD_LOGIC );end Pcontrol;
PROMI reg
M
icode
X“010D"
X"0000" X"0000"
RESET
fetchpinc = ‘1’iload = ‘1’
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X"0000”
X“010D" X”0001”
fetchpinc = ‘1’iload = ‘1’
execDecodeicode
Don’t fetch
JB4HIconstant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icodeX“010D"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0002”
X“0109"
PROMI reg
M
icode
X"0002"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
JB4LOconstant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0003”
PROMI reg
M
icode
X“0037"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0004”
PROMI reg
M
icode
X“0038"
X“0037"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
exec_fetch
SFETCH
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0005”
PROMI reg
M
icode
X"010D"
X“0038"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
DIGSTORE
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0006”
PROMI reg
M
icode
X"0006"
X“010D"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
JB4HI
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0007”
PROMI reg
M
icode
X"010D"
X“010D"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
JB4HI
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0006”
PROMI reg
M
icode
X"0006"
X“010D"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
JB4HI
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0007”
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0109"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
X”0008”
PROMI reg
M
icode
X"0008"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
JB4LO
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0009”
PROMI reg
M
icode
X“0109"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0008”
PROMI reg
M
icode
X"0008"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
JB4LO
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0009”
PROMI reg
M
icode
X"0018"
X“0109"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
3B T reg
exec_fetch
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”000A”
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0001"
X"0018"
fetch
exec
3B T reg
exec_fetch
twotimes
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
X”000B”
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0018"
X"0001"
fetch
exec
76 T reg
exec_fetch
DUP
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
X”000C”
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0018"
X"0018"
fetch
exec
76 T reg
exec_fetch
twotimes
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
X”000D”
76 N reg
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0010"
X"0018"
fetch
exec
EC T reg
exec_fetch
twotimes
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
X”000E”
76 N reg
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0038"
X"0010"
fetch
exec
1D8 T reg
exec_fetch
plus
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
X”000F”
76 N reg
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
PROMI reg
M
icode
X“0101"
X"0038"
fetch
exec
24E T reg
exec_fetch
digstore
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
X”0010”
76 N reg
PROMI reg
M
icode
X"0000"
X“0101"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
exec_fetch
JMP
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0011”
24E T reg
76 N reg
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
PROMI reg
M
icode
X"010D"
X“0101"
fetchpinc = ‘1’Iload = ‘1’
execDecodeicode
Don’t fetch
exec_fetch
constant rom: rom_array := (
JB4HI, X"0000",
JB4LO, X"0002",
SFETCH,
digstore,
JB4HI, X"0006",
JB4LO, X"0008",
twotimes,
DUP,
twotimes,
twotimes,
plus,
digstore,
JMP, X"0000",
X"0000"
);
X”0000”
24E T reg
76 N reg
M(8)=‘1’M(8)=‘0’
M(8)=‘0’ M(8)=‘1’
Lab6 Pcontrol ControllerMealy Machine
Sta
te R
egis
ter
C1
icodetz
s(t+1)
s(t)
clk
clr
current state
nextstate
C2
process(clk, clr)
process(current_state, M)
process(current_state, icode, t, z)
M
architecture Pcontrol_arch of Pcontrol is type state_type is (fetch, exec, exec_fetch);signal current_state, next_state: state_type; synch: process(clk, clr) begin if clr = '1' then current_state <= fetch; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process synch;
C1: process(current_state, M)begin case current_state is when fetch => if M(8) = ‘1’ then next_state <= exec; else next_state <= exec_fetch; end if; when exec_fetch => if M(8) = ‘1’ then next_state <= exec; else next_state <= exec_fetch; end if; when exec => next_state <= fetch; end case;end process C1;
fetch
execexec_fetch
M(8)=‘1’M(8)=‘0’
M(8)=‘0’
M(8)=‘1’
W8X ControllerMealy Machine
Sta
te R
egis
ter
C1
icodetz
s(t+1)
s(t)
clk
clr
current state
nextstate
C2
process(clk, clr)
process(current_state, M)
process(current_state, icode, t, z)
M
C2: process(instr, current_state, BTN4) begin alusel <= "00"; msel <= "00";
pload <= '0'; tload <= '0'; nload <= '0'; digload <= '0';
inc <= '1'; iload <= '0'; if (current_state = fetch) or
(current_state = exec_fetch) then iload <= '1'; -- fetch next instruction end if; if (current_state = exec) or
(current_state = exec_fetch) then case instr is
when nop => null;
when dup => nload <= '1';
when plus => tload <= '1';
when plus1 => tload <= '1'; fcode <= icode(5 downto 0);
when invert => tload <= '1'; fcode <= icode(5 downto 0);
when twotimes => tload <= '1'; fcode <= icode(5 downto 0);
when sfetch =>
tload <= '1'; msel <= "01"; when digstore => digload <= '1'; when jmp => pload <= '1'; inc <= '0'; when jb4LO => pload <= not BTN4; inc <= BTN4; when jb4HI => pload <= BTN4; inc <= not BTN4;
when others => null;
end case; end if; end process C2;
Lab6Fall 2002Pcontrol
Richard E. HaskellOakland UniversityRochester, MI 48309
mux4
Tregclkclr
Nregclkclr
Funit1
T
N
tload
nload
tin
Pcontrol
Prom
pinc
M
P
nload
tload
icodemsel(1:0)
DigDisplay
A(1:4) AtoG(6:0)
SW(1:8)
LD(1:8)
clk
clr
T
T
N
digload
fcode(5:0)
BTN4
iregclkclr iload
digload
iloadfcode(5:0)
pinc
mclk clkdiv
clr
clk
M
clr
clk
PCclkclr pload
pload
y
yM
abcd
bn
cclk
IBUFG
ab
T
ldg‘1’
led
Lab6
debounce
cclk
