L11 Circuit Analysis

8/7/2019 L11 Circuit Analysis

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LPVD Lecture-11

Lecture-11

POWER ANALYSIS AT CIRCUIT-LEVEL

Dr. Arti Noor

M. Tech (VLSI) Division, CDAC Noida UP.

29-3-2011


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Topics

Network Restructuring and Reorganization.

Transistor network restructuring.

Transistor network partitioning and

reorganization.

Special Latches and FFs.

Low Power Digital Cell Library.


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Network restructuring and Reorganization

If signal probabilities are known, then restructuring of transistors mayresult in low power.

Various transistor reordering techniques :

Transistor Network Restructuring:

Boolean functions are composed of AND and OR gates. To realize anyBoolean function, one can map it on complex logic gates directly.

The mapping steps are :

-- Each variable corresponds to N and P transistor pair,

-- For N-Network : serial connection corresponds to AND while parallel

OR operator.-- P-network is just reverse of N-network.

-- Inverter optionally can be added.

Example : Y= AB+C


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Network restructuring summary

Same function can be implemented in different

ways. This results in different timing and powerconsumption.

To do the analysis of timing and power.

As a general rule : put transition involving

transistors near to output node because often

these have less delay and consume less power.

Therefore, one has to calculate transition

probability at each input node to evaluate thecircuit.

A switching level simulation is used to select best

implementation.


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Transistor Network Partitioning and Reorganization

Restructuring operation is applied on single complex logic

gate.

In place of CMOS gate now consider transistor network.

Partitioning and reorganization concept can be applied to

trade-off between power and delay.

Network reorganization is composing different transistors

network that can implement same functionality.

Large Boolean function can not be implemented in single

complex gate because of series and parallel connection

limit of transistors. The exact limit of transistors depends upon technology,

system speed, supply voltage.


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Network Reorganization

With a given technology and serial connection

constrains, the aim is to partition and reorganizecircuit for better performance.

Example:


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Network Reorganization

The choice of network structure increases

exponentially with circuit size for best result. For large network hand calculation is not

possible.

CMOS complex gate generated by reorganization

can not be predesigned.

Sizing each transistor of gate needs a tool for

automatic layout simulation.

Power and timing analysis to be performed attransistor level which is computation intensive.

Sophisticated CAD tools are required at physical

level.


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Special Latches and FFs

Latches and FFs are basic elements used in synchronous

circuits and decide the maximum speed of the system. FFs are clocked at the system and thus consumes large

amount of power.

FFs energy dissipation has two parts :

Clock energy : dissipated when FF is clocked and data isunchanged.

Data Energy : addition to clock energy due to different

data writing in FF.

Normally Data rate is much lower than clock rate and thuspower saving techniques concentrate on clock energy

reduction. In addition to voltage reduction, capacitance

reduction and change in transistor count to minimize

switching techniques are used to reduce the power.


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Flip-Flop and Latch Circuits

Flip-flop and latch can be implemented in different waysand each design varies in terms of area, delay and power

consumption.

The NMOS transistor in place of TG eliminates two phase

non overlapping clock, reduces load capacitance at the

cost of speed and threshold voltage loss.

Similarly single phase FF is suitable for low power

implementation as compared to two phase clock.

One has to do SPICE level simulation after including

transistor sizing techniques to select the bestimplementation of Latches and FFs.


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FF contains differential feedback

circuit to drive RS latch.

Four transistors form cross-coupled

feedback inverters.

RS inputs are precharged and

selectively discharged at

rising edge of clock.

The RS latch retains data

when clock is low during precharge.

T provides a path to GND andprevents latch to have intermediate

values. Only three transistors are

connected to clock and no static

Current when clk stopped.


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Self Gating FF

Some part of clock energy is consumed by internal clock buffer tocontrol TGs.

If there is no change in data then power can be saved bysuppressing the clock switching.

Power is saved by holding the internal clock signal while externalclock of FF switches.


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Flip-Flop and Latch Circuits Self Gating FF

The below figure shows this idea. TG at Clk is used to gate the external clock so that internal clock J and

Jbar do not switch if not required.

When D and Q are different

XOR output is one to pass clk.

When J is high TG is off to stop

unnecessary switching

unless D and Q are different.


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Self Gating FF

This circuit uses more area and delay, but if input

switching probability is very low as compared to clock

rate then probability of clock disabling is very high.

The power dissipation depends on transition frequency of

Td and Tclk. When it is less than one, power saving is

more. when it is zero, no dynamic power consumption by

this circuit.


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Double edge triggered FF

Data can be latched on both rising and falling edge of clock. Clock

frequency can be halved to achieved same throughput compared to

single edge triggered FF.

More area is required but FF retains data when clock is not toggling.

Comparison of both FFs

SETFF

Esc: energy consumed due to clock Esd: energy consumed due to data.

fc: clock frequency and fd is FF

output frequency.

dsdcscs fEfEP !


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Flip-Flop and Latch Circuits DETFF

Normally fd is very small as compared to fc. DETFF area is more as

SETFF, so energies are also larger in this case.

If Esc=Esd; Edc = 1.3Esc, Edd=1.3Esd, fd=0.4fc then

DETFF is working at half frequency, so over all 2X time power savingin clock distribution network.

Esc/Edc ratio is important at the time of circuit design.

dddcdcd fEfEP !5.0

scscd

cscs

PfEP

fEP

84.017.1

4.1

!!

!


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Low Power Digital Cell Library

Most circuits are synthesized at gate level to meet the

various specifications.

At gatelevel the basic building blocks are gates or cells.

Quality of gate level synthesis depends upon quality of

cell library.

Therefore, low power cells are added in library to meet

the power specification.


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Cell Sizes and Spacing

In top-down cell based design, one has to do trade-off among area,delay and power by selecting the appropriate sizes of cells.

Therefore for good low power cell library, one should have cells of

wide range sizes.

The number of gates of different sizes is approximately four times of

traditional cell library for low power. Spacing of cell sizes should be chosen carefully.

Capacitance distribution profile is considered for spacing.

Example : normally net capacitance is within 0.1-0.5pF, thus more cell

sizes should be available to drive this range.

Because of low range of capacitance, lower drive cells should bespaced closer than higher drive cells like :1X,2X, 3X,5X, 8X, 12X.


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Varieties of Boolean Functions

After size and spacing the next consideration is on how many

Boolean functions of given inputs (n-inputs) exist.

For n-input, one has 2n entries at output side with different 0 and 1

combinations.

Each combination is unique Boolean function thus one can write

M is very large for small values of n. For n=3, M=28, thus for n>3 small

number of M Boolean functions are available in cell library. TypicallyOR, AND, XOR, AOI, and OAI are available.

n

M2

2!


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Lack of variety of functions

results in inferior circuits.

Implement Y without having inverted input cells and with inverted

input cells. Compare which cell will take less area and power.

M functions can not be implemented but how many function should

be sufficient for a rich library?

Among M some are degenerated : output dose not depend on all input

variables. Among non-degenerated some are identical like

BAY !

BAYBAY !!


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Equivalence of Functions :

Permutation of input variables.

Negation of input variables.

Negation of output


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P-Equivalence Some Boolean function are P equivalent (one

function can be obtained from other by permuting

the inputs)

Letf(X) andg(X) be two functions and X = {x1, x2,, xn}

Then g(X) = f(V (X))

whereV is a permutation of X


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P-Equivalence (Permutation of input variables) Example

This can be used to reduce the number of function by having Pequivalence classes.

BACYCABY !! ;

)()(

;;;maps

;

34431221

31424231

xfxg

xxxxxxxx

xxxxgxxxxf

V

V

!

pppp

!!


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N-Equivalence (Negation of input variables) Letf(X) andg(X) be two functions and X = {x1, x2 ,, xn}

Then

g(X) = f(N(X))

where Nmaps eachxito itself or its complement

Example :

)()(

;;;maps

;

332211

321321

xfxg

xxxxxx

xxxgxxxf

J

J

!

ppp

!!


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N-Equivalence (Negation of output)

ABYABY

BAYandBAYABY

!}!

!!}!

)(f)(

.

)(fg(X))()(

2121

XXg

xxgandxxf

XorXfXg

!

!!

!!


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NPN-equivalent :

equivalent under input Negation, input Permutation,

output Negation

NP-equivalent :equivalent under input Negation, input Permutation

P- equivalent :

equivalent under input Permutation

The cell library which covers the more classes , produces

circuits with better quality.


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LPVD Lecture-11

Adjustable Device Threshold Voltage

When one reduces the supply voltage how it affects delay and

performance.

When Vdd is closer to Vt, performance decreases rapidly and

becomes limiting factor. Thus one has to scale Vt also.

But proportionally one can not scale Vt. Because of reduction in

subthreshold current and process variation.

))(1(1

)(

max

2

tdd

dd

t

d

tdd

dd

d

VVVV

t

f

VV

Vt

ww

w


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Adjustable Device Threshold Voltage

One solution is use different Vt devices on the same chip. Speed critical devices operate at low Vt while others at

high Vt.

For this additional mask is needed to identify the low Vtdevices.

Another method is control Vt by Body bias voltage.

Additional mask is not needed but the Vt stability is poorand bias voltage generation circuit need additional power.


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Assignment

Use Shannon Decomposition theorem to

find probability and transition densityfunction.

Submission date 4-4-2011

y=a+bc


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Assignment

Draw the 2 input function under P, NP and

NPN equivalence.

Date of submission 11-4-2011.


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Next Topic

Power optimization techniques at LogicLevel (chapter-5 Yeap)

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L11 Circuit Analysis