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conducted
(JoVDTT)
Journal of
www.stmjournals.comSTM JOURNALSScientific Technical Medical
STM JOURNALSScientific Technical Medical
STM JOURNALSScientific Technical Medical
Jan - April 2014 ISSN: 2321-6492
Ÿ A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Ÿ Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and
88–108 MHz Wireless System for Multi Standard Receiver
Ÿ Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder
Ÿ Methodology of Standard Cell Library Design in .LIB Format
Ÿ A New Current Mode Quadrature Oscillator using Current Differencing Transconductance
Amplifier (CDTA)
VLSI Design Tools
& Technology
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Journal of VLSI Design Tools & Technology
Journal of VLSI Design Tools & Technology
(ISSN: 2321–6492)
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Industrial Tribology Machine Dynamics & Maintenance
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Indian School of Mines, Dhanbad, India.
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I take the privilege to present the hard copy compilation for the [Volume 4 Issue (1)] of Journal of
VLSI Design Tools & Technology (JoVDTT). The intension of JoVDTT is to create an atmosphere
that stimulates creativeness, research and growth in the area of VLSI Design Tools & Technology.
The development and growth of the mankind is the consequence of brilliant Research done by
eminent Scientists and Engineers in every field. JoVDTT provides an outlet for Research findings
and reviews in areas of VLSI Design Tools & Technology found to be relevant for National and
International recent developments & research initiative.
The aim and scope of the Journal is to provide an academic medium and an important reference for
the advancement and dissemination of Research results that support high level learning, teaching and
research in the domain of VLSI Design Tools & Technology.
Finally, I express my sincere gratitude and thanks to our Editorial/ Reviewer board and Authors for
their continued support and invaluable contributions and suggestions in the form of authoring write-
ups/ reviewing and providing constructive comments for the advancement of the journals. With
regards to their due continuous support and co-operation, we have been able to publish quality
Research/Reviesw findings for our customers base.
I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.
Dr. Archana Mehrotra
Director
STM Journals
Director's Desk
STM JOURNALS
1. A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology Vijayanand K, Sureshkumar N 1
2. Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver Kehul A. Shah, N. M. Devashrayee 8
3. Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full AdderA. Unmai 25
4. Methodology of Standard Cell Library Design in .LIB FormatArindam Sadhu, Pritam Bhattacharjee 30
5. A New Current Mode Quadrature Oscillator using Current Differencing Transconductance Amplifier (CDTA)Md. Hassan and Sajal K. Paul 39
ContentsJournal of VLSI Design Tools & Technology
JoVDTT (2014)© STM Journals 2014. All Rights Reserved
Journal of VLSI Design Tools & Technology ISSN: 2321-6492
Volume 4, Issue 1
www.stmjournals.com
A Novel Design for Power Reduction in Arithmetic
Circuits using MTCMOS Technology
Vijayanand K1*, Sureshkumar N
2
Info Institute of Engineering, Coimbatore, Tamilnadu, India
Abstract In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation.
Although power consumption is important for modern VLSI design, operation speed and
occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and
low-power design without any area overhead. MTCMOS technology provides the transistors that have low, normal and high threshold voltage. The low-threshold voltage
transistors are used to reduce the propagation delay time in the critical path, the high-
threshold voltage transistors are used to reduce the power consumption in the shortest path. This paper describes a low-power and high speed design for full adder, full
subtractor and 4×4 carry save multiplier circuits with Multi-threshold CMOS
(MTCMOS) technology using Microwind EDA tool.
Keywords: MTCMOS, full adder, full subtractor, CMOS circuit, leakage current, low
power design.
JoVDTT (2014)© STM Journals 2014. All Rights Reserved
Journal of VLSI Design Tools & Technology ISSN: 2321-6492
Volume 4, Issue 1
www.stmjournals.com
Design and Implementation of 2nd
Order Gm-C IF Tuning
Filter Operating at 900 MHz and 88–108 MHz Wireless
System for Multi Standard Receiver
Kehul A. Shah1*, N. M. Devashrayee
2
1Department of Electronics and Communication, SPCE, Visnagar, Gujarat, India
2Department of Electronics and Communication (VLSI Design), NIRMA University,
Ahmedabad, Gujarat, India
Abstract This paper deals with design and optimization of folded cascode OTA-C filter, which
works for frequencies that lead to a base band circuit design for RF application, is based
on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded
cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around
400 MHz. Design of CMOS Gm-C 2nd order Biquad Filter implementation using OTA, operating at center frequency 70 and 10.6 MHz. The filter can be operated at center
frequency of 70 MHz under 1.8 V power supply and is suitable for intermediate frequency (IF) range in most of the wireless systems operating at 900 MHz GSM and at
88–108 MHz FM.
Keywords: Folded cascode OTA, gm/ID methodology, active filters, S-parameter,
smith chart, OTA-C filters, GSM, FM
JoVDTT (2014)© STM Journals 2014. All Rights Reserved
Journal of VLSI Design Tools & Technology ISSN: 2321-6492
Volume 4, Issue 1
www.stmjournals.com
Low Power 8-Bit Square Root Carry Select Adder
Constructed By Using 8 Transistor Full Adder
A. Unmai* Department of Electronics and Communication, Info Institute of Engineering,
Coimbatore, Tamil Nadu, India
Abstract Carry select adder is the high speed adder which is designed to speed up arithmetic
operations and to reduce the computation time. Carry select adder is used to perform fast arithmetic functions in data processing processors. Low power consumption, reduced
area, reduced delay and increased speed are the most important features of the modern electronic system design. In this proposed work, 8 transistor full adder (8T full adder) is
used as the building block for the 8-bit square-root carry select adder (8-b SQRT CSLA).
This 8T full adder is designed by XNOR-XNOR hybrid CMOS design. So it is reliable in terms of power, area and speed. In this 8-b SQRT CSLA design power consumption is
reduced compared with the regular carry select adder (CSLA). In this work performance
is evaluated through the logic design and layout in 0.12 µm CMOS process technology.
Keywords: Low power consumption, 8T full adder, XNOR-XNOR hybrid CMOS
design, DSCH (digital schematic)
JoVDTT (2014) © STM Journals 2014. All Rights Reserved
Journal of VLSI Design Tools & Technology ISSN: 2321-6492
Volume 4, Issue 1
www.stmjournals.com
Methodology of Standard Cell Library Design
in .LIB Format
Arindam Sadhu, Pritam Bhattacharjee* Department of Electronics & Communication Engineering - Microelectronics & VLSI, Heritage
Institute of Technology, Kolkata, India
Abstract The importance of standard cell library design methodology is growing with very-large-scale integration (VLSI) technology advancement due to its usage in VLSI EDA synthesis
flows. In this paper, to best of our knowledge and information in any published
literature no systematic method of standard cell and creating appropriate co-laterals. In this paper the standard cell design methodology, layout topology, methodology for
creating characterized timing table has been developed using 250 nm technology
GPDK. This method can be easily reused in deep sub-micron technology for appropriate co-laterals. In addition a new methodology of reusing standard cell for full custom
design has been proposed in this paper.
Keywords: 250 nm technology GPDK, standard-cell library design, .lib formulated
characterization
JoVDTT (2014)© STM Journals 2014. All Rights Reserved
Journal of VLSI Design Tools & Technology ISSN: 2321-6492
Volume 4, Issue 1
www.stmjournals.com
A New Current Mode Quadrature Oscillator using
Current Differencing Transconductance Amplifier
(CDTA)
Md. Hassan and Sajal K. Paul* Department of Electronics Engineering, Indian School of Mines, Dhanbad, India
Abstract This paper proposed a new current-mode quadrature oscillator using CDTA (Current Difference Transconductance Amplifier) as the active element. The proposed circuit uses
only two grounded or virtually grounded capacitors, two grounded or virtually grounded
resistors and two CDTAs. The functionality of the circuit is verified with the PSPICE simulation results.
Keywords: CDTA, quadrature oscillator, current mode