Introduction to VLSI Testing and Design For Testability(DFT) TESTING...• Design for testability (DFT) – Chip area overhead, i.e., yield loss – Performance overhead, i.e., degradation

「DIP概論」－IP Testing

淡江大學電機工程學系

饒建奇

jcraucsccuedutw教育部顧問室

「超大型積體電路與系統設計」教育改進計畫 DIP聯盟

教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系饒建奇 2

「DIP概論」－ IP Testing

Text Books

bull M L Bushnell and V D Agrawal Essentials of Electronic Testing for Digital Memory amp Mixed-Signal VLSI CircuitsKluwer Academic Publishers 2000

bull M Abramovici M A Breuer and A D Friedman Digital Systems Testing and Testable Design Computer Science Press New York 1990



Outline (12)

bull Introductionbull Fault Modelsbull Fault Simulationbull Test Generation (TG)bull Design for Testability (DFT) bull Advanced Scan Concepts



Outline (22)

bull Compression Techniquesbull Built-In Self-Test (BIST)bull Boundary-Scan Testingbull Memory Testingbull SOC Testing

Chapter 1

Introduction



VLSI Development FlowDetermine specification

Design the circuit

Verify the design

Develop the test procedure

Manufacture the circuit

Test the manufactured circuit

Deliver to customers

Design Errors

TestPlans



Why Do Circuits Fail

bull Human design errorsbull Manufacturing defects bull Package defectsbull Field (Environment) failures

ndash Temperature humidity power etc

verifytest

testtest



Verification vs Testingbull Verification

ndash Check for the correctness of a designbull Simulation

ndash Performed oncebull Testing

ndash Check the correctness of the manufactured circuitndash Performed repeatedly

Verification Testinglogicsoft faults realhard faults



Why Testing

bull Detect and eliminate (hard-)faulty circuits

Vdd

10

00

0

0

fault-free circuit faulty circuit



How to Do Testing

Circuit Under Test

(CUT)

Test Pattern Generator

(TPG)

Output Response Analyzer(ORA)

test patterns T

outputresponses R

GoodBad



Related Terminologies in Testing

bull Diagnosisndash Depict the faulty sites

bull Reliabilityndash Tell whether a ldquogoodrdquo circuit will work after

some time



Importance of Testing

N the number of transistors in a circuit (chip)p the probability that a transistor is faultyPf the probability that the chip is faulty

Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632



Key Issues in Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

Fault Modeling Design for Testability

Test GenerationProblem

Good if R = RrsquoBad if R ne Rrsquoexpected

responses Rrsquo



Circuit Modeling

bull Describe the behavior of circuitsndash Behavior modelndash RTL modelndash Gate level modelndash helliphellip

clocks (edgelevel-sensitive)delaytiming

algorithms



Fault Modeling

bull Describe the effects of physical faultsbull Fault model requirements

ndash Adequately represent actual faultsndash High coverage against physical faultsndash Well-behavedndash Simple enough to use in practice

bull Eg Fault simulation test generation



Fault Modelsbull Single stuck-at fault model

ndash Any single line x is stuck at 0 or 1bull Multiple stuck-at fault model

ndash Several lines x are stuck at 0 or 1bull Delay fault model

ndash Delay of a single path is changedbull Bridging fault model

ndash Signals x and y become AND(x y) or OR(x y)bull helliphellip



Single Stuck-at Fault Model (12)

bull Depict that ldquoone single linerdquo is permanently stuck at 1 or 0

EA

B

C

D F

G

A s-a-1A s-a-0E s-a-1E s-a-0

B s-a-1B s-a-0F s-a-1F s-a-0

C s-a-1C s-a-0G s-a-1G s-a-0

D s-a-1D s-a-0

14 faults



Single Stuck-at Fault Model (22)bull Advantages

ndash Match the gate level and are well-behavedndash The number of possible faults is relatively smallndash Tests for single stuck-at faults give good coverage of

permanent faultsbull Disadvantages

ndash Dose not account for some physical fault effectsndash Few physical faults behave exactly like single-at faults



Detectability of Faults

bull A fault f is said to be detectable if there exists a test vector x such that Cf(x) ne C(x) ie f is ldquodetectedrdquo by x

Vdd

10

00

0

0

fault-free circuit C fault f is detected by (00)

xf s-a-1



Fault Coverage (FC)FC =

the size of fault listnumber of detected faults

CA

B

6 faultsA0 A1 B0 B1 C0 C1

test vector set detected faults FC(0 0)(0 1)(1 1)(0 0) (1 1)(1 0) (0 1) (1 1)

C1A1 C1A0 B0 C0A0 B0 C0 C1ALL

1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts

Shipped PartsDefect Level(DL)

bull Yield (Y) fraction of good partsbull Defect Level (DL) fraction of shipped parts that are defectivebull Quality of shipped parts is a function of Y and FC

DL = 1 ndash Y (1 - FC)

Testing



Circuit Simulationbull Determine how a good circuit should work

ndash Given input vectors determine the normal circuit output responses

EA

B

C

D F

G

1

10

0

01

1

Simulation under the input 1 0 0 0



Fault Simulation (12)

bull Determine the behavior of faulty circuitsE s-a-0 A

B

C

D F

G

1

100

0

01

10

x

Simulation under the input 1 0 0 0 with fault E s-a-0




bull Given a test vector determine all faults that are detected by this test vector

CA

B 1

10

Test vector (1 1) detects A0 B0 C1



Test Generation (12)

bull Given a fault identify a test vector to detect this fault

A

B

C

D s-a-0

E

F

x




bull Sensitizationndash To detect D s-a-0 D must be set to 1

ie A = B = 1bull Propagation

ndash To propagate the fault effect to the output F Emust be set to 1 ie C = 0

Test vector for D s-a-0 is 1 1 0



Automatic Test Pattern Generation (ATPG) (12)

bull Given a circuit identify a set of test vectors to detect all the detectable faults under the considered fault models



Automatic Test Pattern Generation (ATPG) (22)a circuit and the fault list

more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No



Difficulties in Test Generation (12)

bull Reconvergent fanout

A

B

C

D s-a-1

E

F

x



Difficulties in Test Generation (22)bull Sequential test generation

combinational circuit

D

clk

Q

x The fault effect cannot be observed at POs

PIs POs

The test patterns cannotbe generated at PIs



Advanced Test GenerationFC

100

of test patterns

Pseudorandom Test Pattern Generation

Deterministic Test Pattern Generation

Design for Testability (DFT)



Testing Costs

bull Test software developmentndash Automatic test pattern generator (ATPG)ndash Fault simulation and other debugging policies

bull Design for testability (DFT)ndash Chip area overhead ie yield lossndash Performance overhead ie degradation

bull Automatic test equipments (ATEs)



Difficulties in Testing

bull Some real faults are too complex to modelbull Most testing problems are NP-completebull IO access is limitedbull ATEs are expensive

Testing is rarely complete (FC lt 100)



The Goals of Testingbull Detect all expected faults (high fault coverage)bull Diagnose to the smallest replaceablerepairable

component (high fault resolution)bull Fast and low-cost test generationbull Fast and low-cost test applicationbull Efficient response comparisonbull High degree of automationbull Low penalties in hardware overheadperformance

Chapter 2

Fault Models



Faults and Errors

bull Faultsndash Physical defects within a circuit or a systemndash May or may not cause the circuit to fail

bull Errorsndash Manifestation of faults that results in incorrect

circuit or system outputs or statesndash Caused by faults



Failures

bull Deviation of a circuit or a system from its specified behaviorndash Fails to do what it should do ndash Caused by errors

bull Faults Errors and Failures

Faults rArr Errors rArr Failures



Why Model Faultsbull Identify target faults and describe their

effectsbull Limit the scope of test generation

ndash Create test patterns only for the modeled faultsbull Make analysis possible

ndash Compute the fault coverage for specific test patterns

ndash Associate specific faults with specific test patterns



Fault Modelsbull Stuck-at faultsbull Bridging faultsbull PLA faultsbull Transistor stuck-onopen faultsbull Delay faultsbull Functional faultsbull State transition faultsbull Memory faults



Stuck-at Faultsbull Single stuck-at fault model

ndash Only a single line is permanently set to either 0 or 1

bull Multiple stuck-at fault modelndash Several stuck-at faults occur at the same time

bull For a circuit with k linesndash There are 2k single stuck-at faultsndash There are 3k-1 multiple stuck-at faults



Why Single Stuck-at Fault Model (12)

bull Complexity is greatly reducedndash Many different physical defects may be

modeled by the same logical stuck-at faultsbull Technology independent

ndash Can be applied to TTL ECL CMOS etcbull Design style independent

ndash Can be applied to gate arrays standard cells full-custom description




bull The test patterns derived for single stuck-at faults are still valid for most defects even not accurately model some other physical defects

bull Single stuck-at tests cover a large percentage of multiple stuck-at faults



Bridging Faults (12)

bull Two or more normally distinct points(lines) are shorted togetherndash Logic effect depends on technology

bull Wired-AND for TTLbull Wired-OR for ECL

TTL Transistor-Transistor Logic

ECL Emitter-Coupled Logic



Bridging Faults (22)bull Wired-AND for TTL bull Wired-OR for ECL

A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

bull Stuck-at faults on inputs and outputsbull Crosspoint faults

ndash MissingExtrabull Bridging faults



Missing Crosspoint Faults in PLAbull Missing crosspoint in the AND plane

ndash Growth faultbull Missing crosspoint in the OR plane

ndash Disapperance fault



Extra Crosspoint Faults in PLAbull Extra crosspoint in the AND plane

ndash Shrinkage faultbull Extra crosspoint in the OR plane

ndash Appearance fault



Transistor Stuck-On Faults (12)

bull Also referred as stuck-short faults

stuck-on

0




bull May cause ambiguous logic levelsndash Depend on the relative impedances of the pull-

up and pull-down networksbull Quiescent current may be increased called

IDDQ fault



Transistor Stuck-Open Faults (12)

bull May cause output floating(high impedance)

stuck-open

0 Z




bull Turn the circuit into a sequential circuitndash Stuck-open faults require two-vector test

patterns

stuck-open

10 0100

two-vector test pattern

fault-free response

fault response



Gate Delay Faults (12)bull Slow to rise or fall

X X

R

X is slow to rise when channel resistance R is abnormally high



Gate Delay Faults (22)bull Detectability of gate delay faults

ndash May not be detected

slow

critical path



Path Delay Faultsbull Propagation delay of a path exceeds the

clock intervalbull The number of paths grows exponentially

with the number of gates

XY

XY

the clock interval

propagation delay



Functional Faultsbull Behavioral faults

ndash Fault effects are modeled at a higher level for modules such as

bull Decodersbull Multiplexersbull Addersbull Countersbull RAMsbull ROMs



An Example of Functional Faultsbull Decoder

ndash f(LiLj) instead of line Li line Lj is selectedndash f(LiLi+Lj) in addition to Li Lj is selectedndash f(Li0) none of the lines are selected

DecoderLi

Lj



State Transition Graph(STG)bull Each state transition is associated with a 4-

tuple (source input output destination state)

S1

S3S2

I1O1 I2O2



Single State Transition Faults

bull A fault causes a single state transition to a wrong destination state

S1

S3S2

IO IO



Memory Faults (12)

bull Parametric faultsndash Change the values of electrical parameters of

active or passive devices from their normal or expected values

bull Output levelsbull Power Consumptionbull Noise marginbull Data retention time



Memory Faults (22)

bull Functional faultsndash Stuck faults in address register data register

and address decoderndash Cell stuck faultsndash Cell coupling faultsndash Pattern sensitive faults



Coupling Faults

bull A transition in memory bit i causes an unwanted change in memory bit j



Pattern Sensitive Faultsbull The presence of a faulty signal depends on

the signal values of the nearby pointsndash Most common in DRAM

0 0 00 d b0 a 0

a = b = 0 rArr d = 0 prevent writing a 1 into da = b = 1 rArr d = 1 prevent writing a 0 into d



Fault Detectionbull Let z BnrarrB A test pattern t detects a fault f

iff z(t)opluszf(t) = 1x1

x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3

The test pattern 100 detects f because z1(100) = 0while z1f(100) = 1



Sensitization

bull Given a test pattern t a line is said to ldquobe sensitized to a fault f by trdquo if its normal value is changed in the presence of f

bull A path composed of sensitized lines is called ldquoa sensitized pathrdquo



Detectability

bull A fault f is said to be detectable if there exists a test pattern t that detects f otherwise f is a redundant fault

bull For a redundant fault f z(t) = zf(t)ndash No test pattern can simultaneously

sensitize(activate) f and create a sensitized path to a primary output(PO)



Redundant Faultsbull G1 stuck-at-0 fault is redundant

ndash Redundant faults do not change the function of the circuit

ndash The related circuit can be removed to simplify the circuit

1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing

bull The process to reduce the number of the faults under consideration is known as fault collapsing

bull Why fault collapsingndash Save memory space and CPU time for fault

simulation and test generation



Fault Equivalencebull A test pattern t distinguishes between faults α and β iff zα(t) ne zβ(t)

bull Two faults α and β are said to be equivalent in a circuit iff zα(t) = zβ(t) for all tndash Denoted by αharr βndash No test patterns can distinguish between α and β

ndash Any test pattern which detects one of them detects all of them



Fault Equivalence of Primitive Gates (12)

bull NOTndash Input s-a-1 and output s-a-0 are equivalentndash Input s-a-0 and output s-a-1 are equivalent

bull ANDndash All s-a-0 are equivalent

bull ORndash All s-a-1 are equivalent



bull NANDndash All input s-a-0 and output s-a-1 are equivalent

bull NORndash All input s-a-1 and output s-a-0 are equivalent




Equivalent Fault Collapsing (12)[Theorem 2-1] Under the single stuck-at faultmodel for an n-input primitive gate n+2instead of 2n+2 faults need to be considered

2n+2

n+1 n+1

equivalence

n+2cup

[Proof]



Equivalent Fault Collapsing (22)

s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0



Fault Dominancebull Let Tα be the set of all test patterns that

detect fault α We say that a fault βdominates fault α iff zα(t) = zβ(t) for all tisinTα

ndash Denoted by β rarr αndash No need to consider fault β for fault detection

Tα

Tβ

Tβ supeTα



Fault Dominance of Primitive Gatesbull AND

ndash Output s-a-1 dominates any input s-a-1bull OR

ndash Output s-a-0 dominates any input s-a-0bull NAND

ndash Output s-a-0 dominates any input s-a-1bull NOR

ndash Output s-a-1 dominates any input s-a-0



Dominated Fault Collapsing (12)[Theorem 2-2] Under the single stuck-at fault model for an n-input primitive gate only n+1faults need to be considered

2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance



Dominated Fault Collapsing (22)

s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0



Prime Faultsbull α is a prime fault if every fault dominated

by α is also equivalent to αbull Representative set of prime faults(RSPF)

ndash A set consisting of exactly one prime fault from each equivalence class of prime faults

bull Achieve 100 fault coverage ndash Only generate the test set for RSPF



Checkpoints (13)

bull Primary inputs and fanout branches

[Theorem 2-3] Any test set which detects all single stuck-at faults on every check point will detect all single stuck-at faults



Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0



Checkpoints (33)bull The set of checkpoint faults can be further

collapsed by using equivalence and dominance relations

a

b

c

d

e

10 checkpoint faultsa s-a-0 harr d s-a-0c s-a-0 harr e s-a-0b s-a-0 rarr d s-a-0b s-a-1 rarr d s-a-16 test patterns are enough

Chapter 3

Fault Simulation



Simulationbull True-value simulation

ndash Compute the responses for given inputtest patterns without injecting any faults in the circuit

bull For verifying the correctness of the design

bull Fault simulationndash Compute the responses for given inputtest

patterns with injecting considered faults in the circuit



Why Fault Simulation

bull To evaluate the quality of a test setndash In terms of fault coverage(FC)

bull To incorporate into ATPGndash Decrease the time for test pattern generation

bull To construct fault dictionary ndash For post-test diagnosis



Simulation Mechanisms

bull Compiled-code simulationndash Circuit is translated into the program where

each gate is executed for each patternbull Event-driven simulation

ndash Circuit structure and gate status are stored in a table and only those gates which are needed to be updated with a new pattern are processed



Compiled-Code Simulation (13)levelize circuit and produce compiled-codeinitialize data variables(flip-flops and memory)for every input pattern begin

set the primary inputs to the input pattern repeat until (steady-state or maximum iteration-count are reached)begin

execute compiled-codeupdate the associated data variables(flip-flop or memory)

endend



Compiled-Code Simulation (23)

bull The use of compiled-code simulation is usually limited into high-level designndash Since detailed timing or delay is almost

impossible to be simulated in the translated compiled-code




D-FF

abc

d

e

f

Compiled-Code

d = a amp b amp cf = d | ee = f

Q D



Event-Driven Simulation (12)initialize simulation time t to 0while (event list is not empty) begin

for every event (i t) begin gate i changes at time tupdate the value of gate i schedule fanout gates of i in the event list if the associated value changes are expected

endadvance simulation time t

end



Event-Driven Simulation (22)1a

c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1

simulation time t event fanout

0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1



Logic Value Based Fault Simulationbull For functional faults such as single stuck-at

faults helliphellipndash Logic simulation on both fault-free and faulty

circuitsTest Patterns



Complexity of Fault Simulation

bull Suitable for single stuck-at fault modelbull Higher than logic simulation but much

lower than test pattern generationbull In reality the complexity can be reduced by

fault collapsing and advanced techniques

patterns faults gates



Characteristics of Fault Simulationbull Fault activities with respect to fault-free

circuit are often sparse both in time and in spacendash For example f1 is not activated by the given

pattern(time) while f2 affects only the lower part of the circuit(space)

f1 s-a-0

f2 s-a-0

0

1

1



Efficiency of a Fault Simulator

bull Depend on its ability to exploit the sparse characteristics both in time and in space

人生最大的成就是從失敗中站起來證嚴法師靜思語



Classical Fault Simulation Techniques

bull Serial fault simulationbull Parallel fault simulationbull Deductive fault simulationbull Concurrent fault simulation



Serial Fault Simulation

bull The simplest algorithm for fault simulationndash Simulate the fault-free circuit for all input

patterns and save the outputs in a file(table)ndash Simulate one faulty circuit at a time until the

target fault is detected by some one test pattern or proven to be undetectable



Parallel Fault Simulation

bull Simulate faulty circuits in parallel with fault-free circuit by taking advantage of inherent parallel operation of computer wordsndash The number of circuits being processed

concurrently is limited by the word length wbull Each pass at most w-1 faulty circuit are processed



Example of Parallel Fault Simulation

0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0

for fault-free circuitfor circuit with fault b s-a-1for circuit with fault f s-a-0for circuit with fault i s-a-0

rArr Faults f s-a-0 and i s-a-0 are detected by test pattern (a b f) = (1 0 1)



Deductive Fault Simulation

bull Only the fault-free circuit is simulated (true-value simulation) ndash All signal values in each faulty circuit are

deduced from the fault-free circuit values and the circuit structure

bull Each signal is associated a list of faults in the circuit which can change the state of that line



Basic Fault List Propagation RulesInputs Output

a b cOutput Fault list

Lc

0 0 0 [La cap Lb] cup c1

[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type



Example of Deductive Fault Simulation (12)ab

c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

Initially La = a0 and Lb = b0For the fanouts of b c and d Lc = b0 c0 and Ld = b0 d0

Le = [La cup Lc] cup e0 = a0 b0 c0 e0 by Rule (4)Lf = Ld cup f1 = b0 d0 f1 by Rule (10)

g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0

Lg = [Le cap Lf] cup g0 = a0 c0 e0 g0 by Rule (7)

c 1 b0 c0

d 1 b0 d0

Example of Deductive Fault Simulation (22)

rArr Faults a0 c0 e0 and g0 are detected by test pattern (a b) = (1 1)



Concurrent Fault Simulation

bull Each gate retains a list of fault copies each of which stores the status of a fault to exhibit difference form the fault-free values



Example of Concurrent Fault Simulation

ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0



Modern Fault Simulation Techniques

bull Parallel-Pattern Single-Fault Propagation (PPSFP)

bull Critical Path Tracing



PPSFP

bull Based on the serial fault simulation many patterns are simulated in parallel for fault-free and faulty circuits respectivelyndash The number of patterns is limited by the word

length wbull Each pass at most w patterns are processed

ndash The basis of all modern fault simulators



Example of PPSFPbull Consider fault f s-a-0 and four pattern p3 p2

p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1

rArr Fault f s-a-0 are detected by test pattern p3 (a b f) = (1 0 1)

(faulty values)1 0 0 1



Sensitive Inputs

bull A gate input a is sensitive if complementing the value of a changes the value of the gate output

ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1



Critical Pathsbull Let l(v) be the fault-free value of line l

under input pattern t We say that line l is critical with respect to t iff t detects the fault l s-a-l(v)

bull A gate input i is critical with respect to t if the gate output is critical and i is sensitive

bull A path consisting of only critical lines is said to be a critical path



Critical Path Tracing

bull Two-step procedurendash Perform true-value simulation and identify

sensitive gate inputsndash Backtrace from POs to identify the critical lines

bull O(|G|) for fanout-free circuitsndash The fanout-free situation is very rare

bull Perform in fanout-free region and the stem faults are simulated by other methods mentioned earlier



Example of Critical Path Tracing (12)

a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive inputcritical line

rArrFaults i0 h0 f0 e0 and d1 are detected by test pattern (a b f) = (1 0 1)



Anomaly of Critical Path Tracinga

b

f

c

d e

g

h

i

1

0

11

1

0

1critical line

bull Stem criticality is hard to infer from branchesndash Eg Fault b s-a-1 is not detected by (a b f) = (1 0 1)

even though branches c and d are critical

stem

branch

branch



Multiple Path Sensitizationa

b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region


bull Both c and d are not critical but b is critical and bs-a-0 can be detected by (a b f) = (1 1 1)



Summariesbull Does specific test patterns detect specific

faultsndash Serial fault simulationndash Parallel fault simulationndash PPSFP

bull Which faults does a specific test pattern detect (suitable for ATPG)ndash Deductive fault simulationndash Concurrent fault simulationndash Critical Path Tracing

Chapter 4

Test Generation (TG)



Test Generation (TG) Methods

bull From truth tablebull Using Boolean equationbull Using Boolean differencebull From circuit structure

Impractical



TG from Truth Table

bull Based on the serial fault simulationndash Impractical

ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1



TG Using Boolean Equation

bull Based on the definition of detectability we have

Tα = (a b c) | f(a b c) oplus fα(a b c) = 1= (1 1 0)

bull High complexity

ab

c

f

α s-a-0



Boolean DifferenceThe Boolean difference of f(x) with respect to xi is

)()()( 1f0fdx

xdfii

i

oplus=

where fi(0) = (x1 hellip 0 hellip xn) and fi(1) = (x1 hellip 1 hellip xn)



Physical Meaning of Boolean Difference

bull Find all the input combinations such that the change of xi will cause the change of f(x)

bull Relationship between TG and Boolean difference

x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or



Case 1 Faults are present at PIsab

c

f

cb0cb1f0fda

xdfaa +=++bull=oplus= )(1)()()(

The set of all tests for a s-a-1 is (a b c) | a(b + c) = (0 1 x) (0 x 1)The set of all tests for a s-a-0 is (a b c) | a(b + c) = (1 1 x) (1 x 1)

TG Using Boolean Difference (12)



TG Using Boolean Difference (22)Case 2 Faults are present at internal lines

ab

c

f

h = ab

caacac1f0fdh

xdfachf hh +=bull+bull=oplus=+= 11)()()(

The set of all tests for h s-a-1 is (a b c) | h(a + c) = (0 x x) (x 0 0)The set of all tests for h s-a-0 is (a b c) | h(a + c) = (1 1 0)



Controlling and Inversion Valuesbull The value c of an input is said to be controlling

if it determines the value of the gate output regardless of the values of the other inputs then the output value is c oplus i where i for the inversion

bull The basic gates can be characterized by the two parametersndash The controlling value cndash The inversion value i

c iAND 0 0OR 1 0NAND 0 1NOR 1 1



Composite Logic Values and Operations

vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations



Line Justification (LJ)bull Set PIs to some values such that the specific

line has the predetermined value ab

c

f

10 = D

0

1

1

0

s-a-0D

h

ndash Eg Set both a and b to 1 h has the desired value 1 to activate the fault s-a-0 additionally set c to 0 the fault effect will be propagated to f



Justify(l val)Justify(l val)beginset l to valif l is a PI then returnc = controlling value of li = inversion of linval = val oplus i

if(inval = c)then for every input j of l

Justify(j inval)else

beginselect one input j of lJustify(j inval)

endend

Line justification for a fanout-free circuit



TG from Circuit Structure

bull Two basic goalsndash Fault activation (FA)ndash Fault propagation (FP)

rArrLine justification (LJ)

ab

c

f

10 = D larr fault activation (FA)

0 larr fault propagation (FP)

1

1

0

s-a-0D



TG for l s-a-vTG(l v)begin

set all values to xJustify(l v) FA if v = 0 then Propagate(l D) FP else Propagate(l D)

end



Propagate(l err)Propagate(l err) err is D or D beginset l to errif l is PO then returnk = the fanout of l c = controlling value of ki = inversion of kfor every input j of k other than lJustify(j c)

Propagate(k err oplus i)end

Error propagation for a fanout-free circuit



Implication

bull Compute the values that can be uniquelydetermined and check for their consistency with the previously determined ones



Decision Trees

bull Decision Treesndash Consist of decision nodes for problems that the

algorithm is attempting to solvendash A branch leaving a decision node corresponds

to a decisionndash A SUCCESS terminal node labeled S

represents finding a test ndash A FAILURE terminal node labeled F

indicates the detection of an inconsistency



Backtracking

bull A systematic exploration of the complete space of possible solutions and recovery from incorrect decisions recovery involves restoring the state of the computation to the state existing before the incorrect decision



Backtracking of Incorrect Decisions

0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc



bull A FA problem is a LJ problembull A FP problem

ndash Select a FP path to a PO rArr decisionsndash Once the FP path is selected rArr a set of LJ

problemsbull A LJ problem is an either implication or

decision problem

Common Concepts of Structural TG (12)




bull Incorrect decision(inconsistency) rArr Backtrack and make another decisions

bull Once the fault effect is propagated to a PO and all lines to be justified are justified the test pattern is generated otherwise the decision process is repeatedly until all possible decisions have been tried



A Simple Example of TG (12)

s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

bull FA rArr G1 = D rArr a = 1 b = 1 c = 1 rArr G2 = 0 (rArr G5 = 0) G3 = 0



A Simple Example of TG (22)bull FP through G5 or G6 (the last page)

ndash Decision through G5rArr G2 = 1 inconsistency rArr backtracking

ndash Decision through G6rArr G4 = 1 rArr e = 0 rArr SUCCESS

rArrThe resulted test pattern is 111x0 G5 G6

F S

G5 G6



Advanced Example (14)

s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D

bull FPrArr e = 1(rArr o = 0) f = 1 rArr q = 1 r = 1



Advanced Example (34)rArr Justify q = 1 rArr l = 1 or k = 1

ndash Decision l = 1rArr c = 1 d = 1 rArr m = 0 n = 0 rArr r = 0rArr inconsistency rArr backtracking

ndash Decision k = 1rArr a = 1 b = 1

rArr Justify r = 1 rArr m = 1 or n = 1rarr Decision m = 1

rArr c = 0 rArr SUCCESSrarr Decision n = 1

rArr d = 0 rArr SUCCESS

rArrThe resulted test is pattern 110x110 or 11x0110




q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1



A Generic TG AlgorithmSolve( )beginif Imply_and_check( ) = FAILUREthen return FAILURE

if(error at PO and all lines are justified)then return SUCCESS

if(no error can be propagated to a PO)then return FAILURE

select an unsolved problemrepeat

begin backtracking select one untried way to solve itif solve( ) = SUCCESS then

return SUCCESSend

until all ways to solve it have been triedreturn FAILURE

end



D-frontier And J-frontier

bull D-frontierndash The set of all gates whose output value is

currently x but have one or more fault signals on their inputs

bull J-frontierndash The set of all gates whose output value is

known but is not implied by their input values



Example of D-frontier

bull Initially the D-frontier is G6

s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D



Example of J-frontierbull Initially the J-frontier is q = 1 r = 1

s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1



LocalGlobal Implication

bull Local implicationndash Propagate values from one line to its immediate

inputs or outputsbull Global implication

ndash Propagation of values involves a larger area of the circuit and reconvergent fanout

bull Case analysis the SOCRATES system



Local Implication (Backward)

larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x

xJ-frontier = hellip a

11

1 rarr

a



Local Implication (Forward) (12)bull Binary values

x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa

J-frontier = hellip a


D-frontier = hellip a


x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr



Local Implication (Forward) (22)bull Error values

Before After

x

x1D


x

1

D-frontier = hellipa a

D rarr x

Dx a D-frontier = hellip a

D rarr D rarr

D rarrx D

DD rarr

D

DD-frontier = hellip a D-frontier = hellip

aD rarrx D

D0 rarr



Unique D-drive

Before

xx a D-frontier = hellip aD

After

D rarr

larr 1D-frontier = hellip

D



x-path

bull A path is said to be a x-path if all its lines have value x

[Theorem 4-1] Let G be a gate on D-frontier The error(s) on the input(s) of G can be propagated to a PO Z if there exists at least one x-path between G and Z



Error-Propagation Look-Ahead (12)

DD

x

x x

x

x

00

11

bull By Theorem 4-1 none of the fault effects can be observed on any POs




bull Using the error-propagation look-ahead technique we may prune the decision tree by recognizing states from which any further decisions will lead to a failure



D-Algorithm

bull FP is always given priority over LJbull Propagate fault effects on several

reconvergent paths referred to as ldquomultiple-path sensitizationrdquondash Some faults cannot be detected by sensitizing

only a single path



The D-algorithm Implementation (12)D-alg( )begin Implicationsif Imply_and_check( ) = FAILURE

then return FAILURE

if(error not at PO) thenbeginif D-frontier = empty

then return FAILURE

repeat beginselect an untried gate G from

D-frontier Decisionsc = controlling value of Gassign c to every input of G with

value xif D-alg( ) = SUCCESS

then return SUCCESSend

until all gates from D-frontier have been tried

return FAILUREend if (error not at PO)



if J-frontier = emptythen return SUCCESS

select a gate G from the J-frontierc = controlling value of G

repeat begin Decisionsselect an input j of G with value xassign c to jif D-alg( ) = SUCCESS

then return SUCCESSassign c to j

end

until all inputs of G are specifiedreturn FAILURE

end D-alg

The D-algorithm Implementation (22)



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

Example of D-Algorithm (0113)



Example of D-Algorithm (0213)bull Value computation (16)

Decisions Implications Commentsa = 0 Fault activationh = 1b = 1 Unique D-driven through gc = 1g = D D-frontier = i k m




Decisions Implications Commentsd = 1 Fault propagation through i

Propagate fault effects on i = Dd = 0

a single path D-frontier = k m n



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01




bull Value computation (36)Decisions Implications Comments

j = 1 Fault propagation through nk = 1 Propagate fault effects onl = 1 a single path m = 1

n = De = 0e = 1k = D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1




e = 1 Fault propagation through kk = D Propagate fault effects on e = 0 two paths j = 1 D-frontier = m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1





l = 1 Fault propagation through nm = 1 Propagate fault effects on

n= D two reconvergent paths f = 0

f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1




f = 1 Fault propagation through mm = D Propagate fault effects onf = 0 three paths l = 1n= D Fault effects on POrsquos




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D




bull Decision treendash Nodes the associated D-frontierndash Branches the taken decision ie the gate selected from the

D-frontieri k m

k m n

m nF

F S

i

n k

n m

Two times of backtracking




Partial Specification of The x Valuebull For a ldquototally unspecifiedrdquo composite value x

both v and vf are unknownndash x for 0 1 D D

bull For a ldquopartially specifiedrdquo composite value x v is binary and vf is unknown(u) vice versandash 0u for 0 D ndash 1u for D 1ndash u0 for 0 Dndash u1 for D 1



9-V Algorithmbull Similar to D-algorithm except that the

considered logic values are 0 1 D D 0u 1u u0 u1 uu (9-value)

bull Drive a D(D) through a gate G with controlling value c the values it assigns to the unspecified inputs of G correspond to the set c D(c D)

bull ub or bu (b is binary) at a PI is immediately transformed to bb



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

Example of 9-V Algorithm (17)

u1

u1

u1




Decisions Implications Commentsa = 0 Fault activationh = 1b = 1 Unique D-driven through gc = 1g = Di = u1k = u1m = u1 D-frontier = i k m

bullV

alue computation (13)





i = Dd = 0

n = 1u D-frontier = k m n

bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV


Decisions Implications Commentsl = u1 Fault propagation through nj = u1

n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D



Example of 9-V Algorithm (77)bull Decision tree

ndash Nodes the associated D-frontierndash Branches the taken decision ie the gate selected from the

D-frontier

i k m

k m n

S

i

n

No backtracking



D-Algorithm vs 9-V Algorithm

bull Whenever there are k possible paths for FPndash D-algorithm may eventually try all the 2k-1

combinations of pathsndash 9-V algorithm tries only one path at a time but

without precluding simultaneous FP on the other k-1 paths

bull Enumerate at most k ways of FP



Inversion Parity

bull In circuits composed only of AND OR NAND NOR and NOT gates we can define the ldquoinversion parityrdquo of a path as the number taken modulo 2 of the inverting gates (NAND NOR and NOT) along that path



Path-Oriented DEcision Making (PODEM)bull PODEM allows the value assignments for LJ

problems only on PIs ie backtracking can occur only on PIs ndash Treat a value vk to be justified for line k as an

objective (k vk)ndash Use the backtracing procedure to map the object

into a PI assignment that ldquois likely to contributerdquo to achieve the objective



BacktracingObjective (k vk)Step 1 Find a x-path from line k to a PI say aStep 2 Count the inversion parity of the pathStep 3 If the inversion parity is even then

return (a vk) otherwise (a vk)

Note No non-PI values are assigned during backtracing ie these values are assigned only by simulating PI assignments (implications)



The Backtracing ImplementationBacktrace(k vk) map objective into PI assignment beginv = vk

while k is a gate output begin

i = inversion of kselect an input j of k with value xv = v oplus ik = j

endreturn (k v) k is a PI

end



Example of Backtracing ProcedureObjective (f 1)

fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x

The first time of backtracing

fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101

The second time of backtracing



Choosing of Objectives (12)

bull In PODEM the order of the objectives being considered is as follows1 The objectives for FA2 Repeatedly select a gate G from the D-frontier

(until some fault effect is at a PO or the D-frontier is empty) and consider the input with x value as an objective




Objective( )being

the target fault is l s-a-v if (the value of l is x) then return (l v)select a gate G from the D-frontierselect an input j of G with value xc = controlling value of G return (j c)

end



The PODEM ImplementationPODEM( ) beginif (error at PO) then return SUCCESSif (test not possible) then return FAILURE(k vk) = Objective( )(j vj) = Backtrace(k vk) j is a PI Imply(j vj)if PODEM( ) = SUCCESS then return SUCCESSImply(j vj) reverse decision if PODEM( ) = SUCCESS then return SUCCESSImply(j x)return FAILURE

end



Example 1 of PODEM (18)

abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D



Example 1 of PODEM (28)bull Value computation (13)

Objective PI Assignment Implications D-frontier Comments

(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n



Example 1 of PODEM (38)bull Value computation (23)Objective PI Assignment Implications D-frontier Comments

(k 1) e = 0 e = 1j =0

k =1n = 1 m x-path check fails

e = 1 e = 0 reversal

j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11

x-path(to PO)check failsrArr Backtracking




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D



Example 1 of PODEM (88)bull Decision tree

ndash Nodes the PIs selected to be assigned valuesndash Branches the value assigned to the PI

a0b1

c1d1

e0F f1

S

1



Features of PODEMbull PODEM examines all possible input

patterns implicitly but exhaustively as tests for a given fault ie a complete TG

bull PODEM does not needndash Consistency checkndash The J-frontierndash Backward implications

bull Generally faster than D-algorithm



A More Intelligent Backtracing (12)bull To guide the backtracing process of PODEM

controllability for each line is measuredndash CY1(a) the probability that line a has a value 1ndash CY0(a) the probability that line a has a value 0

bull Eg f = ab assume CY1(a) = CY0(a) = CY1(b) = CY0(b) = 05ndash CY1(f) = CY1(a) CY1(b) = 025ndash CY0(f) = 1 - CY1(f) = 075

ab f



bull How to guide the backtracing process using controllabilityndash Principle 1 Among several unsolved problems first

attack the hardest onendash Principle 2 Among several solutions of a problem

first try to the easiest onebull Eg

ndash Objective (c 1) rArr Choose path c-a to backtracendash Objective (c 0) rArr Choose path c-a to backtrace

A More Intelligent Backtracing (22)

ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05



Example 2 of PODEM (14)Initial objective(G5 1)G5 is an AND gate Choose the hardest-1rArr Current objective is (G1 1)G1 is an AND gate Choose the hardest-1 rArr Arbitrarily current objective is (A 1)A is a PI Implication rArr G3 = 0

Ps Initially CY1 and CY0 for all PIs are set to 05

C1(G1) = 025

C1(G1) = 0656



Example 2 of PODEM (24)Is the initial objective justified No rArr Current objective (G5 1)G5 is an AND gate Choose the hardest-1rArr Current objective is (G1 1)G1 is an AND gate rArr Choose the hardest-1 rArr Arbitrarily current objective is (B 1)B is a PI rArr Implication rArr G1 = 1 G6 = 0

C1(G1) = 025

C1(G1) = 0656



Example 2 of PODEM (34)Is the initial objective justified No rArr Current objective (G5 1)The value of G1 is known rArr Current objective (G4 0)The value of G3 is known rArr Current objective(G2 0)A B are known rArr Current objective (C 0)C is a PI rArr Implication rArr G2 = 0 G4 = 0 G5 = D G7 = D

C1(G1) = 025

C1(G1) = 0656

No backtracking




bull If the backtracing process is not guided ndash Two times of backtracking may occur

G5rarr G4rarr G2rarr A

G5rarr G4rarr G2rarr B

G5rarr G4rarr G2rarr C



Head Lines

bull A line that is reachable from at least one stem is said to be bound otherwise free

bull A head line is a free line that directly feeds a bound line

head linesbound

DE

ABC

F

G



The Property of Head Lines[Theorem 4-2] If l is a head line the value of l can be justified without contradicting any other values previously assignedHintThe subcircuit feeding l is fanout-free

head linesbound

DE

ABC

F

G



Fanout-Oriented (FAN) Algorithmbull The FAN algorithm introduces two major

extensions to the backtracing concept of PODEMndash Rather than stopping at PIs backtracing in

FAN may stop at internal lines ie head lines ndash Rather than trying to satisfy one objective

FAN use a multiple-backtrace procedure that attempts to simultaneously satisfy a set of objectives



FAN vs PODEM

head linesbound

DE

ABC

F

G

Assume that setting G = 0 causes the D-frontier to become empty

A1B0

F C0F

1

1

G0F

1

PODEM FAN



Multiple Backtracing (13)Mbacktrace(Current_objectives)beginrepeat

beginremove one entry (k vk) from

Current_objectivesif k is a head line

then add (k vk) to Head_objectiveselse if k is a fanout branch

thenbegin

j = stem(k)increment number of requests at

j for vk

add j to Stem_objectivesend else if k is a fanout branch

else continue tracingbegin

i = inversion of kc = controlling value of k



Multiple Backtracing (23)

if(vkoplus i = c) then

beginselect an input j of k with

value xadd (j c) to

Current_objectivesend if(vkoplus i = c)

elsefor every input j of k with

value x

add (j c) to Current_objectives

end continue tracingend

until Current_objectives = empty




if Stem_objectives ne emptybeginremove the highest-level stem k from

Stem_objectives

vk = most requested value of k

if(k has contradictory requirements and k is not reachable from target fault)

then return (k vk)add (k vk) to Current_objectivesreturn

Mbacktrace(Current_objectives)end if Stem_objectives ne empty

remove one objective (k vk) from Head_objectivesreturn (k vk)

end Mbacktrace



Generation of Conflicting Values on A Stem

0

1

0

1



Example of Multiple Backtracing (12)

AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )

(A1 1 ) (E1 1 ) (E2 1) (C 1) (A1 1 ) A(E1 1 ) (E2 1 ) (C 1 ) (E1 1 ) A E(E2 1 ) (C 1 ) (E2 1 ) A E(C 1) (C 1 ) A E C

A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C

Current_objectivesProcessed

entry Stem_objectives Head_objectives

empty

empty



The FAN Implementation (12)FAN( ) beginif Imply_and_check( ) =

FAILUREthen return FAILURE

if (error at PO and all bound lines are justified) then

beginjustify all unjustified head lines return SUCCESS

end

if(error not at PO and D-frontier = empty)then return FAILURE

add every unjustified bound lines to Current_objectivesselect one gate G from the D-frontier c = controlling value of Gfor every input j of G with value xadd (j c) to Current_objectives



The FAN Implementation (22)(i vi) = Mbackrace(Current_objectives)Assign(i vi)if FAN( ) = SUCCESSthen return SUCCESS

Assign(i vi) reverse decisionif FAN( ) = SUCCESSthen return SUCCESS

Assign(i x)return FAILURE

End FAN( )



ATPG (12)

bull Basic schemeinitialize the test set to NULLrepeat

generate a new test vectorevaluate fault coverage for the test vectorif the test vector is acceptable then add it to the test set

until the required fault coverage is obtained



ATPG (22)

bull Accelerationndash Phase I Random test patterns are generated

first to detect easy-to-detect faultsndash Phase II A deterministic TG is then performed

to generate test patterns for the remaining faults



Sequential TG

bull For circuits with unknown initial statesndash Time-frame expansion based

bull Extended D-algorithmbull 9-V sequential TG

ndash Simulation basedbull CONTEST [Agrawal and Cheng IEEE TCAD Feb

1989]

bull For circuits with known initial statesndash STALLION [Ma et al IEEE TCAD Oct 1988]



Iterative Logic Array (ILA) Model

bull Here the model is restricted to synchronous sequential circuits

initial states



Extended D-algorithm1 Pick up a target fault f2 Create a copy of the combinational logic say Time-

frame 03 Generate a test pattern for f using D-algorithm for

time-frame 04 If all the fault effects are propagated into the FFrsquos

continue the fault propagation in the next time-frame5 If there are values required to be justified in the

FFrsquos continue the line justification (LJ) in the previous time-frame



I

OY1

Y2y1

y2 s-a-1

FF2

FF1

Example of Extended D-algorithm (12)




OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG

bull Extended D-algorithm is not completebull If 9-V instead of 5-V is used it will be a

complete algorithmndash Since it takes into account the possible repeated

effects of the fault in the ILA model



Example of 9-V Sequential TG (12)



Example of 9-V Sequential TG (22)bull If 5-V Sequential TG is usedhelliphellip

D D



Problems of Time-frame Approachesbull The requirements created during the

forward process (FP) have to be justified (LJ) by the backward processes laterndash Need going both forward and backward time

framesndash Need to maintain a large number of time-

framesbull How many Cyclesbull Implementation is complicated



Simulation-Based Approaches

bull Advantagesndash Timing is considered and asynchronous circuits

can be handledndash Can be easily implemented by modifying a

fault simulatorbull Disadvantages

ndash Can not identify undetectable faultsndash Hard-to-activate faults may not be detected



Difficulties of Sequential Test Generation

bull Initialization is difficultndash Justify invalid statesndash Long initialization sequences (simulator

limitations)bull Timing cannot be considered by time-frame

expansionsndash Races and hazardsndash Asynchronous circuits cannot be handled



Why FC of 100 Is Hard

bull If each undetected fault is redundant then FC will easily reach at 100ndash Proving that the undetected fault is a redundant

fault may be very and very hardbull How to increase FC

faultsredundant the-list fault of size thefaultsredundant the-fault undetected of size the-1

faultsredundant the-list fault of size thefaults detected the

=

=FC

Chapter 5




Motivation bull Test costs

ndash Test Generation (TG)ndash Fault Simulationndash Test Application Timendash Memory spacendash helliphellip

bull Test difficultiesndash Sequential gt Combinationalndash helliphellip



Testability Measures

bull Controllabilityndash The difficulty of setting a particular logic signal

to a 0 or 1bull Observability

ndash The difficulty of observing the state of a logic signal



SCOAPbull Sandia ControllabilityObservability

Analysis Program [Goldstein 1979]bull Use six cost functions of type integer to

reflect the relative difficulties of controlling and observing signals in digital circuitsndash Higher numbers indicate more difficult to

control or observe signals



Combinational SCOAP Measures

bull For signal lndash CC0(l)

bull The combinational ldquorelative difficultyrdquo of setting l to 0

ndash CC1(l)bull The combinational ldquorelative difficultyrdquo of setting l to 1

ndash CO(l)bull The combinational ldquorelative difficultyrdquo of propagating

a fault effect from l to a PO



bull For signal lndash SC0(l)

bull The sequential ldquorelative difficultyrdquo of setting l to 0

ndash SC1(l)bull The sequential ldquorelative difficultyrdquo of setting l to 1

ndash SO(l)bull The sequential ldquorelative difficultyrdquo of propagating a

fault effect from l to a PO

Sequential SCOAP Measures



Initialization

bull CC0(i) = CC1(i) = SC0(i) = SC1(i) = 1 for all PI ibull CO(o) = SO(o) = 0 for all PO obull Set others to infin

The controllabilities range between 1 and infin

The observabilities range between 0 and infin



Controllability of Combinational Components (12)

bull CC0(z) = CC0(a) + CC0(b) + 1bull CC1(z) = minCC1(a) CC1(b) + 1bull SC0(z) = SC0(a) + SC0(b)bull SC1(z) = minSC1(a) SC1(b)

ab z

CC0 or CC1 are related to the number of signals that may be manipulated to control SC0 or SC1 are related to the number of time-frames needed to control



Controllability of Combinational Components (22)ab

ab

abab

ab

ab

z

z

z

z

z

z

CC0(z) = minCC0(a) CC0(b) + 1CC1(z) = CC1(a) + CC1(b) + 1

CC0(z) = CC1(a) + CC1(b) + 1CC1(z) = minCC0(a) CC0(b) + 1CC0(z) = CC0(a) + CC0(b) + 1CC1(z) = minCC1(a) CC1(b) + 1CC0(z) = minCC1(a) CC1(b) + 1CC1(z) = CC0(a) + CC0(b) + 1

CC0(z) = minCC1(a) + CC1(b) CC0(a) + CC0(b) + 1CC1(z) = minCC0(a) + CC1(b) CC1(a) + CC0(b) + 1




Controllability of Sequential Components

bull CC0(Q) = minCC0(R) CC1(R) + CC0(D) + CC0(C) + CC1(C)bull CC1(Q) = CC1(R) + CC1(D) + CC0(C) + CC1(C)bull SC0(Q) = minSC0(R) SC1(R) + SC0(D) + SC0(C) + SC1(C) + 1bull SC1(Q) = SC1(R) + SC1(D) + SC0(C) + SC1(C) + 1

D

C

Q

R



Observability (12)

P

QR

N

bull CO(P) = CO(N) + CC1(Q) + CC1(R) + 1bull SO(P) = SO(N) + SC1(Q) + SC1(R)

D

C

Q

R bull CO(R) = CO(Q) + CC1(Q) + CC0(R)bull SO(R) = SO(Q) + SC1(Q) + SC0(R) + 1

CO are related to the number of signals that may be manipulated to observeSO are related to the number of time-frames needed to observe



Observability (22)ab

ab

abab

ab

ab

z

z

z

z

z

z

CO(a) = CO(z) + CC1(b) + 1CO(b) = CO(z) + CC1(a) + 1


CO(a) = CO(z) + CC0(b) + 1CO(b) = CO(z) + CC0(a) + 1CO(a) = CO(z) + CC0(b) + 1CO(b) = CO(z) + CC0(a) + 1

CO(a) = CO(z) + minCC0(b) CC1(b) + 1CO(b) = CO(z) + minCC0(a) CC1(a) + 1CO(a) = CO(z) + minCC0(b) CC1(b) + 1CO(b) = CO(z) + minCC0(a) CC1(a) + 1

zz1z2

zn

CO(z) = minCO(z1) CO(zz) helliphellip CO(zn)



Example of SCOAP (13)

1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

Computation of controllability (12)




Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0


Computation of observability (13)




Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0





Importance of Testability Measures

bull Speed up test generation (TG) algorithmsbull Improve the testability of the circuit under

design ndash Guide the design for testability (DFT) insertion




bull DFT techniquesndash Design efforts specifically employed to ensure

that a circuit is testablebull In general DFT is achieved by employing

extra hardware overheadndash Conflict between design and test engineersndash Balance between amount of DFT and gain

achieved



Benefits of DFTbull Fault coverage uarr (must guarantee) bull Test generation time darrbull Test lengthTest memoryTest application time darrbull Support a test hierarchy

ndash Chipsndash Boardsndash Systems

rArrPay less now and pay more latter without DFT

FC100

with DFT

of T

without DFT



Costs Associated with DFT

bull Pin overhead uarrbull Area uarrbull Yield darrbull Performance darrbull Design time uarr

rArrThere is no free lunch



DFT Techniques

bull Ad hoc DFT techniquesbull Scan-based designsbull Boundary scan



Ad Hoc DFT Techniquesbull Test pointsbull Initializationbull Monostable multivibrators (one-shots)bull Oscillators and clocksbull Partitioning counters and shift registersbull Partitioning of large combinational circuitsbull Logic redundancybull Break global feedback paths



Test Pointsbull Insert test points control points (CPs) and

observation points (OPs) to enhance controllability and observability

C1 C2 C1 C2

jumper

CPOP

original circuits testable circuits

Can be done only for boards



01-Injection

CP1

C1

CP0

C2

01-injection

C1C2

CP00-injection 1-injection

C1C2

CP1

OP OP

OP



01-Injection Using a MUX

NT

C1

CP C2

01-injection

MUX

0

1

OP



IO-Pin Cost Decrement (12)

01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n

Using a demultiplexer and a latchregister to implement CPs




01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs



Time-Sharing IO Pins (12)

PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT



Selection of CPs (12)

bull Control address and data bus lines on bus-structured designs

bull Enablehold inputs to microprocessorsbull Enable and readwrite inputs to memory

devicesbull Clock and presetclear inputs to memory

devices such as flip-flops counter and shift registers




bull Data select inputs to multiplexers and demultiplexers

bull Control lines on tri-state devices



Selection of OPs (12)

bull Stem lines associated with signals having high fanout

bull Global feedback pathsbull Redundant signal linesbull Outputs of logic devices having many

inputs such as multiplexers and parity generators




bull Outputs from state devices such as flip-flops counters and shift registers

bull Address control data buses



Initialization (12)bull Design circuits to be easily initializable

ndash Donrsquot disable preset (PR) and clear (CLR) lines

PR

CLR

Vcc

Vcc

Q

Q



Initialization (22)bull When the preset or clear line is driven by

logic a gate can be added to achieve initialization

PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1



Built-In Initialization Signal Generator

Vcc

t

VZ

Vcc

Z



Monostable Multivibrators (One-Shots) (12)

bull Disable internal one-shots during test

C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s



Oscillators And Clocksbull Disable internal oscillators and clocks

during test

OSCC

OP

AB

01-I



CountersShift Registers (12)bull Partition large counters and shift registers

into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2



CountersShift Registers (22)

CPdata inhibit

CPtest data

C

CPclock inhibitCPtest clock

DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2



Partitioning Large Circuits (12)bull Partition large circuits into smaller

subcircuits to reduce test generation cost

C1 C2

AB

C

D

E

F G

m ns

p

q



Partitioning Large Circuits (22)

If 2p+n + 2q+m lt 2n+m then test time can be reduced

m

s

n

q

p



Logic Redundancy

bull Avoid the use of redundant logicndash Remove (for eliminating hazardshelliphellip)

bull Add test points to remove the redundancy during testing

bull Bias fault coverage



Global Feedback Pathsbull Provide logic to break global feedback

paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO

Original design Modified design



Scan Storage Cell (SSC)

DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC

rArr A SSC can be used as control point (CP) andor observation point (OP)

SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK



Scan Register (SR) (12)

Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR




bull A scan register (SR) loads data in parallel when N T = 0 (normal mode) and shifts when N T = 1 (test mode)ndash Scan-in operation (test mode)

bull Load data into R from line Sin (control)

ndash Scan-out operation (test mode)bull Read data out of R from line Sout (observation)



Generic Scan-Based Design

bull Full serial integrated scanbull Full isolated scanbull Nonserial scan

ndash Random-access scan



Full Serial Integrated Scan (12)

bull All the original storage cells are replaced by the SSCrsquos and made part of the SR

bull Sequential ATPG rarr Combinational ATPG



C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout

Original design (Normal) Modified design (Scanned)




Full Isolated Scan (12)bull The SR is not in the the normal data path

C

Rrsquo

Rs

PI PO

Sin Sout

two data input ports

shadow register



Full Isolated Scan (22)bull Advantages

ndash Real-time testingbull A single test can be applied at the operational clock

rate of the system

ndash On-line testingbull The circuit can be tested while in normal operation

bull Disadvantagesndash Hardware overhead

bull Two data input portsbull Shadow register



Random-Access Scan (12)C

addressable storage elements

clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO



Random-Access Scan (22)bull Advantages

ndash Scan in a new vector only bits that need be changed must be addressed and modified also selected bits can be observed

bull Full controllability and observability


bull Considerable overhead associated with storing the addresses of the cells to be setread



IBM LSSD Scan Cellbull Level Sensitive Scan Design

D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B

Normal mode A = 0 C and B activeTest mode C = 0 A and B active



Clock Schemebull To obtain race-free condition clocks C and

B as well as A and B are nonoverlapping

C

B

A

B

Normal mode A = 0

Test mode C = 0



LSSD Double-Latch Design

Sout

Sin

CA

B

Shift Register Latch (SRL)



LSSD Single-Latch Design

Sout

SinC2




Scan Design Costsbull Hardware overheadbull Extra pinsbull High test timebull Extra slower clock controlsbull Possible performance degradationbull Some designs are not easily realizable as

scan designTest generation costs can be significantly reduced and lead to higher fault coverage



Notes

Chapter 6

Advanced Scan Concepts




bull Multiple test sessionsbull Multiple scan chainsbull Broadcast scan chainsbull Partial scan



Multiple Test Sessions (12)bull of test patterns

ndash C1 100 C2 200 C3 30020 bits 20 bits 20 bits

C1 C2 C3

Test time= 60 300= 18000 (cycles)

One session




ndash C1 100 C2 200 C3 300

20 bits 20 bits 20 bits

C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions



Multiple Scan Chainsbull Reduce test application timebull Large pin overhead

ndash Usually test IO will share the normal IO

A single chain (long test time) Multiple chains



Broadcast Scan Chainsbull Using a single data input to support multiple

scan chains

Source Lee et al ICCADrsquo98



Virtual Circuitsbull The inputs of circuits under test (CUTs) are

connected in a 1-to-1 manner

bull The whole virtual circuit is considered as one circuit during ATPG

bull The resulted test patterns can be shared by all CUTs Source Lee et al ICCADrsquo98



Partial Scanbull Only a subset of flip-flops are scannedbull Trade-offs

ndash Area overheadndash TG complexity

partial scan

full scan

sequential TG

combinational TG

1000 (scanned FFrsquos)



A Basic Method for Partial Scanbull Represent a sequential circuit with feedback

as a directed graph G = (V E)ndash Each flip-flop i is represented as vertex vi in V ndash Each combinational path from flip-flop i to j is

represented as a directed edge from vi to vj in E

Source Cheng and Agrawal IEEE TComputersrsquo90



Graph Representation (13)

3

1 2 4 5 6

A sequential circuit with 6 flip-flops

Graph representation



Graph Representation (23)bull Distance between two vertices on a path is

defined as the number of vertices on that path

distance = 4

distance = 3



Graph Representation (33)bull Sequential depth of a circuit is defined as

the distance of the longest pathbull Cycle length is defined as the maximum

number of vertices in a cycle

Sequential depth = 6

Cycle length = 3 Cycle length = 1 Cycle length = 2



Analysis of Sequential Circuits (13)

bull Any sequential circuit can be divided into 3 classes of subcircuits based on the directed graph representationndash Acyclic directed (testable)ndash Directed with only self-loops (testable)ndash Directed with cycles of two or more vertices

(not testable)




Directed with cycles of two or more vertices (not testable)

Acyclic directed (testable)

Directed with only self-loop (testable)




bull The number of gates or flip-flops is not the dominant factor for test generation complexity

bull Cycle length is the dominant factorndash To reduce test generation complexity cycles of

length ge 2 should be break or eliminatedbull Sequential depth is minor



Flip-Flop Selection Algorithm (12)

beginidentify all cyclesrepeat

for every vertex begincount the frequency of appearance in the cycle list

endselect the most frequently used vertexremove all cycles containing the selected vertex from the cycle listuntil cycle list is empty

end

bull Finding the vertex set that breaks all cycles called the feedback vertex set problem is NP-completendash Heuristics must be used to bound the computation time



= 695




The BALLAST Methodology (13)bull Scan storage elements are selected such that

the remainder of circuit has some testable structurendash A complete test set can be obtained by using

combinational ATPGsequential TG

combinational TG

1000Source Gupta et al IEEE TComputersrsquo90

BALLAST

(scanned FFrsquos)



The BALLAST Methodology (23)

Sout

Sin

HOLD(for test)



bull Test procedure for a test pattern ndash Scan in the pattern to R3 and R6

ndash Hold the test pattern in R3 and R6 for two clock cycles such that the test response appears in R4and R5

ndash Load data to R3 and R6 and scan out




Circuit Model (14)

bull Given a synchronous sequential circuit Sndash The combinational logic can be partitioned into

clouds where each cloud is a maximal region of connected combinational logic such that its inputs are either primary inputs or outputs of FFrsquos and its outputs are either primary outputs or inputs to FFrsquos



Circuit Model (24)bull A register

ndash Consists of one or more FFrsquos driven by the same clock signal

ndash Receives data from exactly one cloud and feeds exactly one cloud

bull Two typesndash Load set (L) always operates in LOAD modendash Hold set (H) two modes of operation ndash LOAD

and HOLD



Circuit Model (34)bull A directed graph G = (V A H W)

ndash V the set of cloudsndash A the set of connections between two clouds

through registersndash H sub A connections through HOLD registersndash W ArarrZ+ defines the number of FFrsquos in each

registersbull W(a) represent the cost of converting a register into

a scan register



Circuit Model (44)

R3



Balanced Sequential Structurebull A synchronous sequential circuit S with G is said

to be a balanced sequential structure (B-structure) ifndash G is acyclic ndash forallv1 v2 isin V all directed paths from v1 to v2 are of equal

lengthndash forallh isin H if h is removed from G the resulted graph is

disconnectedbull When examining whether a circuit with scan

registers is a B-structure the arcs corresponding to scan registers must be removed



Example of B-structure

Red arcs represent HOLD registersOthers represent LOAD registers

A B-structure



Kernel of a B-Structure (13)bull Given a B-structure SB

ndash Combinational equivalent CB is defined as the combinational circuit formed by replacing each FF in every register in SB by a wire or an inverter

bull Single-pattern testablebull A complete single-pattern test set can be derived

using combinational test generation techniques

bull The depth d of SB

ndash The number of registers on the longest path



Kernel of a B-Structure (23)B-structure SB (d = 2)

Combinational Equivalent CB



Kernel of a B-Structure (33)bull Given an input pattern I applied to SB define the

single-pattern output of SB for I as the steady-state output of SB when I is held constant at the inputs to SB and all its registers are operated in LOADmode for at least d clock cycles

bull Given some fault f in SB if the single-pattern outputs for I of the good and the faulty circuits are different then I is a single-pattern test for f



Outline of BALLAST1 Construct G = (V A H W)2 Remove a minimal cost set of arcs R to

construct SB

3 Determine CB of SB and a complete test set Tfor CB using a combinational ATPG

4 Construct a scan path composed of the registers in R so that they can ldquoshiftrdquo ldquoholdrdquo and ldquoloadrdquo



Selection of Scan Registers1 Transform G = (V A H W) into an acyclic

graph GA by removing a minimal cost set of ldquofeedbackrdquo arcs RA (NP-complete)

2 Transform GA into a balanced graph GB by removing a minimal cost set of arcs RB (NP-complete)R = RAcupRB is the desired set for scan registers



Test Procedurebull Operate all scan registers in the SHIFT mode for l

clock cycles (scam in the first test pattern)ndash l is the total number of FFrsquos in the scan path

bull Repeat N times N is the number of test patterns(a) Place all scan register in HOLD mode and all nonscan

registers in LOAD mode for d clock cycles(b) Operate all scan registers in LOAD Load for 1clock

cycle(c) Operate all scan register in SHIFT mode for l clock

cycles



Elimination of HOLD Modebull Eg By adding two dummy bits (d) between

the patterns to be scanned to R3 and R6 the HOLD mode can be eliminated

Sin

Sout1101hellip01dd10hellip101

R3 R6



ConclusionsMethods Partial Scan

Multiple TestSessions

Mutiple ScanChains

Broadcast ScanChains

Area Overhead

PerformanceDegradation

Extal Pins

Extral ClockControl

Test ApplicationTime

same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7

Compression Techniques



Challenges from ORA

bull A bit-by-bit comparison of observed output values with the correct values as previously computed and saved is quite inefficientndash Require a significant amount of memory

storage for saving the correct outputs associated with all test vectors



Response Compressionbull Compress or compact output responses into

ldquoa signaturerdquondash A circuit is tested by comparing the observed

signature with the correct computed signature



Error Maskingbull signature(faulty circuit)

= signature(fault-free circuit)ndash The erroneous output response is an alias of the

correct output responsebull Measurement of masking probability

ndash Compute the fraction of all possible erroneous response sequences that cause masking associated with specific compression techniques



Requirements of Compression Techniques

bull Easy to implement specially in the BIST environment

bull Small performance degradationbull High degree compactionbull No or small alias errors



Basic Compression Techniques

bull Ones-count compressionbull Transition-count compressionbull Parity-check compressionbull Syndrome Testingbull Signature Analysis



Ones-Count Compression (12)bull Given a single-output circuit C let the

output response of C be R = r1 r2 hellip rm

ndash In ones counting the signature 1C(R) is the number if 1s appearing in R ie

where 0 le 1C(R) le m

bull The degree of compression is ⎡log2(m+1)⎤

sum=i

irR1C )(



Ones-Count Compression (22)

counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0

Signature (ones count)1C(R0) = 11C(R1) = 21C(R2) = 0

x1x2x3

Input test patternsequence T

Output Reponses



Analysis of Ones-Countbull Consider a circuit tested with m random

input vectors and let 1C(R0) = r 0 le r le mndash The number of m-bit sequences having r 1s is

such sequences are aliases

bull The ratio of masking sequences to all possible erroneous sequence given 1C(R0) = r is

⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(



Transition-Count Compressionbull TC(R) = sum

minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0

Signature (transition count)TC(R0) = 1TC(R1) = 1(undetectable fault)TC(R2) = 0



bull If all faulty sequences are equally likely to occur as the response of a faulty circuit then the probability of masking is given by

Analysis of Transition-Count

122)|(

1

minusminus

=minus

m

mr

TC1CrmMP



Parity-Check Compression

NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

Signature (parity)p(R0) = 1p(R1) = 0p(R2) = 0



bull All errors consisting of odd number of bit errors are detectedndash Detect all single-bit errors

bull All errors consisting of even number of bit errors are maskedndash Assume all faulty bit streams are equally likely

the probability of masking approaches frac12 as m increases

Analysis of Parity-Check



Syndrome Testingbull Rely on exhaustive testing ie applying all

2n test vectors to an n-input combinational circuitndash Eg Consider a single-output circuit

implementing a function fbull The syndrome S (or signature) is the normalized

number of 1s in the resulting stream ie S = K2n where K is the number of minterms in the function f

ndash A special case of ones-count compression



Signature Analysis

bull Signature analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) and realized in hardware using linear-feedback shift registers (LFSRs)ndash The signature is the content of this register after

the last input bit has been sampled



LFSRs Used as Signature Analyzers

bull Single-input signature registers (SISRs)bull Multiple-input signature registers (MISRs)



SISRsbull Initial state I(x) = 0bull Final state R(x) the remainder or signature

)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2



Analysis of SISRs (12)

bull For a test bit stream of length mndash 2m possible responses of which only one is

correctndash The number of bit streams producing a specific

signature is 2m 2n = 2m-n where n is the length of the LFSR

ndash Among these streams only one is correct

( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984

of erroneous responses are detectedNote This is not of faults




MISRs



Implementation of MISRs

(a) Original (a) Modified



The Storage Cell for MISRs



Notes

Chapter 8

Built-In Self-Test (BIST)



Built-In Self-Test (BIST) (12)bull Capability of a circuit (chip board or

system) to test itself

Test Pattern Generator (TPG)

Circuit under Test (CUT)

Output Response Analyzer (ORA)



bull On-line not placed into the test modendash Concurrent simultaneous with normal

operationndash Nonconcurrent idle normal operation

bull Off-line placed into the test modendash Functional diagnosis SW or FWndash Structural

bull LFSR-based TPG and ORAbull FC is estimated

Built-In Self-Test (BIST) (22)



Glossary of BIST Test Structures (12)bull BILBO

ndash built-in logic block observation (register)bull LFSR

ndash linear feedback shift registerbull MISR

ndash multiple-input signature registerbull ORA

ndash output response analyzer



bull PRPG ndash pseudorandom pattern generator also referred

to as a pseudorandom number generatorbull SISR

ndash single-input signature registerbull SRSG

ndash shift-register sequence generator also a single-output PRPG

bull TPGndash test pattern generator

Glossary of BIST Test Structures (22)



bull Exhaustive testingndash Exhaustive test-pattern generator

bull Pseudorandom testingndash Weighted test generatorndash Adaptive test generator

Test Pattern Generation for BIST (12)




bull Pseudoexhaustive testingndash Syndrome driver counterndash Constant-weight counterndash Combined LFSR and shift registerndash Combined LFSR and XOR gatesndash Condensed LFSRndash Cyclic LFSR



Exhaustive Testing

bull Apply all 2n input vectors where n is the number of inputs to CUTndash Impractical for large n

bull Detect all detectable faults that do not cause sequential behaviorndash In general not applicable to sequential circuits

bull Can use a counter or LFSR for TPG



bull A shift register with a linear feedback network is called a linear feedback shift register (LFSR)

bull A n-stage shift register has at most 2n statesrArr A n-stage LFSR has at most 2nndash1 stages

the linear successor of the all-zero state is itself

there4

Linear Feedback Shift Register (LFSR) (12)




D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0

Z = 0101helliphellip2 states

Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1

Z = 11010011101001 helliphellip7 states

linear feedback network



Two Types of LFSRs (12)bull Type 1 External type

D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1



Two Types of LFSRs (22)bull Type 2 Internal type

D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1



Mathematical Operations over GF(2)

bull Multiplication(bull) bull Addition( )

bull 0 10 0 01 0 1

0 10 0 11 1 0

Eg Let C1 = 0 C2 = 1 C3 = 1 and a1 = 0 a2 = 1 a3 = 1If a0 = C1 bull a1 C2 bull a2 C3 bull a3 then a0 = 0 bull 0 1 bull 1 1 bull 1 = 0



Analysis of LFSRsbull A sequence of binary numbers can be

represented using a generation function (polynomial)

bull The behavior of an LFSR can be determined by its ldquoinitial seed (S0)rdquo and ldquofeedback coefficients (Ci)rdquo



Characteristic Polynomials (13)

bull Let a0 a1 hellip am hellipbe the sequence of binary numbers ndash Generation function

G(x) = a0 + a1x +hellip+ amxm + hellip=bull Let am = a0 a1 hellip am hellipbe the output

sequence of an LFSR of type 1rArr am =

xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1



bull Let the seed S0 be a-1 a-2 hellip a-n hellip

rArr G(x) = =

rArr G(x) = under GF(2)

rArr G(x) depends on the seed S0 and feedback coefficients

xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +

= 1 + C1x + C2x2 + hellip+ Cnxn

called the characteristic polynomial of the LFSR representing the linear feedback network

bull The degrees of all characteristic polynomials for an n-stage LFSR are nndash Eg

P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z




Maximum Length Sequences

bull If period p of the sequence generated by an n-stage LFSR is 2n-1 then it is a maximum length sequencendash 1rsquos = 0rsquos + 1

bull The characteristic polynomial associated with the maximum length sequence is a primitive polynomial



Primitive Polynomialsbull The number of primitive polynomials for n-

stage LFSR is given by

where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ



Some Primitive PolynomialsEg 20 3 0 for x20 + x3 + 1



An Example of LFSR

bull 23-1 = 7 ldquoalmost completerdquo patterns are generated

D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23



Off-Line BIST Architecturesbull Criteria

ndash Centralized or distributed BIST circuitryndash Embedded or separate BIST elements

bull Key elementsndash Test pattern generators (TPGs)ndash Output response analyzers (ORAs)ndash The circuits under test (CUTs)ndash A distribution system (DIST) for transmitting data from

TPGs to CUTs and from CUTs to ORAsndash A BIST controller for controlling the BIST circuitry

and CUT during self-test



CentralizedSeparate BIST (12)




bull During testing the BIST controller may carry out one or more of the following functionsndash Single-step the CUTs through some test

sequencendash Inhibit system clocks and control test clocksndash Communicate with other test controllers

possibly using test bussesndash Control the operation of a self-test



DistributedSeparated BIST



DistributedEmbedded BIST

The TPG and ORA elements are configured from functional elements within the CUT such as registers

Less hardware overheadLead to a more complex design



Factors for Choosing BIST Architecturesbull Degree of test parallelism (distributed darr)bull Fault coverage (distributed darr)bull Level of packaging (centralized darr)bull Test time (distributed darr)bull Physical constraints (embedded and separateuarr)bull Complexity of replaceable units (centralized darr)bull Factory and field of test-and-repair strategiesbull Performance degradation



Test-Per-Clock System

LFSR SR

CUT

MISR

Some new set of faults is tested during every clock period



Test-Per-Scan SystemLFSR SR

CUT

MISR SR

Each new set of faults being tested requiresOne clock to conduct the testA series of shifts of the scan chain (SR)

Complete that testRead out all of the test results



STUMPSbull Self-Test Using a MISR and Parallel Shift register

ndash Test-per-scan

LFSR (Pseudo-Random Test Pattern Generator)

SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn

Source Bardell ITCrsquo82



BILBObull Built-In Logic Block Observation

ndash Distributedembedded

BILBO register

BILBO0 0 shift mode0 1 reset1 0 LFSRMISR1 1 normal mode

Source Konemann 1979

z1 z2 zn

B1 B2



Applications of BILBO (12)bull Bus-Oriented structure



Applications of BILBO (22)bull Pipeline-oriented structure

POs



What to Do If 2n Is Too Large

bull Using pseudorandom testingndash Eg Generate only 232 test patterns

bull Using pseudoexhaustive testingndash Eg Partitioning



Pseudorandom Testingbull Weighted test generation

ndash The distribution of 0s and 1s produced on the output lines of TPGs is not necessary uniform

bull Adaptive test generationndash Modify the weights based on the simulation

resultsbull (advantage) efficient in terms of test lengthbull (disadvantage) the TPG hardware is more complex



Weighted Test Generation

bull Using an LFSR and a combinational circuit

D Q D Q D Q

The probability of 05 for a 1is changed to 025



Pseudoexhaustive Testing

bull Achieve many benefits of exhaustive testing but usually require far fewer test patternsndash Rely on various forms of circuit segmentation

and attempt to test each segment exhaustivelybull A segment is a subcircuit of a circuit C

ndash Segments need not be disjoint



Segmentation

bull Logical segmentationndash Sensitized path segmentationndash Cone segmentation (verification testing)

bull Physical segmentation



bull The circuit can be pseudoexhaustivelytested with 2n1 + 2n2 + 1 test patterns

n1

n2

C1

C2

Sensitized Path Segmentation (12)



Sensitized Path Segmentation (22)n1

n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation

bull An m-output circuit is logically segmented into m cones each cone consists of all logic associated with one outputndash Each cone is tested exhaustively and all cones

are tested concurrentlyhelliphellipndash Called verification testing by McCluskey[1984]



An (n w)-CUTbull [Definition] Consider a combinational circuit

C with inputs X = x1 x2 hellip xn and outputs Y= y1 y2 hellip ym Let yi = fi(Xi) where Xi sube X Let w = maxi|Xi| We denote this circuit as an (n w)-CUT ndash Pseudoexhaustively testing an (n w)-CUT needs at

least 2w test patterns



An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4

Pseudoexhaustively testing this (4 2)-CUT need at least 22 test patterns



Constant Weight Patternsbull [Definition] Let T be a set of n-tuples T is

said to exhaustively cover all k-subspaces if for all subsets of k bit positions each of the 2k

binary pattern appears at least once among the |T| n-tuplesndash Eg

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4

T can be a pseudoexhaustive test set for an (n w)-CUT if k ge w



Identification of Test Signal Inputsbull Consider a CUT with n inputs If none of

the outputs is a function of both inputs say a and b then the inputs a and b can be applied to the same test signal line

f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

apply x and z to the same test signal line



MTC Circuitsbull [Definition]A circuit is said to be a maximal-test-

concurrency(MTC) circuit if the minimal number of required test signals for the circuit is equal to the maximum number of inputs upon which any output depends

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)

A MTC circuit A non-MTC circuit



Identification of Minimal Set of Test Signals

Step 1 Generate a dependency matrix D = [dij] where dij = 1 if output i depends on input j otherwise dij = 0

Step 2 Partition the matrix into group of inputs so that two or more inputs in a group do not affect the same output

Step 3 Collapse each group to form an equivalent input called a test signal input



Example of Identification (12)

abcdefg

f1(a b e)f2(b c g)f3(a d e)

f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV

Transformation to a (4 3)-CUT



Physical Segmentation

bull Insert bypass storage cells (bscs) such that in the test mode each output and bscdepends on at most w inputs and bscsndash A bypass storage cell is similar to a cell used in

boundary-scan designbull In the normal mode the inserted bsc acts a wirebull In the test mode the inserted bsc can be part of an

LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5

Example of Physical Segmentation (16)



Example of Physical Segmentation (26)x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4




Pseudoexhaustive Testing by LFSRSR Chains

bull Step1 Partition the circuit under test(CUT) by inserting bypass storage cells(bscs)ndash Reduce the maximum dependency

bull Step 2 Route an LFSRSR chain with a primitive feedback polynomial through the primary inputs(PIs) and bscs



LFSRSR Chainsx4 + x3 + 1 (primitive)

PIs

+

BSCs

An LFSRSR chain with a primitive feedbackpolynomial of degree k generates the maximum sequence of length 2k-1

Exhaustively test each output cone



Residue Polynomials

bull For an LFSRSR with primitive feedback polynomial f(x) of degree k the residue Ri(x) of stage i is defined as

Ri(x) = xi mod f(x)

XOR network with f(x)210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri



Example of Residue Polynomials

+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5



Linear Independencybull [Theorem] An output cone depending on

the inputs p1hellip pk can be exhaustively tested hArr the corresponding residues Rp1

hellipRpk

are linear independent (LI)

210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G

XOR network with f(x)

R2 Rk-1 Rk is LIhArrThe cone of G is

exhaustively tested



Example of Linear Independency+

x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5

bull If some output cone C depends on inputs 0 3 and 4the output cone can be exhaustively tested

Because 1 x+1 x2+x is LI



Why Not Exhaustively Testingbull Subject to the input-output relation it is not

an easy task to construct a desirable LFSRSR chain as the pseudo-exhaustive TPG for the CUTndash Not all the output cones whose input residues

are LI that is linear dependent (LD)bull Called the LD problem



Possible Solutions to The LD Problembull To overcome the LD problem some variants of

LFSRSR have been proposedndash LFSRXORndash Reconfigurable LFSRSRndash Permuted LFSRSRndash Convolved LFSRSRndash Multiple LFSRSRndash Cell-reordering LFSRSRndash Constant-weight LFSRSRndash Linear-code LFSRSRndash Condensed LFSRSR

These solutions encounter serious problemsThe hardware overhead maybe largeThe construction time maybe long



LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network



Reconfigurable LFSRSR

0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed



Tree-Structured LFSRSR (TLS)

bull Rationalndash The SR chain of LFSRSR unnecessarily

constraints the searching domain for constructing a pseudo-exhaustive TPG

bull Constructionndash Step 1 Backbone generationndash Step 2 Tree growing

Source Rau et al ITCrsquo98



Backbone Generationbull Step 1 Use a selected primitive feedback

polynomial to construct the LFSR portionbull Step 2 Based on the LI constraint include

as many PIs or bscs as possible to a shift register(SR) chain connected to the LFSR with as little routing overhead as possibleThe constructed LFSR and SR portion is called the Backbone



Example of Backbone Generation (12)






Tree Growing

bull Based on the LI constraint try to connect isolated PIs or BSCs to the backbone with as little routing overhead as possible



Example of Tree Growing



XOR-Tree Generation

bull There may be PIs or BSCs which can not be included in the scan tree after the backbone generation and tree growing processesndash Because the LI requirement can not be

satisfiedndash Referred to as the linear dependent (LD)

problem



Overcoming The LD Problem

bull How to overcome the LD problem using as few XORs as possiblendash Use nonzero-terms of polynomial to directly

synthesize the required residuesndash Eg Under polynomial f(x) = x3 + x + 1 we can

synthesize R4 (x2 + x) with ldquoR2 (x2) xor R1(x)rdquo



Looking for Proper Residues

Rj

XOR network with f(x)210 k-1

R0 R1 R2 Rk-1

i

Ri

jN

bull [Theorem] There must exist a residue Rj j gt i to avoid the LD problem



Residue Replacementbull Synthesize an XOR network from the exited

backbone and tree branches for shorter routingdistance oplus

backbone

branches

isolated oplus



Residue Replacement Process

bull Under the polynomial f(x) = x4 + x3 +1 We can synthesize residue R10 with the existent residues R5 and R6 as follows

R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7



Simulation Results of TLS (12) (n m k) Ckt Before Partitioning After Partitioning C432 (36 7 36) (56 27 20) C499 (41 32 41) (49 40 14) C880 (60 26 45) (75 41 20) C1355 (41 32 41) (49 40 14) C1908 (33 25 33) (47 39 19) C2670 (233 140 122) (262 169 20) C3540 (50 22 50) (118 90 20) C5315 (178 123 67) (225 170 20) C6288 (32 32 32) (87 87 20) C7552 (207 108 194) (296 197 20)



Simulation Results of TLS (22)

PIsBSCs [16] Ckt (n m k) CPU time Backbone Branches Isolated XORs XORs

C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31



Solutions of BIST (12)

bull Exhaustivepseudoexhaustive testingbull Weighted pseudorandom testingbull Mixed mode test pattern generation

ndash Pseudorandom test patterns firstndash Deterministic test patterns followed

bull Donrsquot consider the fact that the test pattern are given in a form of testcubes with unspecified inputs




bull Reseeding ndash Change the seeds as needed

bull Reprogram the characteristic polynomialbull Combination of two or more of the above

methods



Notes

Chapter 9

Boundary-Scan Testing



Board Level Testing

Sn m

Sn m

n

mMUXm

TNIsolate one module (chip) from the others

Test chips and chip interconnectionsRaise the concept of boundary-scan testing

R1

R2



History of Boundary-Scan Testingbull 1988 Joint Test Action Group (JTAG)

proposed Boundary-Scan Standardbull 1990

ndash Boundary-Scan approved as IEEE 11491ndash Boundary-Scan Description Language (BSDL)

proposed by HPbull 1993 11491a approved to replace 11491bull 1994 11491b BSDL approved



1149111491a

bull Testing of digital chips and interconnections between chips

bull Widely used in industryndash Eg advance CPU HDTV satellite systemhelliphellip



Chip Architecture for 11491

TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic

OptionalBIST registersScan registers

MRs Miscellaneous Registers Boundary-Scan Cell

Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad



A Typical Boundary-Scan Cell (13)

0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control



bull As an input boundary-scan cell INcorresponds to a chip input pad OUT is tied to a normal input to the application logic

bull As an output boundary-scan cell IN corresponds to the output of the application logic OUT is tied to an output pad




bull Operation Modesndash Normal Mode Mode_Control = 0

bull IN -gt OUTndash Scan Mode ShiftDR = 1 ClockDR

bull TDI-gthellip-gtSIN-gtSOUT-gthellip-gtTDOndash Capture Mode ShiftDR = 0 ClockDR

bull IN-gtQA

ndash Update Mode Mode_Control = 1 UpdateDRbull QA-gtOUT




Board And Chip Testing

Application Logic 2

Application Logic 3 Application Logic 4

TDI

TDO

Application Logic 1



Board And Chip Test Modes

bull External Test Modendash Test the interconnection between the chips of

boardbull Sample Test Mode

ndash Sample and shift out or shift in data without interfering the normal operation of board

bull Internal Test Modendash Test the chips of board



External Test Mode (14)

Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)



Sample Test Mode (12)

0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out



Internal Test Mode (12)

Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO



Test Bus (12)bull A board supporting 11491 contains a test bus

consisting of at least four signalsndash TDI Test Data Inputndash TDO Test Data Outputndash TMS Test Mode Selectorndash TCK Test Clockndash TRST(optional) Test Reset



Test Bus (22)

bull These signals are connected to a chip via its test-bus portsndash Ring configurationndash Star configuration

bull Each chip is considered to be a slave bus and the bus is assumed to be driven by a bus master



Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Test-Bus Circuitry (12)

bull The (on-chip) test-bus circuitry allows access to and control of the test features of a chip consisting of four main elementsndash Test access port(TAP)ndash TAP controller(TAPC)ndash A scannable instruction register and associated

logicndash A group of scannable test data registers(TDRs)



Test-Bus Circuitry (22)Boundary-scan register

Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK

Test data registers(TDRs)

TDI

optional

optional

Device identification register

User test data register

TAPC

IR clocks and controls

TDR clocks and controls

SelectEnable

OutputBuffer

Instruction register



TAPC

bull A synchronous finite state machine with 16statesndash Inputs TCK TMSndash Outputs ShiftDR ClockDR UpdateDR ShiftIR

ClockIR UpdateIR Select Enable TCK (optional) TRST



States of TAPC (12)bull Test-Logic-Reset normal modebull Run-TestIdle wait for a internal test such

as BISTbull Select-DR-Scan initial a scan-data

sequence for the selected registersbull Capture-DR load data in parallelbull Shift-DR load data in serialbull Exit1-DR finish phase-1 shifting of data



States of TAPC (22)bull Pause-DR temporarily halt the scan

operation to allow the bus master to reload datandash Necessary during the transmission of long test

sequencesbull Exit2-DR finish phase-2 shifting of databull Update-DR parallel load from associated

shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

State Diagram of TAPCTest-Logic-Reset

Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1

Control of data registers Control of instruction register

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-DR-Scan Select-IR-Scan

Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers

bull Test Data Registers(TDRs)ndash Boundary-scan registersndash Bypass register(1-bit)ndash Device Identification registersndash Registers that are part of the application logic

itself



bull Instruction Register(IR)ndash Shift in a new instruction while holding the

current instruction fixed as its output portsndash Specify operations to be executedndash Select TDRs

bull Each instruction enables a single serial test-data register path between TDI and TDO

Instruction Register and Instructions (12)




bull Instructionsndash Mandatory

bull BYPASS to reduce the length of the scan pathbull EXTEST external test modebull SAMPLE sample test mode

ndash Recommendedbull INTEST internal test modebull RUNBIST for the Run-TestIdle State



BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2



Summaries of Boundary-Scan Operations

bull Instructions are sent serially over TDI into the instruction register

bull Selected test circuitry is configured to respond to the current instruction

bull Test instruction is to be executedbull Test results are shifted out through TDO

new test data on TDI may be shifted in at the same time



bull Now the IEEE 11491b standardbull Purposes (12)

ndash To provide a standard description language for boundary scan devices

ndash To simplify the design work for boundary scan ndashautomated synthesis is possible

ndash To promote consistency throughout ASIC designers device manufacturers foundries test developers and ATE manufacturers

Boundary Scan Description Language (BSDL) (12)




bull Purposes(22)ndash For easy incorporation into software tools for

test generation analysis and failure diagnosisndash To reduce possibility of human error when

employing boundary scan in a design

Chapter 10

Memory Testing



Fault Models (13)bull Stuck-at fault (SAF)

ndash The logic value of a cell or a line is always 0 or 1

bull Transition fault (TF)ndash A cell or a line that fails to undergo a 0rarr1 or

a 1rarr0bull Coupling fault (CF)

ndash A write operation to one cell changes the contents of a second cell



Fault Models (23)

bull Neighborhood Pattern Sensitive Fault (NPSF)ndash The content of a cell or the ability to change its

content is influenced by the contents of some other cells in the memory



Fault Models (33)

bull Address Decoder Fault (AF)ndash Any fault that affects address decoder

bull With a certain address no cell will be accessedbull A certain cell is never accessedbull With a certain address multiple cells are accessed

simultaneouslybull A certain cell can be accessed by multiple addresses



Memory Chip Test Algorithms

bull Traditional testsbull Tests for SAFs TFs and CFsbull Tests for NPSFs



Traditional TestsAlgorithms Test length Order

n is the number of bits of the memory array



Test Time as A Function of Memory Size

Cycle time 10 nsn is the number of bits of the memory array



Notation of March Test Algorithms

bull uArr address 0 to address n-1bull dArr address n-1 to address 0bull either waybull w0 write 0bull w1 write 1bull r0 read a cell whose value should be 0bull r1 read a cell whose value should be 1

hArr



March Test Algorithm MATS

bull Modified Algorithmic Test Sequencendash (w0) (r0 w1) (r1)

Step 1 write 0 to all cellsStep 2 for each cell

read 0 and write 1Step 3 read 1 from all cells

hArr hArr hArr



Other March Test Algorithms (13)

bull MATS+ndash (w0) uArr(r0 w1) dArr(r1 w0)

bull Marching 10ndash (w0) uArr(r0 w1 r1) dArr(r1 w0 r0)

(w1) uArr(r1 w0 r0) dArr(r0 w1 r1)bull MATS++

ndash (w0) uArr(r0 w1) dArr(r1 w0 r0)

hArrhArr

hArrhArr



bull MARCH Xndash (w0) uArr(r0 w1) dArr(r1 w0) (r0)

bull MARCH C-ndash (w0) uArr(r0 w1) uArr(r1 w0)

dArr(r0 w1) dArr(r1 w0) (r0)bull MARCH A

ndash (w0) uArr(r0 w1 w0 w1) uArr(r1 w0 w1)dArr(r1 w0 w1 w0) dArr(r0 w1 w0)


hArr hArr

hArr

hArr

hArr



bull MARCH Yndash (w0) uArr(r0 w1 r1) dArr(r1 w0 r0) (r0)

bull MARCH Bndash (w0) uArr(r0 w1 r1 w0 r0 w1) uArr(r1 w0 w1)dArr(r1 w0 w1 w0) dArr(r0 w1 w0)


hArrhArrhArr



Tests for FaultsAlgorithms Test Length Fault CoverageMATS 4n Some AFs SAFsMATS+ 5n AFs SAFsMarching 10 14n AFs SAFs TFsMATS++ 6n AFs SAFs TFsMARCH X 6n AFs SAFs TFs some CFsMARCH C- 10n AFs SAFs TFs some CFsMARCH A 15n AFs SAFs TFs some CFsMARCH Y 8n AFs SAFs TFs some CFsMARCH B 17n AFs SAFs TFs some CFsn is the number of bits of the memory array



NPSF

bull ANPSFndash Active Neighborhood Pattern Sensitive Fault

bull PNPSFndash Passive Neighborhood Pattern Sensitive Fault

bull SNPSFndash Static Neighborhood Pattern Sensitive Fault



ANPSF

bull n changes rArr b changesndash Eg n 0 rArr 1

b 1 rArr 0

n n nn b nn n n

b base celln neighborhood cells



PNPSF

bull Contain n patterns rArr b cannot changendash Eg n 00000000 rArr b 0 or 1

n n nn b nn n n




SNPSF

bull Contain n patterns rArr b is forced to a certain valuendash Eg n 11111111 rArr b 1

n n nn b nn n n




DC Parametric Testing

bull OpenShort testbull Power consumption testbull Leakage testbull Threshold testbull Output drive current testbull Output short current test



AC Parametric Testingbull Output signal

ndash The rise and fall timesbull Relationship between input signals

ndash The setup and hold timesbull Relationship between input and output

signalsndash The delay and access times

bull Successive relationship between input and output signalsndash The speed test



Dynamic Faults

bull Recovery faultsndash Sense amplifier recoveryndash Write recovery

bull Retention faultsndash Sleeping sicknessndash Refresh line stuck-at ndash Static data loss

bull Bit-line precharge voltage imbalance faults



BIST Pros And Consbull Advantages

ndash Minimal use of testersndash Can be used for embedded RAMs

bull Disadvantagesndash Silicon area overheadndash Speed slow access timendash Extra pins or multiplexing pinsndash Testability of the test hardware itselfndash A high fault coverage is a challenge



Architecture of a DRAM Chip



Typical Memory BIST Architecture



Multiple Memory BIST Architecture



Serial Testing of Embedded RAM



Built-In Self-Repair

bull BIST can only identify faulty chipbull Laser cut may be infeasible in some cases

eg field testingbull Two types

ndash Use fault-array comparatorbull Repair by cellbull Repair by column (or row)

ndash Using switch array



BIST Using Switch Array



BIST Using Fault-Address Comparison

Chapter 11

SOC Testing



System-on-A-Chip (SOC)bull Integrate all the function blocks of a

complete system into a single chip



Challenges vs Solutions

bull Challengesndash Capacityndash Design productivity gapndash Time-to-market (TTM)ndash helliphellip

bull Solutionsndash Core-based designndash Platform-based designndash helliphellip



Core-Based SOC Design

bull Coresndash Pre-defined pre-verified complex function

blocks also termed Virtual Components (VCs) or Intellectual Properties (IPs)

bull Core-based SOC designndash Reuse existed cores to implement a complete

system in a single chiprArrReduce TTM



SOC Components

bull Simple coresbull Complex coresbull User-define logic (UDL) bull Interconnect logic and wirerArr SOC testing should cover all the

components



SOC Design Flow

bull SOC components -- cores are only manufactured and tested in the final systemndash It is quite difficult to test the

individual coresbull Cores usually are protected

by laws



Core-Based Test Challenges

bull Distributed design and test developmentbull Test access to embedded coresbull SOC-level test optimization



Distributed Design and Test Development

bull Core providersndash Core-internal design DFT

bull Test pattern generation for coresbull Deliver cores with the complete tests

bull Core usersndash Chip-level DFT

bull Test pattern generation for chipsndash Reuse of core-level test patternsndash Additional test patterns for non-core circuitry



Test Access to Embedded Cores (12)

bull Many cores are (deeply) embedded rArr No direct (functional) access to core terminalsndash Other cores between SOC pins and core

terminalsndash Often core terminals gt SOC pins




bull To test cores as stand-alone unitsndash Provide core test access paths from SOC pins to

core terminalsndash Isolate cores such that external influence do not

hamper the core testndash Provide test access means for outward-facing

tests



SOC-Level Test Optimizationbull How are embedded cores tested

ndash Stand-alone vs merged with other modulesbull Optimization of test access infrastructure

ndash Test quality and bandwidth vs area and costbull Optimization of test execution and

schedulingndash Trade-offs between test vector count and

application time power dissipation and area



Solutions to Challenges

bull Distributed design and test developmentndash Standardized set of deliverables

bull Test access to embedded coresndash Standardized on-chip test access hardwarendash Tools for test translation

bull SOC-level test optimizationndash Tools to evaluate trade-offs



Test Access Architecture

bull Test pattern sourcesinkndash Generates test patternscompares test responses

bull Test access mechanism (TAM)ndash Transports test patternsresponses tofrom CUT

bull Core test wrapperndash Provides switching of core terminals to functional IO

or TAM



Off-Chip SourceSinkbull pins determines bandwidthbull More TAM area

ndash Requires expensive ATE



On-Chip SourceSinkbull Close to core-under-test (CUT)bull Less TAM area

ndash Requires lightweight ATEbull BIST IP area



TAM

bull Tasksndash Transport test patterns from source to CUTndash Transport responses from CUT to sink

bull Design parametersndash Width transport capacityndash Length transport distance



TAM Widthbull Transport capacity

ndash Minimum meet core testrsquos data ratendash Maximum bandwidth of sourcesink

bull Trade-offsndash Test qualityndash Test application time ndash Silicon area cost



TAM Lengthbull Physical distance

ndash On-chip sourcesink may shorten TAM lengthndash Sharing may shorten TAM length

bull Share TAM with functional hardwarebull Go through vs pass around other modulesbull Share TAMs between multiple cores



TAM Implementationsbull Multiplexed accessbull Reused system bus (AMBA)bull Transparency (Macro Test SOCET)bull Boundary Scan (JTAG partial-scan variants)bull Scalable TAMs (Test Bus Test Rail)

On one SOC different TAMs may co-exist



Multiplexed Access (13)

bull Connect wires to all core terminals and multiplex onto existing IC pins

bull Common practice for embedded memories

bull Also used for block-based ASICs

MUX

control



Benefits of Multiplexed Access

bull Each embedded core can be tested as stand-alone device

bull Translation from core-level test into IC-level test is simple

bull Simple silicon debug and diagnosis



Drawbacks of Multiplexed Accessbull Not scalable

ndash terminals of one core gt IC pinsbull Parallelserial conversion rArr at-speed testing is

difficult

ndash Too many embedded cores bull High area costs for connecting and multiplexing all

coresbull Control circuitry for the multiplexer grows more and

more complex



Analysis of Multiplexed Access (13)bull Let K be the number of SOC pins available

for scan test and M be the number of control pinsrArrThe number of scan chains as TAM N =

bull For core iisinC where C is the core setndash pi the number of test patternsndash fi the number of scannable flip-flops

bull In a balanced way each chain has flip-flops

ndash ti the test time

( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i



bull The test time ti of core i

can be reduced as

Analysis of Multiplexed Access (23)

pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

Scan-In Normal Scan-Out



bull The total test time T of the SOC

can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max



Reused System Busbull Many SOCs have an on-chip system bus

which connects to most cores especially the platform-based system

bull Reuse of the system bus as TAM is cheap wrt silicon area



An Example of Reused System Busbull ARMrsquos Advanced Microcontroller Bus

Architecture (AMBA)ndash The 32-bit system bus is used as TAM



Analysis of Reused System Busbull Benefits

ndash Low area cost for TAMndash Translation form core-level test into IC-level

test is independent of SOC configurationbull Drawbacks

ndash Not scalablebull Fixed bus width does not allow trade-offs

(area quality test time)ndash Functional test approach of ARM core

dominates overall IC test approachbull Difficult to integrate scan design or BIST



Transparencybull Transparent path

ndash Path from input to output which propagates data without information loss



Examples of Transparency

bull Scan chains bull Arithmetic functions add + 0 mult 1bull Embedded memories SRAM DRAM

ROMbull Basic gates AND OR INV MUX



Analysis of Transparency (12)

bull Benefitsndash Low area cost for TAM in case of reuse of

existing hardwarebull Drawbacks (12)

ndash Corersquos test access depends on other modulesndash Translation from core-level test into IC-level

test might be complicated eg latencies of cores



Analysis of Transparency (22)bull Drawbacks (22)

ndash During core design core environments are unknown

bull Insufficient transparency ndash core user has to add TAMs

bull Too much transparency ndash area costbull Multiple versions ndash expensive for core provider and

core user



Macro Test Philips Research

bull Generic approach for testing embedded modules

bull Originally focused on defect-oriented testing

bull Approach and tools proved useful for core test

bull May take advantage of transparent paths through modules

defect-oriented testing A type of testing where the nature of the test ismeant to directly exercise detect and isolate defects and defect effects rather than abstract fault models



SOCET PrincetonNEC

bull Core provider is responsible for testable and transparent cores

bull Design-for-transparency techniquebull Multiple versions of cores with different

area and transparency latency ndash Selection and trade-offs at SOC level



Boundary Scan (12)

bull Boundary Scan Test solves board-level interconnect testndash IEEE 11491 standard (lsquoJTAGrsquo)ndash ICs are components in SOB

bull Cores are components in SOC



Boundary Scan (22)



Examples of Boundary Scanbull Various Texas Instruments papers have

suggested the use of Boundary Scan as TAM

bull Partial Boundary Scan Ringndash No scan flip-flops on those inputs for which

stimuli can be justified from preceding logicndash ATPG techniques to find this out



Benefits of Boundary Scan

bull Existing well-known and well-documented standard

bull Reuse of IC-level BIST implementations augmented with private instructions for test debug emulation etc



Drawbacks of Boundary Scan

bull Fixed 1-bit TAM width does not allow trade-offs between silicon area test quality and test time

bull Intertwined test control and test data due to lack of pins

bull Multiple TAP controllers on one IC is against IEEE 11491 standard



Dedicated Scalable TAMs (12)bull Dedicated TAM

ndash Not through other modules or over existing buses bull Scalable TAM

ndash TAM width is variable to be chosen by core provideruser

bull Core user determines IC-level architecturendash How many TAMs of which widthndash Which configuration (bus rail etc)ndash Which core connects to which TAM



Dedicated Scalable TAMs (22)



Example I of Dedicated Scalable TAMs

Test Bus



Example II of Dedicated Scalable TAMs

TestRail



Analysis of Dedicated Scalable TAMs (12)

bull Benefitsndash Guaranteed test access

bull Accessibility of a core does not depend on neighboring circuitry

ndash Fast and easy test expansion bull No difficult path-finding through complicated

circuitry ndash Enable ldquoplug-n-playrdquo connection at IC levelndash Allow the trade-offs between area quality and

test time



Analysis of Dedicated Scalable TAMs (22)bull Costs

ndash Design timebull Can be minimized through standardization and

automation

ndash Silicon area ndash sharing with existing hardware is more difficult

bull But transistors are not as expensive as they used to be

ndash Performance impact bull Can be avoided if taken into account upfront



Daisychain Architecturecontrol



Analysis of Daisychain Architecture (12)

bull Reassign the indices of the cores according to a non-decreasing number of patternsndash We can scan in a pattern in all cores p1 times

pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛



bull Afterwards we put core 1 in by-pass mode and test next p2 ndash p1 patterns for the other cores

bull The total test time T of the SOC is


⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus



Distribution ArchitectureScan Enables



Si scan clocksli length of scan chains

Reduction of Idle TimeNormal

A single scan enable

Multiple scan enables



Analysis of Distribution Architecture

bull We define ni to be the number of scan chains of core i


pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max



The Scan Chain Distribution Problem (SCDP)bull Find a distribution of a given number of

scan chains over the cores such that the total test time is minimized

FF

FF

core

FF

FF

core

A single scan chain Two scan chains



The SCDP Algorithm



Reduction of Scan Controlsbull Distribute as fewer scan controls as possible

over the cores such that minimal time resulted form SCDP is still maintainedndash Constructing an additional scan chain needs to

remove two scan-control signalsndash Some cores are controlled by the same scan-

control signalbull An efficient algorithm has been presented

by Aerts et al ndash ITCrsquo98



Core Test Wrapperbull Interface between the CUT and the rest of

chipndash Provide switching capability between modes

bull Normal functional operationbull InTest inward-facing core test modebull ExTest outward-facing interconnect test modebull Bypass

ndash Width adaptationbull Serial-to-parallel conversion at core inputsbull Parallel-to-serial conversion at core outputs



Functional-Only Connections



Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass



Reasons for Modular Testingbull Test Quality

ndash Different circuit structures such as random logic memory hellip require different test methods

bull Blackboxed Embedded Corendash Implementation is not known forced to use the tests

developed by core provider

bull Divide-and-conquerndash Very large SOCs are intractable for ATPG or fault

simulation tools

bull Test Reusendash Module will be reused in other designs

Chapter 12

Introduction to IEEE P1500



IEEE P1500 lsquoSECTrsquo (12)bull Facilitate test interoperability of embedded

cores to improve efficiency of core creators integrators and manufacturersndash Standardize interface between core provider and

core userbull Core test information modelbull Test access to embedded cores

ndash Do not standardizebull Corersquos internal test methods and DFTbull Chip-level test integration and optimization



IEEE P1500 lsquoSECTrsquo (22)bull Membership of IEEE P1500 is on an individual

basis information and meetings are open to everyonendash httpgrouperieeeorggroups1500



IEEE P1500 Main Componentsbull Standardized scalable core test wrapperbull Core test information model

ndash Described in standardized Core Test Language (CTL)bull Two compliance levels

ndash IEEE 1500 Unwrappedndash IEEE 1500 Wrapped



IEEE P1500 for Mergeable Cores (13)bull Mergeable cores

ndash Cores that can be merged with surrounding circuitry to form one unit for testing

ndash Mergeable cores do not need to be mergedbull Eg Digital logic at RT- or gate-level



IEEE P1500 for Mergeable Cores (23)

MergeableEg digital logicAt RTgate-level

Non-MergeableEg layoutencrypted memory

Before integration

MergedCoremodule tested as part of its integration environment

Non-MergedCoremodule tested as aseparate entity with test patternsdeveloped for the coremoduleas a stand-alone unit

After integration



bull Challengesndash Most DFT insertion and test pattern generation take

place at gate-levelndash Core test cannot be re-used once core is mergedndash What to standardize for RTL- and other merged

cores to facilitate test interoperability




Standardized Wrapperbull IEEE P1500 is a core-level standard

ndash Implementation of SourceSink depends on test methods

ndash Implementation of TAMs depends on SOCndash Note IEEE P1500 only standardizes the

wrapper



Wrapper Functionsbull Transparent functional modebull Test access

ndash Inward-facing for core-internal tests (InTest)ndash Outward-facing for core-external tests (ExTest)

bull Switchable connection between core and TAM(s)ndash One lsquosingle-bit TAM Plugrsquo is mandatoryndash Zero or more lsquoMulti-bit TAM Plugsrsquo are optional

bull Optional lsquowidth adaptationrsquo for TAM plugs



The Wrapper Architecture



Wrapper Elements (12)bull Wrapper Instruction Register (WIR)

ndash Controls operation of wrapperndash Mandatory optional and user-defined instructions ndash Implementation requires shiftupdate registerndash Controlled directly from WIPndash Instructions are loaded via WSI-WSO

bull Wrapper Bypass Register (WBY)ndash Mandatory bypass for serial TAM

(between WSI-WSO)



Wrapper Elements (22)bull Wrapper Boundary Register (WBR)

ndash Controllabilityobservability on core terminalsndash Built from library of wrapper cellsndash In test mode configured to one or multiple test

access chainsndash Test data are loaded from WSI-WSO or

WPI-WPO



Wrapper Interface (12)bull Functional inputsoutputs

ndash Number names and functions match the corersquos functional inputsoutputs

bull Wrapper Interface Port (WIP)ndash 6-bit control port for WIR and Wrapper



Wrapper Interface (22)bull Serial interface WSI-WSO

ndash Load instructions into WIRndash Load test data into selected wrapper registers

(WBR WBY)bull Parallel interface WPI-WPO

ndash Load test data into WBRndash User-defined width

bull Zero or more parallel ports (typical one)



Wrapper Interface Register (WIR)bull Serial shiftupdate registerbull Scalable length

ndash Mandatory bits for mandatory wrapper modesndash Optional bits for optional wrapper modesndash User-defined bits



Wrapper Interface Port (WIP)bull Functions

ndash Control the operation of the WIRndash Control together with the WIR instruction the operation of the

wrapperbull Signals

WRCK lsquoWrapper Clockrsquo dedicated P1500 clock signal for WIR WBY optionally WBR

WRSTN lsquoWrapper Resetrsquo dedicated P1500 reset (asynchronous active-low) signal for WIR puts wrapper in Normal mode

SelectWIR (De-)selects WIR as register between WSI-WSO

CaptureWR Enables capture operation for selected register

ShiftWR Enables shift operation for selected register

UpdateWR Enables update operation for selected register



Basic Wrapper Cellbull Modes

ndash Normal mode normal = 1ndash Shift mode shift = 1

bull Controllabilityndash normal = 0 =gt value in SE is driven onto cfo

bull Observabilityndash shift = 0 =gt value at cfo is captured into SE



Wrapper Cell Optionsbull SEs can be shared with functional SEsbull Capture in Update SE instead of Shift SEbull Update SE that prevents ripple-through while

shiftingbull Multiple shift SEs for high-speed stimuli bull Mode in which lsquosafersquo value is presented at cfo



Wrapper Cell with Only ShiftCapture SE

Dedicated SE Shared SE



Wrapper Cell with ShiftCapture + Update SEs

Shared Updated SE

Dedicated SEs



Scalable Wrapper Cell



Wrapper Instruction Set



Serial Interface WSI-WSO (12)bull Mandatory serial interface is used for two

purposesndash Wrapper control load instructions into the WIRndash Low-bandwidth test data access to WBR (serial TAM)

bull P1500 envisions concatenated connectionndash Daisychain is a flat interconnection methodndash Supports hierarchical design

bull Consistent interface at every level of hierarchy



Serial Interface WSI-WSO (22)bull Concatenated serial mechanism easy to

connect to IEEE 11491 (JTAG) TAP and TAP Controllerndash Private instructions connect daisychained serial

mechanisms between TDI and TDOndash Cores can be tested and debugged even while

SOC is soldered onto PCB



Parallel Interface(s) WIP-WPO (12)bull Optional parallel interface(s) are used for test

data access to WBR with user-defined scalable bandwidth

bull Optionsndash Zero Low-bandwidth serial interface is only TAMndash One SOC manufacturing test takes place via Parallel

TAM bull Serial TAM is used for loading WIR instructions and

during board-level silicon debugndash Multiple Different core tests need different

bandwidths



bull P1500 supports many SOC-level configurationsndash Multiplexingndash Daisychainndash Distribution

Parallel Interface(s) WIP-WPO (22)



Typical Usage of P1500



P1500 Wrapper Parameters (12)bull Scalability in the follow parameters

ndash Bandwidthbull Number of WPI-WPO pairs (zero or more)bull Width of the WPI-WPO pairs (if present)

ndash Instructionsbull Optional instructionsbull User-defined instructionsbull OpCodes of instructions



bull WBR functionalityndash Shared or dedicated wrapper cellsndash Shift-only or Shift+Update wrapper cellsndash Storage capacity (one or more bits)ndash Location of capture (in Shift or Update register)ndash Ripple protection (with Update register or gate)ndash lsquoSafe statersquo output values

P1500 Wrapper Parameters (12)



Notes



P1500rsquos Information Model (12)

bull The information model should allow the SOC integrator or automation tools to successfully create a complete test for the SOC

bull The information model is captured in Core Test Language (CTL) a language for expressing test-related information for reusable cores



bull CTL is meant to co-exist and complement information expressed as a netlist

bull The CTL description of a P1500-compliant core allows to ndash Construct a wrapper and an appropriate TAMndash Configure the code to be testedndash Configure the core for its surroundings to be

testedndash Transform core-level into SOC-level test

patterns




IEEE 1450 (STIL)bull IEEE 1450 - Standard Test Interface Language

(STIL) for digital test vector datandash httpgrouperieeeorggroups1450

bull STIL is meant as a common interchange format between EDA test generation and ATE test application ndash STIL is capable of describing digital test vector datandash Focus on large volume of digital data

bull Developed by EDA vendors ATE vendors and IC manufacturers



IEEE P14506 (CTL) (12)

bull IEEE P14506 - Core Test Language bull Initially created by and developed within

IEEE P1500 to describe its information modelndash CTL syntax and semantics in IEEE P14506ndash Information model and CTL usage in IEEE

P1500



IEEE P14506 (CTL) (22)bull CTL uses STIL-like syntax

ndash Test patterns and waveforms are described in STIL

ndash CTL mandates separation of test patterns into test protocol and test data for easy expansion

ndash CTL-specific constructs describe corersquos test modes

ndash CTL-specific constructs describe corersquos integration



STIL - CTL Structure



CTL Key Words



Usage of MacroDefs (12)

bull STIL contains the construct MacroDefsndash This can be used for separating test protocol

and data in CTL this separation is mandatory



Usage of MacroDefs (22)bull Typical usage

ndash Voluminous test data is coded in separate CTL file

ndash CTL for lsquo1500-Unwrappedrsquo core references test patterns with a MacroDef applicable for unwrapped core

ndash CTL for lsquo1500-Unwrappedrsquo core references same test patterns but has an updated MacroDefs

ndash SOC-level test again references same test patterns but with yet another MacroDefs



Motivation for Dual Compliance Levels (12)

bull Testing an embedded core or module only works if properly isolated from the rest of the SOC and hence requires a wrapper

bull The P1500 wrapper is scalable in many aspects to allow optimization towardsndash Corendash SOC



bull In order to provide additional flexibility and support multiple use scenarios P1500 standardizes two separate compliance levels




Two Compliance Levels (12)

bull IEEE 1500 Unwrappedndash Core does not have a complete IEEE 1500

wrapper functionndash Core has a complete IEEE Information Model

which accurately describes the corersquos tests as well as provide all information on the basis of which the core could be made lsquoIEEE 1500 Wrappedrsquo (either manually or automatically by tools)




bull IEEE 1500 Wrappedndash Core incorporates complete IEEE 1500 wrapper

function ndash Core has a complete Information Model which

accurately describes the corersquos tests as well as the wrapper and how to operate it



P1500 Use Scenario 1 (13)

bull Core provider delivers lsquoIEEE 1500 Unwrappedrsquo corendash The Information Model that comes with it

contains all relevant core test knowledge including core-related data for generation of the IEEE 1500 wrapper




bull Core user makes core lsquoIEEE 1500 Wrappedrsquondash Adding IEEE 1500 Wrapperndash Upgrading the Information Model from bare

core terminals to wrapper terminals




bull Can take data specific to particular system-chip into account while instantiating the wrapper (eg TAMs width of TAMs rsquosafersquo state)

bull lsquoIEEE 1500 Unwrappedrsquo guarantees fast and reliable route to lsquoIEEE 1500 Wrappedrsquo



P1500 Use Scenario 2bull Core provider delivers lsquoIEEE 1500

Wrappedrsquo core of which the wrapper is built-to-order on customer specification

bull Similar to Scenario 1 except conversion done by core provider

bull Requires cooperative information exchangebull Core provider might have expertstools for

conversion




bull Core provider offers a catalogue of off-the-shelf lsquoIEEE 1500 Wrappedrsquo cores with fixed wrapper parameters

bull Core user selects the core which best matches the system chip needs

bull Allows to integrate wrapper with core in order to minimize costs




bull Scenario might be popular especially for hard cores

bull Large cataloguendash More work for core providerbut more choice

for core user



Usage of Dual Compliance Levels (12)

bull Full benefits of test interoperability are only obtained from a fully compliant lsquo1500-wrappedrsquo Core

bull Two compliance levels provide two optionsndash Make a core lsquo1500-wrappedrsquo compliant directly ndash Make an intermediate stop at lsquo1500-

Unwrappedrsquo



bull For this purpose lsquo1500-Unwrappedrsquo will also be fully standardized




SOC Test Creation

bull Distinguish two types of circuitry within SOC ndash IEEE 1500 Wrapped Coresndash lsquoOther Circuitryrsquo

bull Unwrapped coresbull Interconnect logic and wiring

bull IEEE P1500 facilitates SOC test for both types



Test Creation for Compliant Cores (13)

bull Test for IEEE 1500 Wrapped core is delivered with the core in its Information Modelndash No need for core user to know the

implementation details of the core to develop a test

ndash Test re-use



bull Test access to core is guaranteed (provided proper TAM connections are made)




bull Translation of test from wrapper boundary to SOC pinsndash In case of one-to-one relationship between core

terminals and SOC pins simple renaming suffices

ndash Sharing TAMs with multiple cores bypasses bidirectional TAMs complicate this process




Test Creation for lsquoOther Circuitryrsquo (12)

bull Test re-use not possiblebull Typically ATPG at SOC level is required

to generate test patterns for this circuitry bull IEEE 1500 Wrapped cores are tested by

their own patterns and do not need to be included in this



ndash Wrapped cores should be black-boxedbull For some cores not netlist available at allbull Even if netlist is available blackboxing will reduce

the compute time for ATPG for the other circuitry substantially

ndash The P1500 Information Model provides necessary information about controllability observability features in wrapper to APTG tool




Overview of Example

Given a very small scan-testablecorebull lsquo1500-Unwrappedrsquo compliant core

ndash P1500 Information Modelbull lsquo1500-Wrappedrsquo compliant core

ndash P1500 Wrapper ndash P1500 Information Model



Bare Core



STIL Test Patterns



Wrapped Core

WIP



Modes Instruction and Opcodes



Normal + Serial Bypass Modes

WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP



Parallel InTest Mode

WIP



Parallel ExTest Mode

WIP



Wrapper Design (12)

bull Automated wrapper designndash Library of wrapper cellsndash Wrapper configuration depends on core

terminal types ndash Optimization for test time

bull No industry-wide standard (yet)ndash Ad-hoc wrappers may not operate in concerto



Wrapper Design (22)

bull Optimal wrapper design algorithm for test time minimization

Ref [Marinissen et al ndash ITCrsquo00]



Wrapper Chain Design (12)

bull Wrapper itemsndash Wrapper input cellsndash Wrapper output cellsndash Core-internal scan chains




bull Wrapper chain designndash Designing the test access chains within the

wrapper from wrapperrsquos TAM input plug through all wrapper items to TAM output plug



Wrapper Chain Design amp Test Time (12)

bull lsquoTest Timersquo for large ICs is important cost factor ndash Test application time

=gt more time on ATE

ndash Size of test vector set =gt more expansive ATE



bull Wrapper chain design has large impact on test time ndash Partitioning which wrapper item in which

wrapper chainndash Ordering position of wrapper item in a

wrapper chainndash Bypasses shorten wrapper chain where

possible

3

2

1




Ordering of Wrapper Items



Bypasses (12)

bull Scan chain bypassndash Shortens wrapper chain length through during

ExTestbull Wrapper bypass

ndash Shortens wrapper chain length while testing other core up- or downstream in same TAM

ndash Contains register for plug-n-play connection of (possible) long wires



Bypasses (22)



Partitioning of Wrapper Items (12)

bull Partition ndash x wrapper input cells all of scan length 1ndash y wrapper output cells all of scan length 1ndash z core-internal scan chains which scan length Ii



bull over ndash m wrapper chains

(typically m lt z lt x+y+z)such that ndash scan-in length over all wrapper chains in

minimizedndash scan-out length over all wrapper chains in

minimized




Three-Step Solution Approach (13)

1 Find partition PS of z core-internal scan chains over m wrapper chains such that maximum sum of scan lengths in any wrapper chain is minimized

(Hard)



2 Assign x wrapper input cells to wrapper chains on top of PS such that maximum scan-in time of any wrapper chain is minimized

(Easy)




3 Assign y wrapper output cells to wrapper chains on top of PS such that maximum scan-out time of any wrapper chain is minimized

(Easy)




Wrapper Scan Chain Partitioning (12)

[Problem Definition]Givenndash Set of core-internal scan chains

S = S1 S2 hellip SZ with length L(Si)ndash m identical wrapper chains (typically mlt z)

Find ndash Partition P =P1 P2 hellip Pm of S such that

is minimizedsum isinlele P SLi

Smi)(max

1



bull Problem is equivalent to well-known NP-hard problems of Multi-Processor Scheduling and Bin Design




WSCP Algorithms (13)

Polynomial-time algorithms for near-optimal resultsbull LPT(Last Processing Time)

ndash Sort items from large to smallL(S1) ge L(S2) ge hellip ge L(Sz)

ndash Assign scan chains to shortest wrapper chain so far

Ref [Grahamrsquo69]




bull COMBINEndash Use LPT to obtain start solution ndash Linear Search over maximum wrapper chain

lengths bull Try whether wrapper items fit a wrapper chain

length with FFD (First Fit Decreasing)

Ref [Coffman Garey Hohnson78]




bull LPT is fast and has good resultsndash COMBINE produces sometimes better

resultsat the expense of more CPU time



Example Core (12)

bull Core characteristicsndash Terminals

8 functional inputs a[07]

11 functional outputs z[010]

9 scan inputs si[08]

9 scan outputs so[08]

+ 1 scan enable sc

38 core terminals in total

ndash Core-internal scan chains lengths 12 6 8 6 6 12 6 8 8 flip flops



Example Core (22)

bull Desired wrapper characteristicsndash Serial TAMndash 3-bit parallel TAMndash Wrapper bypassndash No scan chain bypasses



Wrapper Result (14)bull Algorithmic results

ndash LPT max length = 26P1 = 12 8 6P2 = 12 6 6P3 = 8 8 6

ndash COMBINE max length = 24P1 = 12 12P2 = 8 8 8P3 = 6 6 6 6



Wrapper Result (24)

bull Operation modes (13)ndash Serial access

bull All wrapper items connected into one chain



Wrapper Result (34)

bull Operation modes (23)ndash Parallel access

bull All wrapper items divided over the (three) wrapper chains according to COMBINE



Wrapper Result (44)

bull Operation modes (33)ndash Parallel pass

bull Bypass over the (three) wrapper chains



Compliance Checking (12)

bull Automatic check to assure that Core + Wrapper are compliant to standard

bull Relevant to both core provider and core user as compliance guarantees interoperability of this core with others at SOC level




bull No industry-wide standard (yet)ndash Current compliance checkers only work for

company-internal standardsbull Wrapper generator and compliance checker

might work in concerto

Ref [Marinissen et al - ITC00]



Wrapper Generator + Compliance Checker (13)

bull Automated wrapper design ndash corersquos netlist availablendash Compliance checker identifies still missing

wrapper functionality ndash Wrapper generator adds only required missing

hardwarendash Optional compliance checker for outgoing

inspection



bull Automated wrapper design ndash corersquos netlist not availablendash Wrapper generator adds full wrapper

functionalityndash Optional compliance checker for outgoing

inspection bull Manual wrapper design

ndash compliance checker for outgoing inspection




bull Wrapped core usage ndash compliance checker for incoming inspection




ExTest test Generation (12)

bull Test patterns for cores come from core provider

bull Core user is responsible for test patterns of SOC-specific circuitryndash Interconnect wiring ndash Interconnect logic(lsquoglue logicrsquo)ndash SOC-specific modules(lsquoUDLrsquo)

Interconnect ATPG

Normal ATPG




bull Interconnect ATPGndash lsquoLow-fatrsquo netlistndash Specific fault model for interconnect



Interconnect Faults



Interconnect ATPG

bull Determine a set of tests to detectndash Any interconnection open (S1 or S0)ndash Any shorted pair of net (wired-AND or wired-

OR)bull Solution is known as the ldquoCountingrdquo

algorithm



TAM Architecting (12)

bull Decision support to analyze and evaluate trade-offs for various TAM architectures at SOC levelndash How many TAMsndash Which core connects to which TAMndash How wide is each TAMndash How is the wrapper designed




bull Impact onndash Test quality ndash Test time ndash Areandash Dissipationndash Performance impact



Three TAM Architectures

Ref [Aerts amp Marinissen - ITC98]



Multiplexing Architecture



Daisychain Architecture



Distribution Architecture



Architecture Model



Improved Wrapper Design

Source [Iyengar et al ndash ITCrsquo01]



TAM Architecting with Fixed Widths (14)












Problem Formalization (13)

bull PW Design a wrapper for a given core such that ndash The core testing time in minimized ndash The TAM width required for the core is minimized

bull PAW Determinendash An assignment of cores to TAMs of given widthsndash A wrapper design for each core

such that the SOC testing time is minimized




bull PPAW Determinendash A partition of the total TAM width over the given number of

TAMs ndash An assignment of cores to TAMs of given widthsndash A wrapper design for each core





bull PNPAW Determine ndash The number of TAMs for the SOCndash A partition of the total TAM width over the given number of





More Research Neededbull Many interesting research results are

appearing in this domainbull TAM architecting and test scheduling are

intertwinedbull Most of todayrsquos approaches focus only on

ndash lsquoTest-busrsquo like TAMs (and ignore other TAM types)

ndash InTests (and ignore ExTests)ndash Test time (and ignore other costs)



Test Expansion

bull Translation of ndash Core-level test (defined at core terminals)intondash SOC-level test defined at IC pins)

bull Test Protocol Expansion

Ref [Marinissen amp Lousberg ndash TEC97 ETW99]



Macro Test Concept Overview (13)

bull Test = test protocol + test patternsbull Subsequent tasks automated

ndash Test protocol expansion (TPE)ndash Test protocol scheduling (TPS)ndash Test assembly (TASS)

bull Support of multiple hierarchy levels



bull Supports every kind of test access mechanismndash Original forcus on transparency of macros

especially core-internal scan chains







Terminology (12)

bull Pattern ndash A vector with stimulus and response values

bull Pattern List ndash The list of all patterns needed for a test of a

macrobull Test Protocol

ndash The prescription according to which a pattern should be applied



Terminology (22)

bull Testndash Repeated execution of a test protocol where

every time another pattern from the pattern list is filled in



Simple Example (12)

Ref [Marinissen amp Lousberg ndash ETW99]



Simple Example (22)



Transfer through Neighbors



Example SOC



Test Protocol Expanded to SOC Pins



Test Assembly



Test Assembly Example



Test Scheduling (12)

bull Minimization of occupancy of resources for given core tests and SOC test infrastructure




bull Resources ndash Power dissipation during test executionRef[Zorian ndash VTS93]

[Saluja amp Agrawal ndash Trans VLSI System97]

ndash Test application timestorage capacity at ATERef[Marinissen amp Aerts ndashTECS98]

[Chakrabarrty ndash ICCAD99 TCAD00][Iyengar amp Chakrabarrty ndash VTS01][Larsson amp Peng - DATE01]



Modifiedhelliphellip



Examples of Cores

bull Processor ARM hellipbull Memory RAM ROM hellipbull DSP TI hellipbull Peripheral DMA controller hellipbull Interface PCI USB UART hellipbull Multimedia JPEG MPEG hellipbull Networking Ethernet controller hellip



Chip and Board Testing

DFT BISThelliphellip

Boundary Scanhelliphellip



Virtual Component (VC)

bull A design block that meets the VSI (Virtual Socket Interface) specification and is used as a component in the virtual socket design environmentndash VSI is supported by the VSI Alliance (VSIA)

httpwwwvsiacom



Intellectual Property (IP)

bull The rights in cores that allow the owner of those rights to control the exploitation of those cores and the expression of the cores by othersndash Protected by lawsndash Liability in cases of failure



Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]



bull Sequential controllability and observabilitybull Bugs 136amp137 144(modified)



bull A fault model is an abstraction of the error caused by a particular physical faultsndash The purpose is to simplify the test procedure

and reduce its cost while still retaining the capability of detecting the presence of the modeled faults

ndash Defects vs faults vs errors vs failuresndash Permanent faults vs non-permanent ones



Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM

IP 1BUS amp INTERCONNECT

ASIC 1

UDL

DSP CPU ASIC 2IP 2



Text Books

bull M L Bushnell and V D Agrawal Essentials of Electronic Testing for Digital Memory amp Mixed-Signal VLSI CircuitsKluwer Academic Publishers 2000

bull M Abramovici M A Breuer and A D Friedman Digital Systems Testing and Testable Design Computer Science Press New York 1990



Outline (12)




Outline (22)


Chapter 1

Introduction




Design the circuit

Verify the design





Design Errors

TestPlans






verifytest

testtest










Why Testing


Vdd

10

00

0

0




How to Do Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

GoodBad






some time





Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632




Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R




responses Rrsquo



Circuit Modeling



algorithms



Fault Modeling















EA

B

C

D F

G




D s-a-1D s-a-0

14 faults











Vdd

10

00

0

0


xf s-a-1





CA

B




1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts




Testing





EA

B

C

D F

G

1

10

0

01

1






B

C

D F

G

1

100

0

01

10

x






CA

B 1

10






A

B

C

D s-a-0

E

F

x















more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No





A

B

C

D s-a-1

E

F

x





D

clk

Q


PIs POs





100

of test patterns






Testing Costs













Chapter 2

Fault Models



Faults and Errors






Failures










































A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

















stuck-on

0






IDDQ fault





stuck-open

0 Z





patterns

stuck-open

10 0100


fault-free response

fault response




X X

R






slow

critical path






XY

XY

the clock interval

propagation delay










DecoderLi

Lj





S1

S3S2

I1O1 I2O2





S1

S3S2

IO IO



Memory Faults (12)






Memory Faults (22)





Coupling Faults






0 0 00 d b0 a 0






x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3




Sensitization





Detectability









1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing























2n+2

n+1 n+1

equivalence

n+2cup

[Proof]




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0






Tα

Tβ

Tβ supeTα











2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0









Checkpoints (13)





Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0





a

b

c

d

e


Chapter 3

Fault Simulation

























endend









D-FF

abc

d

e

f

Compiled-Code


Q D






end




c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1


0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1


















f1 s-a-0

f2 s-a-0

0

1

1
























0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0













Lc


[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type




c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1



g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0


c 1 b0 c0

d 1 b0 d0










ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0








PPSFP







p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1





Sensitive Inputs


ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1

















a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region






b

f

c

d e

g

h

i

1

0

11

1

0

1critical line



stem

branch

branch




b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region








Chapter 4






Impractical



TG from Truth Table


ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1







ab

c

f

α s-a-0




)()()( 1f0fdx

xdfii

i

oplus=







x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or




c

f

cb0cb1f0fda







ab

c

f

h = ab

caacac1f0fdh












vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations





c

f

10 = D

0

1

1

0

s-a-0D

h








endend







ab

c

f



1

1

0

s-a-0D





end








Implication




Decision Trees








Backtracking





0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc






decision problem










s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2








F S

G5 G6




s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D














q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1








return SUCCESSend


end












s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D




s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1











larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x


11

1 rarr

a




x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa





x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr




Before After

x

x1D


x

1


D rarr x


D rarr D rarr

D rarrx D

DD rarr

D


aD rarrx D

D0 rarr



Unique D-drive

Before


After

D rarr


D



x-path






DD

x

x x

x

x

00

11








D-Algorithm



only a single path




then return FAILURE


then return FAILURE













end


end D-alg




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1














abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01










abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1







f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D





D-frontieri k m

k m n

m nF

F S

i

n k

n m
















abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1


u1

u1

u1





bullV






i = Dd = 0


bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV



n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D





D-frontier

i k m

k m n

S

i

n

No backtracking










Inversion Parity



















end




fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x


fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101










Objective( )being


end




end




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D





(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n




(k 1) e = 0 e = 1j =0



j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D





a0b1

c1d1

e0F f1

S

1












ab f








ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05





C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656

No backtracking










Head Lines



head linesbound

DE

ABC

F

G




head linesbound

DE

ABC

F

G









FAN vs PODEM

head linesbound

DE

ABC

F

G


A1B0

F C0F

1

1

G0F

1

PODEM FAN







thenbegin


j for vk









value xadd (j c) to



value x








Stem_objectives






end Mbacktrace




0

1

0

1




AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )


A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C



empty

empty







end








End FAN( )



ATPG (12)






ATPG (22)






Sequential TG




1989]






initial states










I

OY1

Y2y1

y2 s-a-1

FF2

FF1





OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG










D D



























=

=FC

Chapter 5





































Initialization








ab z





ab

abab

ab

ab

z

z

z

z

z

z









D

C

Q

R



Observability (12)

P

QR

N


D

C

Q






ab

abab

ab

ab

z

z

z

z

z

z





zz1z2

zn





1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)





Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0






Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0














achieved






FC100

with DFT

of T

without DFT








DFT Techniques









C1 C2 C1 C2

jumper

CPOP





01-Injection

CP1

C1

CP0

C2

01-injection

C1C2


C1C2

CP1

OP OP

OP




NT

C1

CP C2

01-injection

MUX

0

1

OP




01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n





01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs




PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT




























PR

CLR

Vcc

Vcc

Q

Q





PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1




Vcc

t

VZ

Vcc

Z





C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s




during test

OSCC

OP

AB

01-I




into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2




CPdata inhibit

CPtest data

C


DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2





C1 C2

AB

C

D

E

F G

m ns

p

q





m

s

n

q

p



Logic Redundancy







paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO





DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC


SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK




Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR



















C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout






C

Rrsquo

Rs

PI PO

Sin Sout


shadow register





rate of the system








clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO











D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B






C

B

A

B

Normal mode A = 0

Test mode C = 0




Sout

Sin

CA

B





Sout

SinC2








Notes

Chapter 6










C1 C2 C3


One session




ndash C1 100 C2 200 C3 300


C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions









scan chains












partial scan

full scan

sequential TG

combinational TG











3

1 2 4 5 6







distance = 4

distance = 3












(not testable)



















end




= 695







combinational TG


BALLAST

(scanned FFrsquos)




Sout

Sin

HOLD(for test)









Circuit Model (14)









and HOLD







a scan register



Circuit Model (44)

R3












A B-structure





















construct SB















cycles





Sin


R3 R6





Mutiple ScanChains


Area Overhead


Extal Pins

Extral ClockControl


same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7




Challenges from ORA






























sum=i

irR1C )(




counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0


x1x2x3


Output Reponses







⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(




minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0






122)|(

1

minusminus

=minus

m

mr

TC1CrmMP




NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

















Signature Analysis










)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2








( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984





MISRs










Notes

Chapter 8










































Exhaustive Testing









there4





D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0


Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1






D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1




D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1





bull 0 10 0 01 0 1

0 10 0 11 1 0













xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1




rArr G(x) = =



xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +




P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z











where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ






An Example of LFSR


D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23































LFSR SR

CUT

MISR





CUT

MISR SR






ndash Test-per-scan


SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn






BILBO register



z1 z2 zn

B1 B2







POs
















D Q D Q D Q










Segmentation






n1

n2

C1

C2





n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation










An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4







⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4






f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0






f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)











abcdefg


f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV







LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5





y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4










PIs

+

BSCs





Residue Polynomials


Ri(x) = xi mod f(x)


R0 R1 R2 Rk-1 Rk Ri




+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5





hellipRpk


210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G



exhaustively tested




x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5















LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network




0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed





















Tree Growing







XOR-Tree Generation



problem










Rj


R0 R1 R2 Rk-1

i

Ri

jN






backbone

branches

isolated oplus





R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7








C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31












methods



Notes

Chapter 9




Board Level Testing

Sn m

Sn m

n

mMUXm



R1

R2









1149111491a






TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic



Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control











bull IN-gtQA






Application Logic 2


TDI

TDO

Application Logic 1











Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out




Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO







Test Bus (22)





Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS









Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK


TDI

optional

optional



TAPC



SelectEnable

OutputBuffer




TAPC













shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1


Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1


Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR


Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers


itself















BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2





















Chapter 10

Memory Testing










Fault Models (23)





Fault Models (33)




















hArr







hArr hArr hArr








hArrhArr

hArrhArr








hArr hArr

hArr

hArr

hArr






hArrhArrhArr






NPSF






ANPSF


b 1 rArr 0

n n nn b nn n n




PNPSF


n n nn b nn n n




SNPSF


n n nn b nn n n















Dynamic Faults


































Chapter 11

SOC Testing



















SOC Components


components



SOC Design Flow



by laws























tests




















or TAM











TAM























MUX

control











difficult



more complex








( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i




can be reduced as


pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛





can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max








































core user











SOCET PrincetonNEC






Boundary Scan (12)





Boundary Scan (22)






























Test Bus




TestRail








test time





automation











pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛






⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus















pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max





FF

FF

core

FF

FF

core




The SCDP Algorithm



















Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass








simulation tools


Chapter 12



























Before integration



After integration












wrapper















(between WSI-WSO)






WPI-WPO





















wrapperbull Signals
























Shared Updated SE

Dedicated SEs


























bandwidths



















Notes











patterns










IEEE P14506 (CTL) (12)



P1500













CTL Key Words























































conversion












for core user






Unwrappedrsquo







SOC Test Creation









ndash Test re-use

























Overview of Example






Bare Core



STIL Test Patterns



Wrapped Core

WIP







WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP




WIP




WIP



Wrapper Design (12)






Wrapper Design (22)























possible

3

2

1







Bypasses (12)







Bypasses (22)










minimized






(Hard)




(Easy)





(Easy)









Smi)(max

1











Ref [Grahamrsquo69]















Example Core (12)






+ 1 scan enable sc





Example Core (22)









Wrapper Result (24)





Wrapper Result (34)





Wrapper Result (44)





















inspection

















Interconnect ATPG

Normal ATPG







Interconnect Faults



Interconnect ATPG



algorithm
























Architecture Model












































Test Expansion




















Terminology (12)







Terminology (22)





Simple Example (12)




Simple Example (22)






Example SOC






Test Assembly




















Examples of Cores











httpwwwvsiacom







Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]











Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM


ASIC 1

UDL

DSP CPU ASIC 2IP 2



Outline (12)




Outline (22)


Chapter 1

Introduction




Design the circuit

Verify the design





Design Errors

TestPlans






verifytest

testtest










Why Testing


Vdd

10

00

0

0




How to Do Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

GoodBad






some time





Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632




Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R




responses Rrsquo



Circuit Modeling



algorithms



Fault Modeling















EA

B

C

D F

G




D s-a-1D s-a-0

14 faults











Vdd

10

00

0

0


xf s-a-1





CA

B




1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts




Testing





EA

B

C

D F

G

1

10

0

01

1






B

C

D F

G

1

100

0

01

10

x






CA

B 1

10






A

B

C

D s-a-0

E

F

x















more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No





A

B

C

D s-a-1

E

F

x





D

clk

Q


PIs POs





100

of test patterns






Testing Costs













Chapter 2

Fault Models



Faults and Errors






Failures










































A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

















stuck-on

0






IDDQ fault





stuck-open

0 Z





patterns

stuck-open

10 0100


fault-free response

fault response




X X

R






slow

critical path






XY

XY

the clock interval

propagation delay










DecoderLi

Lj





S1

S3S2

I1O1 I2O2





S1

S3S2

IO IO



Memory Faults (12)






Memory Faults (22)





Coupling Faults






0 0 00 d b0 a 0






x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3




Sensitization





Detectability









1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing























2n+2

n+1 n+1

equivalence

n+2cup

[Proof]




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0






Tα

Tβ

Tβ supeTα











2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0









Checkpoints (13)





Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0





a

b

c

d

e


Chapter 3

Fault Simulation

























endend









D-FF

abc

d

e

f

Compiled-Code


Q D






end




c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1


0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1


















f1 s-a-0

f2 s-a-0

0

1

1
























0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0













Lc


[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type




c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1



g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0


c 1 b0 c0

d 1 b0 d0










ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0








PPSFP







p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1





Sensitive Inputs


ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1

















a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region






b

f

c

d e

g

h

i

1

0

11

1

0

1critical line



stem

branch

branch




b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region








Chapter 4






Impractical



TG from Truth Table


ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1







ab

c

f

α s-a-0




)()()( 1f0fdx

xdfii

i

oplus=







x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or




c

f

cb0cb1f0fda







ab

c

f

h = ab

caacac1f0fdh












vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations





c

f

10 = D

0

1

1

0

s-a-0D

h








endend







ab

c

f



1

1

0

s-a-0D





end








Implication




Decision Trees








Backtracking





0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc






decision problem










s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2








F S

G5 G6




s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D














q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1








return SUCCESSend


end












s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D




s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1











larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x


11

1 rarr

a




x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa





x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr




Before After

x

x1D


x

1


D rarr x


D rarr D rarr

D rarrx D

DD rarr

D


aD rarrx D

D0 rarr



Unique D-drive

Before


After

D rarr


D



x-path






DD

x

x x

x

x

00

11








D-Algorithm



only a single path




then return FAILURE


then return FAILURE













end


end D-alg




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1














abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01










abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1







f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D





D-frontieri k m

k m n

m nF

F S

i

n k

n m
















abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1


u1

u1

u1





bullV






i = Dd = 0


bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV



n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D





D-frontier

i k m

k m n

S

i

n

No backtracking










Inversion Parity



















end




fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x


fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101










Objective( )being


end




end




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D





(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n




(k 1) e = 0 e = 1j =0



j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D





a0b1

c1d1

e0F f1

S

1












ab f








ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05





C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656

No backtracking










Head Lines



head linesbound

DE

ABC

F

G




head linesbound

DE

ABC

F

G









FAN vs PODEM

head linesbound

DE

ABC

F

G


A1B0

F C0F

1

1

G0F

1

PODEM FAN







thenbegin


j for vk









value xadd (j c) to



value x








Stem_objectives






end Mbacktrace




0

1

0

1




AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )


A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C



empty

empty







end








End FAN( )



ATPG (12)






ATPG (22)






Sequential TG




1989]






initial states










I

OY1

Y2y1

y2 s-a-1

FF2

FF1





OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG










D D



























=

=FC

Chapter 5





































Initialization








ab z





ab

abab

ab

ab

z

z

z

z

z

z









D

C

Q

R



Observability (12)

P

QR

N


D

C

Q






ab

abab

ab

ab

z

z

z

z

z

z





zz1z2

zn





1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)





Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0






Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0














achieved






FC100

with DFT

of T

without DFT








DFT Techniques









C1 C2 C1 C2

jumper

CPOP





01-Injection

CP1

C1

CP0

C2

01-injection

C1C2


C1C2

CP1

OP OP

OP




NT

C1

CP C2

01-injection

MUX

0

1

OP




01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n





01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs




PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT




























PR

CLR

Vcc

Vcc

Q

Q





PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1




Vcc

t

VZ

Vcc

Z





C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s




during test

OSCC

OP

AB

01-I




into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2




CPdata inhibit

CPtest data

C


DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2





C1 C2

AB

C

D

E

F G

m ns

p

q





m

s

n

q

p



Logic Redundancy







paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO





DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC


SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK




Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR



















C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout






C

Rrsquo

Rs

PI PO

Sin Sout


shadow register





rate of the system








clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO











D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B






C

B

A

B

Normal mode A = 0

Test mode C = 0




Sout

Sin

CA

B





Sout

SinC2








Notes

Chapter 6










C1 C2 C3


One session




ndash C1 100 C2 200 C3 300


C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions









scan chains












partial scan

full scan

sequential TG

combinational TG











3

1 2 4 5 6







distance = 4

distance = 3












(not testable)



















end




= 695







combinational TG


BALLAST

(scanned FFrsquos)




Sout

Sin

HOLD(for test)









Circuit Model (14)









and HOLD







a scan register



Circuit Model (44)

R3












A B-structure





















construct SB















cycles





Sin


R3 R6





Mutiple ScanChains


Area Overhead


Extal Pins

Extral ClockControl


same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7




Challenges from ORA






























sum=i

irR1C )(




counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0


x1x2x3


Output Reponses







⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(




minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0






122)|(

1

minusminus

=minus

m

mr

TC1CrmMP




NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

















Signature Analysis










)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2








( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984





MISRs










Notes

Chapter 8










































Exhaustive Testing









there4





D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0


Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1






D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1




D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1





bull 0 10 0 01 0 1

0 10 0 11 1 0













xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1




rArr G(x) = =



xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +




P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z











where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ






An Example of LFSR


D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23































LFSR SR

CUT

MISR





CUT

MISR SR






ndash Test-per-scan


SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn






BILBO register



z1 z2 zn

B1 B2







POs
















D Q D Q D Q










Segmentation






n1

n2

C1

C2





n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation










An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4







⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4






f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0






f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)











abcdefg


f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV







LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5





y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4










PIs

+

BSCs





Residue Polynomials


Ri(x) = xi mod f(x)


R0 R1 R2 Rk-1 Rk Ri




+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5





hellipRpk


210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G



exhaustively tested




x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5















LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network




0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed





















Tree Growing







XOR-Tree Generation



problem










Rj


R0 R1 R2 Rk-1

i

Ri

jN






backbone

branches

isolated oplus





R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7








C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31












methods



Notes

Chapter 9




Board Level Testing

Sn m

Sn m

n

mMUXm



R1

R2









1149111491a






TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic



Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control











bull IN-gtQA






Application Logic 2


TDI

TDO

Application Logic 1











Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out




Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO







Test Bus (22)





Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS









Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK


TDI

optional

optional



TAPC



SelectEnable

OutputBuffer




TAPC













shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1


Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1


Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR


Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers


itself















BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2





















Chapter 10

Memory Testing










Fault Models (23)





Fault Models (33)




















hArr







hArr hArr hArr








hArrhArr

hArrhArr








hArr hArr

hArr

hArr

hArr






hArrhArrhArr






NPSF






ANPSF


b 1 rArr 0

n n nn b nn n n




PNPSF


n n nn b nn n n




SNPSF


n n nn b nn n n















Dynamic Faults


































Chapter 11

SOC Testing



















SOC Components


components



SOC Design Flow



by laws























tests




















or TAM











TAM























MUX

control











difficult



more complex








( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i




can be reduced as


pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛





can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max








































core user











SOCET PrincetonNEC






Boundary Scan (12)





Boundary Scan (22)






























Test Bus




TestRail








test time





automation











pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛






⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus















pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max





FF

FF

core

FF

FF

core




The SCDP Algorithm



















Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass








simulation tools


Chapter 12



























Before integration



After integration












wrapper















(between WSI-WSO)






WPI-WPO





















wrapperbull Signals
























Shared Updated SE

Dedicated SEs


























bandwidths



















Notes











patterns










IEEE P14506 (CTL) (12)



P1500













CTL Key Words























































conversion












for core user






Unwrappedrsquo







SOC Test Creation









ndash Test re-use

























Overview of Example






Bare Core



STIL Test Patterns



Wrapped Core

WIP







WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP




WIP




WIP



Wrapper Design (12)






Wrapper Design (22)























possible

3

2

1







Bypasses (12)







Bypasses (22)










minimized






(Hard)




(Easy)





(Easy)









Smi)(max

1











Ref [Grahamrsquo69]















Example Core (12)






+ 1 scan enable sc





Example Core (22)









Wrapper Result (24)





Wrapper Result (34)





Wrapper Result (44)





















inspection

















Interconnect ATPG

Normal ATPG







Interconnect Faults



Interconnect ATPG



algorithm
























Architecture Model












































Test Expansion




















Terminology (12)







Terminology (22)





Simple Example (12)




Simple Example (22)






Example SOC






Test Assembly




















Examples of Cores











httpwwwvsiacom







Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]











Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM


ASIC 1

UDL

DSP CPU ASIC 2IP 2



Outline (22)


Chapter 1

Introduction




Design the circuit

Verify the design





Design Errors

TestPlans






verifytest

testtest










Why Testing


Vdd

10

00

0

0




How to Do Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

GoodBad






some time





Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632




Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R




responses Rrsquo



Circuit Modeling



algorithms



Fault Modeling















EA

B

C

D F

G




D s-a-1D s-a-0

14 faults











Vdd

10

00

0

0


xf s-a-1





CA

B




1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts




Testing





EA

B

C

D F

G

1

10

0

01

1






B

C

D F

G

1

100

0

01

10

x






CA

B 1

10






A

B

C

D s-a-0

E

F

x















more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No





A

B

C

D s-a-1

E

F

x





D

clk

Q


PIs POs





100

of test patterns






Testing Costs













Chapter 2

Fault Models



Faults and Errors






Failures










































A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

















stuck-on

0






IDDQ fault





stuck-open

0 Z





patterns

stuck-open

10 0100


fault-free response

fault response




X X

R






slow

critical path






XY

XY

the clock interval

propagation delay










DecoderLi

Lj





S1

S3S2

I1O1 I2O2





S1

S3S2

IO IO



Memory Faults (12)






Memory Faults (22)





Coupling Faults






0 0 00 d b0 a 0






x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3




Sensitization





Detectability









1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing























2n+2

n+1 n+1

equivalence

n+2cup

[Proof]




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0






Tα

Tβ

Tβ supeTα











2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0









Checkpoints (13)





Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0





a

b

c

d

e


Chapter 3

Fault Simulation

























endend









D-FF

abc

d

e

f

Compiled-Code


Q D






end




c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1


0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1


















f1 s-a-0

f2 s-a-0

0

1

1
























0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0













Lc


[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type




c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1



g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0


c 1 b0 c0

d 1 b0 d0










ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0








PPSFP







p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1





Sensitive Inputs


ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1

















a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region






b

f

c

d e

g

h

i

1

0

11

1

0

1critical line



stem

branch

branch




b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region








Chapter 4






Impractical



TG from Truth Table


ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1







ab

c

f

α s-a-0




)()()( 1f0fdx

xdfii

i

oplus=







x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or




c

f

cb0cb1f0fda







ab

c

f

h = ab

caacac1f0fdh












vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations





c

f

10 = D

0

1

1

0

s-a-0D

h








endend







ab

c

f



1

1

0

s-a-0D





end








Implication




Decision Trees








Backtracking





0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc






decision problem










s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2








F S

G5 G6




s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D














q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1








return SUCCESSend


end












s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D




s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1











larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x


11

1 rarr

a




x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa





x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr




Before After

x

x1D


x

1


D rarr x


D rarr D rarr

D rarrx D

DD rarr

D


aD rarrx D

D0 rarr



Unique D-drive

Before


After

D rarr


D



x-path






DD

x

x x

x

x

00

11








D-Algorithm



only a single path




then return FAILURE


then return FAILURE













end


end D-alg




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1














abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01










abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1







f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D





D-frontieri k m

k m n

m nF

F S

i

n k

n m
















abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1


u1

u1

u1





bullV






i = Dd = 0


bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV



n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D





D-frontier

i k m

k m n

S

i

n

No backtracking










Inversion Parity



















end




fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x


fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101










Objective( )being


end




end




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D





(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n




(k 1) e = 0 e = 1j =0



j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D





a0b1

c1d1

e0F f1

S

1












ab f








ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05





C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656

No backtracking










Head Lines



head linesbound

DE

ABC

F

G




head linesbound

DE

ABC

F

G









FAN vs PODEM

head linesbound

DE

ABC

F

G


A1B0

F C0F

1

1

G0F

1

PODEM FAN







thenbegin


j for vk









value xadd (j c) to



value x








Stem_objectives






end Mbacktrace




0

1

0

1




AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )


A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C



empty

empty







end








End FAN( )



ATPG (12)






ATPG (22)






Sequential TG




1989]






initial states










I

OY1

Y2y1

y2 s-a-1

FF2

FF1





OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG










D D



























=

=FC

Chapter 5





































Initialization








ab z





ab

abab

ab

ab

z

z

z

z

z

z









D

C

Q

R



Observability (12)

P

QR

N


D

C

Q






ab

abab

ab

ab

z

z

z

z

z

z





zz1z2

zn





1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)





Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0






Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0














achieved






FC100

with DFT

of T

without DFT








DFT Techniques









C1 C2 C1 C2

jumper

CPOP





01-Injection

CP1

C1

CP0

C2

01-injection

C1C2


C1C2

CP1

OP OP

OP




NT

C1

CP C2

01-injection

MUX

0

1

OP




01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n





01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs




PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT




























PR

CLR

Vcc

Vcc

Q

Q





PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1




Vcc

t

VZ

Vcc

Z





C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s




during test

OSCC

OP

AB

01-I




into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2




CPdata inhibit

CPtest data

C


DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2





C1 C2

AB

C

D

E

F G

m ns

p

q





m

s

n

q

p



Logic Redundancy







paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO





DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC


SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK




Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR



















C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout






C

Rrsquo

Rs

PI PO

Sin Sout


shadow register





rate of the system








clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO











D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B






C

B

A

B

Normal mode A = 0

Test mode C = 0




Sout

Sin

CA

B





Sout

SinC2








Notes

Chapter 6










C1 C2 C3


One session




ndash C1 100 C2 200 C3 300


C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions









scan chains












partial scan

full scan

sequential TG

combinational TG











3

1 2 4 5 6







distance = 4

distance = 3












(not testable)



















end




= 695







combinational TG


BALLAST

(scanned FFrsquos)




Sout

Sin

HOLD(for test)









Circuit Model (14)









and HOLD







a scan register



Circuit Model (44)

R3












A B-structure





















construct SB















cycles





Sin


R3 R6





Mutiple ScanChains


Area Overhead


Extal Pins

Extral ClockControl


same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7




Challenges from ORA






























sum=i

irR1C )(




counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0


x1x2x3


Output Reponses







⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(




minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0






122)|(

1

minusminus

=minus

m

mr

TC1CrmMP




NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

















Signature Analysis










)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2








( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984





MISRs










Notes

Chapter 8










































Exhaustive Testing









there4





D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0


Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1






D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1




D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1





bull 0 10 0 01 0 1

0 10 0 11 1 0













xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1




rArr G(x) = =



xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +




P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z











where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ






An Example of LFSR


D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23































LFSR SR

CUT

MISR





CUT

MISR SR






ndash Test-per-scan


SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn






BILBO register



z1 z2 zn

B1 B2







POs
















D Q D Q D Q










Segmentation






n1

n2

C1

C2





n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation










An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4







⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4






f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0






f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)











abcdefg


f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV







LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5





y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4










PIs

+

BSCs





Residue Polynomials


Ri(x) = xi mod f(x)


R0 R1 R2 Rk-1 Rk Ri




+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5





hellipRpk


210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G



exhaustively tested




x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5















LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network




0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed





















Tree Growing







XOR-Tree Generation



problem










Rj


R0 R1 R2 Rk-1

i

Ri

jN






backbone

branches

isolated oplus





R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7








C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31












methods



Notes

Chapter 9




Board Level Testing

Sn m

Sn m

n

mMUXm



R1

R2









1149111491a






TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic



Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control











bull IN-gtQA






Application Logic 2


TDI

TDO

Application Logic 1











Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out




Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO







Test Bus (22)





Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS









Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK


TDI

optional

optional



TAPC



SelectEnable

OutputBuffer




TAPC













shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1


Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1


Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR


Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers


itself















BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2





















Chapter 10

Memory Testing










Fault Models (23)





Fault Models (33)




















hArr







hArr hArr hArr








hArrhArr

hArrhArr








hArr hArr

hArr

hArr

hArr






hArrhArrhArr






NPSF






ANPSF


b 1 rArr 0

n n nn b nn n n




PNPSF


n n nn b nn n n




SNPSF


n n nn b nn n n















Dynamic Faults


































Chapter 11

SOC Testing



















SOC Components


components



SOC Design Flow



by laws























tests




















or TAM











TAM























MUX

control











difficult



more complex








( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i




can be reduced as


pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛





can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max








































core user











SOCET PrincetonNEC






Boundary Scan (12)





Boundary Scan (22)






























Test Bus




TestRail








test time





automation











pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛






⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus















pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max





FF

FF

core

FF

FF

core




The SCDP Algorithm



















Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass








simulation tools


Chapter 12



























Before integration



After integration












wrapper















(between WSI-WSO)






WPI-WPO





















wrapperbull Signals
























Shared Updated SE

Dedicated SEs


























bandwidths



















Notes











patterns










IEEE P14506 (CTL) (12)



P1500













CTL Key Words























































conversion












for core user






Unwrappedrsquo







SOC Test Creation









ndash Test re-use

























Overview of Example






Bare Core



STIL Test Patterns



Wrapped Core

WIP







WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP




WIP




WIP



Wrapper Design (12)






Wrapper Design (22)























possible

3

2

1







Bypasses (12)







Bypasses (22)










minimized






(Hard)




(Easy)





(Easy)









Smi)(max

1











Ref [Grahamrsquo69]















Example Core (12)






+ 1 scan enable sc





Example Core (22)









Wrapper Result (24)





Wrapper Result (34)





Wrapper Result (44)





















inspection

















Interconnect ATPG

Normal ATPG







Interconnect Faults



Interconnect ATPG



algorithm
























Architecture Model












































Test Expansion




















Terminology (12)







Terminology (22)





Simple Example (12)




Simple Example (22)






Example SOC






Test Assembly




















Examples of Cores











httpwwwvsiacom







Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]











Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM


ASIC 1

UDL

DSP CPU ASIC 2IP 2

Chapter 1

Introduction




Design the circuit

Verify the design





Design Errors

TestPlans






verifytest

testtest










Why Testing


Vdd

10

00

0

0




How to Do Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

GoodBad






some time





Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632




Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R




responses Rrsquo



Circuit Modeling



algorithms



Fault Modeling















EA

B

C

D F

G




D s-a-1D s-a-0

14 faults











Vdd

10

00

0

0


xf s-a-1





CA

B




1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts




Testing





EA

B

C

D F

G

1

10

0

01

1






B

C

D F

G

1

100

0

01

10

x






CA

B 1

10






A

B

C

D s-a-0

E

F

x















more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No





A

B

C

D s-a-1

E

F

x





D

clk

Q


PIs POs





100

of test patterns






Testing Costs













Chapter 2

Fault Models



Faults and Errors






Failures










































A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

















stuck-on

0






IDDQ fault





stuck-open

0 Z





patterns

stuck-open

10 0100


fault-free response

fault response




X X

R






slow

critical path






XY

XY

the clock interval

propagation delay










DecoderLi

Lj





S1

S3S2

I1O1 I2O2





S1

S3S2

IO IO



Memory Faults (12)






Memory Faults (22)





Coupling Faults






0 0 00 d b0 a 0






x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3




Sensitization





Detectability









1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing























2n+2

n+1 n+1

equivalence

n+2cup

[Proof]




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0






Tα

Tβ

Tβ supeTα











2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0









Checkpoints (13)





Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0





a

b

c

d

e


Chapter 3

Fault Simulation

























endend









D-FF

abc

d

e

f

Compiled-Code


Q D






end




c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1


0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1


















f1 s-a-0

f2 s-a-0

0

1

1
























0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0













Lc


[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type




c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1



g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0


c 1 b0 c0

d 1 b0 d0










ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0








PPSFP







p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1





Sensitive Inputs


ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1

















a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region






b

f

c

d e

g

h

i

1

0

11

1

0

1critical line



stem

branch

branch




b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region








Chapter 4






Impractical



TG from Truth Table


ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1







ab

c

f

α s-a-0




)()()( 1f0fdx

xdfii

i

oplus=







x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or




c

f

cb0cb1f0fda







ab

c

f

h = ab

caacac1f0fdh












vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations





c

f

10 = D

0

1

1

0

s-a-0D

h








endend







ab

c

f



1

1

0

s-a-0D





end








Implication




Decision Trees








Backtracking





0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc






decision problem










s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2








F S

G5 G6




s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D














q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1








return SUCCESSend


end












s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D




s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1











larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x


11

1 rarr

a




x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa





x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr




Before After

x

x1D


x

1


D rarr x


D rarr D rarr

D rarrx D

DD rarr

D


aD rarrx D

D0 rarr



Unique D-drive

Before


After

D rarr


D



x-path






DD

x

x x

x

x

00

11








D-Algorithm



only a single path




then return FAILURE


then return FAILURE













end


end D-alg




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1














abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01










abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1







f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D





D-frontieri k m

k m n

m nF

F S

i

n k

n m
















abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1


u1

u1

u1





bullV






i = Dd = 0


bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV



n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D





D-frontier

i k m

k m n

S

i

n

No backtracking










Inversion Parity



















end




fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x


fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101










Objective( )being


end




end




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D





(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n




(k 1) e = 0 e = 1j =0



j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D





a0b1

c1d1

e0F f1

S

1












ab f








ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05





C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656

No backtracking










Head Lines



head linesbound

DE

ABC

F

G




head linesbound

DE

ABC

F

G









FAN vs PODEM

head linesbound

DE

ABC

F

G


A1B0

F C0F

1

1

G0F

1

PODEM FAN







thenbegin


j for vk









value xadd (j c) to



value x








Stem_objectives






end Mbacktrace




0

1

0

1




AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )


A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C



empty

empty







end








End FAN( )



ATPG (12)






ATPG (22)






Sequential TG




1989]






initial states










I

OY1

Y2y1

y2 s-a-1

FF2

FF1





OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG










D D



























=

=FC

Chapter 5





































Initialization








ab z





ab

abab

ab

ab

z

z

z

z

z

z









D

C

Q

R



Observability (12)

P

QR

N


D

C

Q






ab

abab

ab

ab

z

z

z

z

z

z





zz1z2

zn





1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)





Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0






Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0














achieved






FC100

with DFT

of T

without DFT








DFT Techniques









C1 C2 C1 C2

jumper

CPOP





01-Injection

CP1

C1

CP0

C2

01-injection

C1C2


C1C2

CP1

OP OP

OP




NT

C1

CP C2

01-injection

MUX

0

1

OP




01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n





01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs




PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT




























PR

CLR

Vcc

Vcc

Q

Q





PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1




Vcc

t

VZ

Vcc

Z





C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s




during test

OSCC

OP

AB

01-I




into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2




CPdata inhibit

CPtest data

C


DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2





C1 C2

AB

C

D

E

F G

m ns

p

q





m

s

n

q

p



Logic Redundancy







paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO





DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC


SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK




Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR



















C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout






C

Rrsquo

Rs

PI PO

Sin Sout


shadow register





rate of the system








clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO











D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B






C

B

A

B

Normal mode A = 0

Test mode C = 0




Sout

Sin

CA

B





Sout

SinC2








Notes

Chapter 6










C1 C2 C3


One session




ndash C1 100 C2 200 C3 300


C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions









scan chains












partial scan

full scan

sequential TG

combinational TG











3

1 2 4 5 6







distance = 4

distance = 3












(not testable)



















end




= 695







combinational TG


BALLAST

(scanned FFrsquos)




Sout

Sin

HOLD(for test)









Circuit Model (14)









and HOLD







a scan register



Circuit Model (44)

R3












A B-structure





















construct SB















cycles





Sin


R3 R6





Mutiple ScanChains


Area Overhead


Extal Pins

Extral ClockControl


same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7




Challenges from ORA






























sum=i

irR1C )(




counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0


x1x2x3


Output Reponses







⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(




minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0






122)|(

1

minusminus

=minus

m

mr

TC1CrmMP




NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

















Signature Analysis










)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2








( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984





MISRs










Notes

Chapter 8










































Exhaustive Testing









there4





D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0


Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1






D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1




D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1





bull 0 10 0 01 0 1

0 10 0 11 1 0













xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1




rArr G(x) = =



xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +




P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z











where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ






An Example of LFSR


D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23































LFSR SR

CUT

MISR





CUT

MISR SR






ndash Test-per-scan


SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn






BILBO register



z1 z2 zn

B1 B2







POs
















D Q D Q D Q










Segmentation






n1

n2

C1

C2





n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation










An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4







⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4






f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0






f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)











abcdefg


f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV







LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5





y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4










PIs

+

BSCs





Residue Polynomials


Ri(x) = xi mod f(x)


R0 R1 R2 Rk-1 Rk Ri




+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5





hellipRpk


210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G



exhaustively tested




x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5















LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network




0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed





















Tree Growing







XOR-Tree Generation



problem










Rj


R0 R1 R2 Rk-1

i

Ri

jN






backbone

branches

isolated oplus





R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7








C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31












methods



Notes

Chapter 9




Board Level Testing

Sn m

Sn m

n

mMUXm



R1

R2









1149111491a






TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic



Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control











bull IN-gtQA






Application Logic 2


TDI

TDO

Application Logic 1











Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out




Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO







Test Bus (22)





Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS









Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK


TDI

optional

optional



TAPC



SelectEnable

OutputBuffer




TAPC













shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1


Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1


Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR


Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers


itself















BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2





















Chapter 10

Memory Testing










Fault Models (23)





Fault Models (33)




















hArr







hArr hArr hArr








hArrhArr

hArrhArr








hArr hArr

hArr

hArr

hArr






hArrhArrhArr






NPSF






ANPSF


b 1 rArr 0

n n nn b nn n n




PNPSF


n n nn b nn n n




SNPSF


n n nn b nn n n















Dynamic Faults


































Chapter 11

SOC Testing



















SOC Components


components



SOC Design Flow



by laws























tests




















or TAM











TAM























MUX

control











difficult



more complex








( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i




can be reduced as


pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛





can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max








































core user











SOCET PrincetonNEC






Boundary Scan (12)





Boundary Scan (22)






























Test Bus




TestRail








test time





automation











pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛






⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus















pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max





FF

FF

core

FF

FF

core




The SCDP Algorithm



















Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass








simulation tools


Chapter 12



























Before integration



After integration












wrapper















(between WSI-WSO)






WPI-WPO





















wrapperbull Signals
























Shared Updated SE

Dedicated SEs


























bandwidths



















Notes











patterns










IEEE P14506 (CTL) (12)



P1500













CTL Key Words























































conversion












for core user






Unwrappedrsquo







SOC Test Creation









ndash Test re-use

























Overview of Example






Bare Core



STIL Test Patterns



Wrapped Core

WIP







WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP




WIP




WIP



Wrapper Design (12)






Wrapper Design (22)























possible

3

2

1







Bypasses (12)







Bypasses (22)










minimized






(Hard)




(Easy)





(Easy)









Smi)(max

1











Ref [Grahamrsquo69]















Example Core (12)






+ 1 scan enable sc





Example Core (22)









Wrapper Result (24)





Wrapper Result (34)





Wrapper Result (44)





















inspection

















Interconnect ATPG

Normal ATPG







Interconnect Faults



Interconnect ATPG



algorithm
























Architecture Model












































Test Expansion




















Terminology (12)







Terminology (22)





Simple Example (12)




Simple Example (22)






Example SOC






Test Assembly




















Examples of Cores











httpwwwvsiacom







Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]











Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM


ASIC 1

UDL

DSP CPU ASIC 2IP 2




Design the circuit

Verify the design





Design Errors

TestPlans






verifytest

testtest










Why Testing


Vdd

10

00

0

0




How to Do Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

GoodBad






some time





Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632




Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R




responses Rrsquo



Circuit Modeling



algorithms



Fault Modeling















EA

B

C

D F

G




D s-a-1D s-a-0

14 faults











Vdd

10

00

0

0


xf s-a-1





CA

B




1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts




Testing





EA

B

C

D F

G

1

10

0

01

1






B

C

D F

G

1

100

0

01

10

x






CA

B 1

10






A

B

C

D s-a-0

E

F

x















more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No





A

B

C

D s-a-1

E

F

x





D

clk

Q


PIs POs





100

of test patterns






Testing Costs













Chapter 2

Fault Models



Faults and Errors






Failures










































A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

















stuck-on

0






IDDQ fault





stuck-open

0 Z





patterns

stuck-open

10 0100


fault-free response

fault response




X X

R






slow

critical path






XY

XY

the clock interval

propagation delay










DecoderLi

Lj





S1

S3S2

I1O1 I2O2





S1

S3S2

IO IO



Memory Faults (12)






Memory Faults (22)





Coupling Faults






0 0 00 d b0 a 0






x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3




Sensitization





Detectability









1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing























2n+2

n+1 n+1

equivalence

n+2cup

[Proof]




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0






Tα

Tβ

Tβ supeTα











2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0









Checkpoints (13)





Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0





a

b

c

d

e


Chapter 3

Fault Simulation

























endend









D-FF

abc

d

e

f

Compiled-Code


Q D






end




c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1


0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1


















f1 s-a-0

f2 s-a-0

0

1

1
























0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0













Lc


[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type




c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1



g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0


c 1 b0 c0

d 1 b0 d0










ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0








PPSFP







p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1





Sensitive Inputs


ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1

















a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region






b

f

c

d e

g

h

i

1

0

11

1

0

1critical line



stem

branch

branch




b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region








Chapter 4






Impractical



TG from Truth Table


ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1







ab

c

f

α s-a-0




)()()( 1f0fdx

xdfii

i

oplus=







x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or




c

f

cb0cb1f0fda







ab

c

f

h = ab

caacac1f0fdh












vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations





c

f

10 = D

0

1

1

0

s-a-0D

h








endend







ab

c

f



1

1

0

s-a-0D





end








Implication




Decision Trees








Backtracking





0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc






decision problem










s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2








F S

G5 G6




s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D














q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1








return SUCCESSend


end












s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D




s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1











larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x


11

1 rarr

a




x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa





x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr




Before After

x

x1D


x

1


D rarr x


D rarr D rarr

D rarrx D

DD rarr

D


aD rarrx D

D0 rarr



Unique D-drive

Before


After

D rarr


D



x-path






DD

x

x x

x

x

00

11








D-Algorithm



only a single path




then return FAILURE


then return FAILURE













end


end D-alg




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1














abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01










abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1







f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D





D-frontieri k m

k m n

m nF

F S

i

n k

n m
















abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1


u1

u1

u1





bullV






i = Dd = 0


bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV



n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D





D-frontier

i k m

k m n

S

i

n

No backtracking










Inversion Parity



















end




fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x


fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101










Objective( )being


end




end




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D





(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n




(k 1) e = 0 e = 1j =0



j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D





a0b1

c1d1

e0F f1

S

1












ab f








ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05





C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656

No backtracking










Head Lines



head linesbound

DE

ABC

F

G




head linesbound

DE

ABC

F

G









FAN vs PODEM

head linesbound

DE

ABC

F

G


A1B0

F C0F

1

1

G0F

1

PODEM FAN







thenbegin


j for vk









value xadd (j c) to



value x








Stem_objectives






end Mbacktrace




0

1

0

1




AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )


A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C



empty

empty







end








End FAN( )



ATPG (12)






ATPG (22)






Sequential TG




1989]






initial states










I

OY1

Y2y1

y2 s-a-1

FF2

FF1





OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG










D D



























=

=FC

Chapter 5





































Initialization








ab z





ab

abab

ab

ab

z

z

z

z

z

z









D

C

Q

R



Observability (12)

P

QR

N


D

C

Q






ab

abab

ab

ab

z

z

z

z

z

z





zz1z2

zn





1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)





Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0






Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0














achieved






FC100

with DFT

of T

without DFT








DFT Techniques









C1 C2 C1 C2

jumper

CPOP





01-Injection

CP1

C1

CP0

C2

01-injection

C1C2


C1C2

CP1

OP OP

OP




NT

C1

CP C2

01-injection

MUX

0

1

OP




01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n





01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs




PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT




























PR

CLR

Vcc

Vcc

Q

Q





PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1




Vcc

t

VZ

Vcc

Z





C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s




during test

OSCC

OP

AB

01-I




into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2




CPdata inhibit

CPtest data

C


DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2





C1 C2

AB

C

D

E

F G

m ns

p

q





m

s

n

q

p



Logic Redundancy







paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO





DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC


SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK




Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR



















C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout






C

Rrsquo

Rs

PI PO

Sin Sout


shadow register





rate of the system








clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO











D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B






C

B

A

B

Normal mode A = 0

Test mode C = 0




Sout

Sin

CA

B





Sout

SinC2








Notes

Chapter 6










C1 C2 C3


One session




ndash C1 100 C2 200 C3 300


C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions









scan chains












partial scan

full scan

sequential TG

combinational TG











3

1 2 4 5 6







distance = 4

distance = 3












(not testable)



















end




= 695







combinational TG


BALLAST

(scanned FFrsquos)




Sout

Sin

HOLD(for test)









Circuit Model (14)









and HOLD







a scan register



Circuit Model (44)

R3












A B-structure





















construct SB















cycles





Sin


R3 R6





Mutiple ScanChains


Area Overhead


Extal Pins

Extral ClockControl


same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7




Challenges from ORA






























sum=i

irR1C )(




counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0


x1x2x3


Output Reponses







⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(




minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0






122)|(

1

minusminus

=minus

m

mr

TC1CrmMP




NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

















Signature Analysis










)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2








( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984





MISRs










Notes

Chapter 8










































Exhaustive Testing









there4





D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0


Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1






D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1




D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1





bull 0 10 0 01 0 1

0 10 0 11 1 0













xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1




rArr G(x) = =



xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +




P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z











where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ






An Example of LFSR


D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23































LFSR SR

CUT

MISR





CUT

MISR SR






ndash Test-per-scan


SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn






BILBO register



z1 z2 zn

B1 B2







POs
















D Q D Q D Q










Segmentation






n1

n2

C1

C2





n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation










An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4







⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4






f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0






f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)











abcdefg


f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV







LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5





y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4










PIs

+

BSCs





Residue Polynomials


Ri(x) = xi mod f(x)


R0 R1 R2 Rk-1 Rk Ri




+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5





hellipRpk


210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G



exhaustively tested




x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5















LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network




0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed





















Tree Growing







XOR-Tree Generation



problem










Rj


R0 R1 R2 Rk-1

i

Ri

jN






backbone

branches

isolated oplus





R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7








C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31












methods



Notes

Chapter 9




Board Level Testing

Sn m

Sn m

n

mMUXm



R1

R2









1149111491a






TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic



Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control











bull IN-gtQA






Application Logic 2


TDI

TDO

Application Logic 1











Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out




Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO







Test Bus (22)





Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS









Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK


TDI

optional

optional



TAPC



SelectEnable

OutputBuffer




TAPC













shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1


Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1


Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR


Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers


itself















BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2





















Chapter 10

Memory Testing










Fault Models (23)





Fault Models (33)




















hArr







hArr hArr hArr








hArrhArr

hArrhArr








hArr hArr

hArr

hArr

hArr






hArrhArrhArr






NPSF






ANPSF


b 1 rArr 0

n n nn b nn n n




PNPSF


n n nn b nn n n




SNPSF


n n nn b nn n n















Dynamic Faults


































Chapter 11

SOC Testing



















SOC Components


components



SOC Design Flow



by laws























tests




















or TAM











TAM























MUX

control











difficult



more complex








( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i




can be reduced as


pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛





can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max








































core user











SOCET PrincetonNEC






Boundary Scan (12)





Boundary Scan (22)






























Test Bus




TestRail








test time





automation











pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛






⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus















pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max





FF

FF

core

FF

FF

core




The SCDP Algorithm



















Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass








simulation tools


Chapter 12



























Before integration



After integration












wrapper















(between WSI-WSO)






WPI-WPO





















wrapperbull Signals
























Shared Updated SE

Dedicated SEs


























bandwidths



















Notes











patterns










IEEE P14506 (CTL) (12)



P1500













CTL Key Words























































conversion












for core user






Unwrappedrsquo







SOC Test Creation









ndash Test re-use

























Overview of Example






Bare Core



STIL Test Patterns



Wrapped Core

WIP







WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP




WIP




WIP



Wrapper Design (12)






Wrapper Design (22)























possible

3

2

1







Bypasses (12)







Bypasses (22)










minimized






(Hard)




(Easy)





(Easy)









Smi)(max

1











Ref [Grahamrsquo69]















Example Core (12)






+ 1 scan enable sc





Example Core (22)









Wrapper Result (24)





Wrapper Result (34)





Wrapper Result (44)





















inspection

















Interconnect ATPG

Normal ATPG







Interconnect Faults



Interconnect ATPG



algorithm
























Architecture Model












































Test Expansion




















Terminology (12)







Terminology (22)





Simple Example (12)




Simple Example (22)






Example SOC






Test Assembly




















Examples of Cores











httpwwwvsiacom







Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]











Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM


ASIC 1

UDL

DSP CPU ASIC 2IP 2






verifytest

testtest










Why Testing


Vdd

10

00

0

0




How to Do Testing

Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R

GoodBad






some time





Pf = 1-(1-p)N

If p = 10-6 and N= 106

Pf = 632




Circuit Under Test

(CUT)


(TPG)


test patterns T

outputresponses R




responses Rrsquo



Circuit Modeling



algorithms



Fault Modeling















EA

B

C

D F

G




D s-a-1D s-a-0

14 faults











Vdd

10

00

0

0


xf s-a-1





CA

B




1667333350006667

10000



Testing QualityIC

FabricationYield(Y)

Rejected Parts




Testing





EA

B

C

D F

G

1

10

0

01

1






B

C

D F

G

1

100

0

01

10

x






CA

B 1

10






A

B

C

D s-a-0

E

F

x















more fulats

select a fault

test generation

fault simulation

fault dropping

exit

Yes

No





A

B

C

D s-a-1

E

F

x





D

clk

Q


PIs POs





100

of test patterns






Testing Costs













Chapter 2

Fault Models



Faults and Errors






Failures










































A

B

f

g

A

B

f

g

A

B

f

g

A

B

f

g



PLA Faults

















stuck-on

0






IDDQ fault





stuck-open

0 Z





patterns

stuck-open

10 0100


fault-free response

fault response




X X

R






slow

critical path






XY

XY

the clock interval

propagation delay










DecoderLi

Lj





S1

S3S2

I1O1 I2O2





S1

S3S2

IO IO



Memory Faults (12)






Memory Faults (22)





Coupling Faults






0 0 00 d b0 a 0






x2

x3

z1

z2

f s-a-1 z1 = x1 x2

z2 = x2 x3

z1f = x1

z2 f= x2 x3




Sensitization





Detectability









1

s-a-0G1

1

1

00

0

10a

b

c

z



Fault Collapsing























2n+2

n+1 n+1

equivalence

n+2cup

[Proof]




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0






Tα

Tβ

Tβ supeTα











2n+2

n+1 n+1

equivalencen+1

cup

[Proof]

n 1dominance




s-a-0

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1 s-a-0

s-a-0

s-a-0

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-0









Checkpoints (13)





Checkpoints (23)

a

b

c

d

e

s-a-1s-a-1

s-a-1

s-a-1s-a-1

s-a-1

s-a-1

s-a-1s-a-0

s-a-0

s-a-0s-a-0

s-a-0

s-a-0s-a-0

s-a-0





a

b

c

d

e


Chapter 3

Fault Simulation

























endend









D-FF

abc

d

e

f

Compiled-Code


Q D






end




c

bd

e

f

g2

2

2

41

1 rarr0

0 rarr1

1 rarr0

0 rarr1

1 rarr0 rarr1


0 c = 0 d e

1

2 d = 1 e =0 f g

3

4 g = 0

5

6 f = 1 g

7

8 g = 1


















f1 s-a-0

f2 s-a-0

0

1

1
























0 0 0 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 0 1 1 1 0 0

0 1 0 0

1 0 0 1

1 1 1 1a

b

f

c

de

g

h

is-a-1

s-a-0

s-a-0













Lc


[La cap Lb] cup c1

[La cap Lb] cup c1

[La cup Lb] cup c0

[La cup Lb] cup c1

[La cap Lb] cup c0

[La cap Lb] cup c0

[La cap Lb] cup c0

La cup c0

La cup c1

(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)

1 - 0 (10)

NOT

OR

AND

Gate Type




c 1 b0 c0

d 1 b0 d0

1 a0

1 b0

e 1 a0 b0 c0 e0

f 0 b0 d0 f1



g



ab

g

1 a0

1 b1

e 1 a0 b0 c0 e0

f 0 b0 d0 f1

1 a0 c0 e0 g0


c 1 b0 c0

d 1 b0 d0










ab c

d g

1

1

e

f

1

11 1

1 0

0 1 0 1 1 1

b0 d0 f1

01 1

00

a0

01

1

b0

00

0

c0

01

1

d0

1

00

e0

01

1

f1

10

0

g0

1

a001 0

10 0

10 0

11 0

b0 c0 e0


1

0








PPSFP







p1 and p0

0 1 0 1 1 0 1 0

1 0 0 1

1 1 0 1

0 1 0 1

1 0 0 0

1 1 1 1a

b

f

c

de

g

h

i

s-a-0

p3 p2 p1 p0

0 0 0 00 0 0 0

0 1 0 1





Sensitive Inputs


ab

1rarr0

1

c

a is sensitive

ab 0

0 c

a is not sensitive

1rarr0 0 rarr1

















a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region

sensitive input




a

b

f

c

d e

g

h

i

1

0

11

1

0

1fanout-free region






b

f

c

d e

g

h

i

1

0

11

1

0

1critical line



stem

branch

branch




b

f

c

d

g

h

i

1

1

1

1

1

1fanout-free region








Chapter 4






Impractical



TG from Truth Table


ab

c

f

α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1







ab

c

f

α s-a-0




)()()( 1f0fdx

xdfii

i

oplus=







x1xixn

fcircuit0 rarr 1

0 rarr1

1rarr0or x1

xixn

fcircuit1rarr 0

1 rarr0

0 rarr1or




c

f

cb0cb1f0fda







ab

c

f

h = ab

caacac1f0fdh












vvf symbol

00 0

11 1

10 D

01 D

AND 0 1 D0 0

DD0x

1DDx

00000

D x0 0

D0Dx

10xxx

DDx x

OR 0 1 D1 D

1D1x

1111

01DDx

D x0 D

11Dx

1x1xx

DDx x

5-valued operations





c

f

10 = D

0

1

1

0

s-a-0D

h








endend







ab

c

f



1

1

0

s-a-0D





end








Implication




Decision Trees








Backtracking





0xxx

ad

d = 0

F F

a = 0 a = 1b = 0

a = 1b = 1c = 0

bc






decision problem










s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2








F S

G5 G6




s-a-1

ab

cd

efh

k

l

mno

p

q

r s




bull FA rArr h = D














q = 1

F

l = 1 l = 0 k = 1

r = 1

S

m = 1

S

n = 1








return SUCCESSend


end












s-a-1

abc

d

e

G2

G1

G3

G5

G4

G6

f1

f2

D




s-a-1

ab

cd

efh

k

l

mno

p

q

r s

1

1











larr 1x

x

larr 0x

1

larr 0x

xlarr 1

x

x

Before

J-frontier = hellip

After1larr 1

larr 1

0larr 0

1

0x


11

1 rarr

a




x

Before0 rarr x

1

x

0 rarr

x

0a

1 rarr

1 rarr

x

0a

D

1 rarr

xa

D

0 rarr

xa





x

After0

10

x

0

1

1

larr 0

0

D

1 aD

0 a

J-frontier = hellip

J-frontier = hellip

D-frontier = hellip

D-frontier = hellip

0 rarr

1 rarr

D rarr

0 rarr




Before After

x

x1D


x

1


D rarr x


D rarr D rarr

D rarrx D

DD rarr

D


aD rarrx D

D0 rarr



Unique D-drive

Before


After

D rarr


D



x-path






DD

x

x x

x

x

00

11








D-Algorithm



only a single path




then return FAILURE


then return FAILURE













end


end D-alg




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1














abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01










abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

01

DContradiction


D

1

11

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1







f = 1

m =D Contradiction




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

01

D

Contradiction


D

1

1








abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1D

01

D

10 1

10

D

1

D





D-frontieri k m

k m n

m nF

F S

i

n k

n m
















abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1


u1

u1

u1





bullV






i = Dd = 0


bullV





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

1

0

D

1u

u1




bullV



n = Df = u0f = 1f = 0

e = u0

e = 1e = 0k = D

m = D



0

1D


abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011 D

1

u1

u1

1

0

D

D0

1D





D-frontier

i k m

k m n

S

i

n

No backtracking










Inversion Parity



















end




fd

e

ca

bx

x

x

xxx

fd

e

ca

bx

1

x

10x


fd

e

ca

bx

1

x1

0x

fd

e

ca

b1

1

0

101










Objective( )being


end




end




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

D

D





(a 0) a = 0 h = 1 g

(b 1) b = 1 g(c 1) c = 1 g = D i k m

(d 1) d = 1 d = 0

i = D k m n




(k 1) e = 0 e = 1j =0



j = 1k = D m n




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

00

1

D

D

11





abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

1D




(l 1) f = 1 f = 0l = 1

m = Dn = D




abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

f

011

11 0

11

0

D

D

11 0

D

D

D





a0b1

c1d1

e0F f1

S

1












ab f








ab c

CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05





C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656




C1(G1) = 025

C1(G1) = 0656

No backtracking










Head Lines



head linesbound

DE

ABC

F

G




head linesbound

DE

ABC

F

G









FAN vs PODEM

head linesbound

DE

ABC

F

G


A1B0

F C0F

1

1

G0F

1

PODEM FAN







thenbegin


j for vk









value xadd (j c) to



value x








Stem_objectives






end Mbacktrace




0

1

0

1




AB

A1

A2E

E1

E2

G

H

I

JC

1

0




(I 1 ) (J 0 ) (I 1 )

(J 0 ) (G 0 ) (J 0 )

(G 0 ) (H 1 ) (G 0 )

(H 1 ) (A1 1 ) (E1 1) (H 1 )


A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C

A C



empty

empty







end








End FAN( )



ATPG (12)






ATPG (22)






Sequential TG




1989]






initial states










I

OY1

Y2y1

y2 s-a-1

FF2

FF1





OY1

Y2

I

y1

y2 s-a-1

time-frame 00

1

D

I

OY1

Y2

y1

y2 s-a-1

time-frame 1

1D

I

y1

y2 s-a-1

time-frame -1

0

0

Y1

Y2



9-V Sequential TG










D D



























=

=FC

Chapter 5





































Initialization








ab z





ab

abab

ab

ab

z

z

z

z

z

z









D

C

Q

R



Observability (12)

P

QR

N


D

C

Q






ab

abab

ab

ab

z

z

z

z

z

z





zz1z2

zn





1

23

4

5

6

PI3

PI2

PI1

PO

Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)





Note ( C0 C1 )

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54)

Note ( C0 C1 ) O

(11)

(11)

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11)

(11)

(11)

(22)

(22)

(23)

(35)

(27)

(54) 0






Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11)

(11)

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0

Note ( C0 C1 ) O

(11) 5

(11) 5

1

23

4

5

6

PI3

PI2

PI1

PO

(11) 5

(11) 5

(11) 9

(11) 9

(11) 9

(22) 8

(22) 8

(23) 3

(35) 5

(27) 3

(54) 0














achieved






FC100

with DFT

of T

without DFT








DFT Techniques









C1 C2 C1 C2

jumper

CPOP





01-Injection

CP1

C1

CP0

C2

01-injection

C1C2


C1C2

CP1

OP OP

OP




NT

C1

CP C2

01-injection

MUX

0

1

OP




01

2n-11 2 n

X1 X2 Xn

Z

CP1CP2

CPN

DEMUX

N = 2n





01

2n-11 2 n

X1 X2 Xn

Z

OP1OP2

OPN

MUX

N = 2n

Multiplexing OPs




PIs DEMUX

normal functional

inputsn

n

n nCPs

0

1

NT




OPs

DEMUX

normal functional

outputs

n

n

nPOs

0

1

NT




























PR

CLR

Vcc

Vcc

Q

Q





PR

CLR

Q

Q

C1

Clear

PR

CLR

Q

Q

C1




Vcc

t

VZ

Vcc

Z





C1C2

one-shotjumper

CPOP

jumper

OP CP





C1

C2

one-shotA

B

E (OP)

C

D

MUX

0

1

01-I

s




during test

OSCC

OP

AB

01-I




into smaller units

DIN

CK

DOUTR1

DIN

CK

DOUTR2C

X1 X2

Y1 Y2




CPdata inhibit

CPtest data

C


DIN

CK

DOUT

R1

X1

Y1

CPdata inhibit

CPtest data

OP

DIN

CK

DOUT

R2

X2

Y2





C1 C2

AB

C

D

E

F G

m ns

p

q





m

s

n

q

p



Logic Redundancy







paths



Scan SystemPO

C

R

PI

C

Rrsquo

PI

Sin

Sout

PO





DSi

N TCK

Q So

N T Q So

0 D1 Si

D QSSC

Symbol for a SSC


SSC



Simultaneous CO

C1 C2

MUX

0

1

T

D Q

CPOP

SiN T CK




Sin

CK

N T

D1

Q

Q1 D2

Q

Q2 Dn

Q

Qn

DSi

N TCK

SoutSSC SSC

R

Symbol for a SR



















C

R

PI PO

CK

C

Rs

PI PO

CKNT Sin

Sout






C

Rrsquo

Rs

PI PO

Sin Sout


shadow register





rate of the system








clocks and controls

Y-address(decoder)

X-address(decoder)

Sout

SinSCK

PI PO











D

Sin

Q2 Sout(L2)

Q1 (L1)

C

A

B






C

B

A

B

Normal mode A = 0

Test mode C = 0




Sout

Sin

CA

B





Sout

SinC2








Notes

Chapter 6










C1 C2 C3


One session




ndash C1 100 C2 200 C3 300


C1 C2 C3

Test time= 60 100 +

40 100 +20 100

= 12000 (cycles)

Three sessions









scan chains












partial scan

full scan

sequential TG

combinational TG











3

1 2 4 5 6







distance = 4

distance = 3












(not testable)



















end




= 695







combinational TG


BALLAST

(scanned FFrsquos)




Sout

Sin

HOLD(for test)









Circuit Model (14)









and HOLD







a scan register



Circuit Model (44)

R3












A B-structure





















construct SB















cycles





Sin


R3 R6





Mutiple ScanChains


Area Overhead


Extal Pins

Extral ClockControl


same

same

same

same

same

same

darr or uarr

darr

darr

darr

same or uarr

same

uarr

same

darr

same

same

darr

darr

same

Full Scan

Chapter 7




Challenges from ORA






























sum=i

irR1C )(




counter

s-a-0 fault f2

s-a-1 fault f1

111100001100110010101010

00000000 = R211000000 = R110000000 = R0


x1x2x3


Output Reponses







⎥⎦

⎤⎢⎣

⎡rm

1rm

minus⎥⎦

⎤⎢⎣

⎡

)1

1rmM

2CP m

m

r1C minus

minus=(




minus

=+

oplus1m

1i1ii rr

NetworkT D Q

counter

00000000 = R211000000 = R110000000 = R0






122)|(

1

minusminus

=minus

m

mr

TC1CrmMP




NetworkT

00000000 = R211000000 = R110000000 = R0 D Q

















Signature Analysis










)()()( )(or )()()(

)()( xRxPxQxG

xPxRxQ

xPxG

+=+=

G(x) Q(x)



Example of SISRs

R(x) = x2+x4 Q(x) =1+x2








( ) 21212P n

m

nm

SA nmM minusminus

congminus

minus=|



ndash Eg If n = 16 then(1-2-16) 100 = 999984





MISRs










Notes

Chapter 8










































Exhaustive Testing









there4





D Q D Q

S0 1 0S1 0 1S2 (=S0) 1 0


Z D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7 (=S0) 0 1 1






D Q D Q ZD Q D Q

C1 C2 Cn-1 Cn= 1C0

= 1




D Q

Cn-1Cn= 1

D Q

Cn-2

D Q

C1

D Q Z

C0= 1





bull 0 10 0 01 0 1

0 10 0 11 1 0













xa m

mmsum

infin

=0

aC im

n

ii minus

=sum

1




rArr G(x) = =



xa m

mmsum

infin

=0sum suminfin

= =minus⎟⎠

⎞⎜⎝

⎛

0 1m

mn

iimi xaC

( )sum

sum

=

minus

minus

minus

minus=

+

++

n

i

i

i

i

i

in

ii

xC

xaxaxC

1

1

11

1




bull Let P(x) = 1 +




P(x) = x3 + x + 1

sum=

n

i

i

i xC1

D Q D Q D Q Z











where

( ) ( )n

nn 12

2

minus=φλ

( ) prod ⎟⎟⎠

⎞⎜⎜⎝

⎛minus=

np pnn

|

11φ

n1 12 14 28 1616 204832 67108864

( )n2λ






An Example of LFSR


D Q D Q D Q Z

S0 0 1 1S1 1 0 1S2 0 1 0S3 0 0 1S4 1 0 0S5 1 1 0S6 1 1 1S7(=S0) 0 1 1



Exhaustive Testing

D Q D Q D Q0 0 1

0 0 0

1 0 0

scan chain 3

CUT

test cycles 3+23































LFSR SR

CUT

MISR





CUT

MISR SR






ndash Test-per-scan


SR1 SR2 SRn

MISR

CUT1 CUT2 CUTn






BILBO register



z1 z2 zn

B1 B2







POs
















D Q D Q D Q










Segmentation






n1

n2

C1

C2





n2

C1

C2

n1

n2

C1

C2

n1

n2

C1

C2

2n1 test patterns

2n2 test patterns

1 test pattern

1

1

0



Cone Segmentation










An (4 2)-CUT

y1 y2 y3 y4

x1 x2 x3 x4







⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

101011110000

Tn = 3

k = 2|T| = 4






f(x y)

g(x y)

x

y

z

1 1 0 0

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0






f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

f(x y)

g(x y)

x

y

z

1 1 0 0

1 0 1 0

0 1 1 0h(x z)











abcdefg


f4(c d e)

f5(e f)

C

f

f

f

f

f

gfedcba

D

5

4

3

2

1

01100000011100001100110001100010011

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 1




f

f

f

f

f

gfedbca

Dg

5

4

3

2

1

01100000011010001100110001100010101

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 2

I II III IV

f

f

f

f

f

Dc

5

4

3

2

1

11000111011110110111

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

Step 3

I II III IV







LFSRSR



gate

x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 4 4

6 5





y1 y2

3 3 32

4 3 4

4 4gate

bsc



x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 1




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 2




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 3




x1 x2 x3 x4 x5 x6 x7

y1 y2

3 3 32

4 3 4

4 4gate

bsc

Segment 4










PIs

+

BSCs





Residue Polynomials


Ri(x) = xi mod f(x)


R0 R1 R2 Rk-1 Rk Ri




+x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5





hellipRpk


210 k-1 k i

R0 R1 R2 Rk-1 Rk Ri

Output G



exhaustively tested




x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2 3 4 5















LFSRXOR+ x3 + x + 1

1 x x2 x+1

x2+x

x2+x+1

0 1 2

++

3 4 5

XOR network




0 1 2 3 4 5 6

+

7



Permuted LFSRSR

0 1 2 3 4 5 6

+

7

0 2 5 1 3 4 6 7

inputs



Convolved LFSRSR

0 1 2 3 4 5 6

+

7+



Multiple LFSRSR

0 1 2 3

+

4 5 6 7

+

1 0 0 0 1 1 0 0

seed





















Tree Growing







XOR-Tree Generation



problem










Rj


R0 R1 R2 Rk-1

i

Ri

jN






backbone

branches

isolated oplus





R10 = R9 + R7

= R8 + R6 + R7

= R7 + R5 + R6 + R7








C432 (56 27 20) 056 44 12 0 0 9 C499 (49 40 14) 054 48 1 0 0 11 C880 (75 41 20) 064 69 6 0 0 13 C1355 (49 40 14) 277 47 2 0 0 11 C1908 (47 39 19) 241 41 4 2 3 10 C2670 (262 169 20) 1374 247 15 0 0 7 C3540 (118 90 20) 3482 72 45 1 6 27 C5315 (225 170 20) 7566 186 39 0 0 36 C6288 (87 87 20) 25937 59 25 3 15 25 C7552 (296 197 20) 3359 216 80 0 0 31












methods



Notes

Chapter 9




Board Level Testing

Sn m

Sn m

n

mMUXm



R1

R2









1149111491a






TAPC

MUX

Sin

Sout

MRsInstruction Reg

Bypass Reg

Application Logic



Boundary-Scan Path

TDITMS

TCKTDO

TAP

IO Pad




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control











bull IN-gtQA






Application Logic 2


TDI

TDO

Application Logic 1











Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Update-DR(Chip 1)




Chip 1

Chip 2

TDI

TDO

Capture-DR(Chip 2)




Chip 1

Chip 2

TDI

TDO

Shift-DR(Chip 2)




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Sample




0

1

MUX

S QA

Q1D

QB

Q1D

0

1

MUX

S

INOUT

SOUT

SIN

ShiftDR

ClockDR UpdateDR

Mode_Control

Shift inShift out




Chip 1TDI

Shift-DR

TDO

Chip 1TDI

Update-DR

TDO




Chip 1TDI

Capture-DR

TDO

Chip 1TDI

Shift-DR

TDO







Test Bus (22)





Ring Configuration

TDOTDI

TMSTCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS



Star Configuration

TDOTDI

TMS1

TCK

Busmaster

TDITCKTMSTDO

1

Application chips

TDITCKTMSTDO

2

TDITCKTMSTDO

N

TMSN

TMS2

TAPC

Registers

TAPC

Registers

TAPC

Registers

CKTMS









Bypass registers

M

U

X

Decoding logic MUX

TDOTMS

TCK


TDI

optional

optional



TAPC



SelectEnable

OutputBuffer




TAPC













shift registers



TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1


Run-testIdle

TMS = 1TMS = 0

TMS = 0

TMS = 1 TMS = 1 TMS = 1


Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR


Capture-IR

Shift-IR

Exit1IR

Pause-IR

Exit2-IR

Update-IR

TMS = 1

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 1 TMS = 0

TMS = 0

TMS = 0

TMS = 1

TMS = 0

TMS = 1

TMS = 0

TMS = 1



Test Data Registers


itself















BYPASS (12)

Bypass register

TAPC

TDOTMS TCKTDI

Application Logic



BYPASS (22)

Bypass register

TAPC

TDI

Application Logic

Bypass register

TAPC

TDO

Application Logic

1 2





















Chapter 10

Memory Testing










Fault Models (23)





Fault Models (33)




















hArr







hArr hArr hArr








hArrhArr

hArrhArr








hArr hArr

hArr

hArr

hArr






hArrhArrhArr






NPSF






ANPSF


b 1 rArr 0

n n nn b nn n n




PNPSF


n n nn b nn n n




SNPSF


n n nn b nn n n















Dynamic Faults


































Chapter 11

SOC Testing



















SOC Components


components



SOC Design Flow



by laws























tests




















or TAM











TAM























MUX

control











difficult



more complex








( )⎥⎥

⎦

⎥

⎢⎢

⎣

⎢ minus2MK

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡

Nf i




can be reduced as


pNfp1pN

f it ii

iiibull⎥⎥⎥

⎤

⎢⎢⎢

⎡++bull

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡= bull

p1Nf1pt i

iii bull+bull+=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛





can be reduced as


( )sumisin

⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull+=

Cip

Nf1pT i

ii

⎥⎥

⎤⎢⎢

⎡

isin+sum

isin⎟⎠

⎞⎜⎝

⎛+⎥⎥⎤

⎢⎢⎡bull=

Nf

CiCip

NfpT i

ii

i max








































core user











SOCET PrincetonNEC






Boundary Scan (12)





Boundary Scan (22)






























Test Bus




TestRail








test time





automation











pNf

1p11

C

1j

j +⎥⎥

⎤⎢⎢

⎡+ sum

=⎟⎠⎞⎜

⎝⎛






⎟⎠⎞⎜

⎝⎛

=⎟⎠⎞⎜

⎝⎛ minus+

⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minus pp

Nf

1pp 1212

C

2j

j

( ) 1ppNf

1ipp 0C

C

1i

C

ij

j1ii minus=+⎟

⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛sum ⎥

⎥

⎤⎢⎢

⎡+minusminussum

= =minus















pnf1pt i

iii

i++=

⎥⎥⎥

⎥

⎤

⎢⎢⎢

⎢

⎡⎟⎠⎞⎜

⎝⎛

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+⎥⎥

⎤⎢⎢

⎡+

isinp

nf1p i

i

iiCi

max





FF

FF

core

FF

FF

core




The SCDP Algorithm



















Wrapper + TAM

Daisychain



Wrapper Modes (14)

Normal Operation

Normal



Wrapper Modes (24)

InTest

InTest



Wrapper Modes (34)

ExTest

ExTest



Wrapper Modes (44)

Bypass

Bypass








simulation tools


Chapter 12



























Before integration



After integration












wrapper















(between WSI-WSO)






WPI-WPO





















wrapperbull Signals
























Shared Updated SE

Dedicated SEs


























bandwidths



















Notes











patterns










IEEE P14506 (CTL) (12)



P1500













CTL Key Words























































conversion












for core user






Unwrappedrsquo







SOC Test Creation









ndash Test re-use

























Overview of Example






Bare Core



STIL Test Patterns



Wrapped Core

WIP







WIP



Serial in Test Mode

WIP



Serial ExTest Mode

WIP




WIP




WIP



Wrapper Design (12)






Wrapper Design (22)























possible

3

2

1







Bypasses (12)







Bypasses (22)










minimized






(Hard)




(Easy)





(Easy)









Smi)(max

1











Ref [Grahamrsquo69]















Example Core (12)






+ 1 scan enable sc





Example Core (22)









Wrapper Result (24)





Wrapper Result (34)





Wrapper Result (44)





















inspection

















Interconnect ATPG

Normal ATPG







Interconnect Faults



Interconnect ATPG



algorithm
























Architecture Model












































Test Expansion




















Terminology (12)







Terminology (22)





Simple Example (12)




Simple Example (22)






Example SOC






Test Assembly




















Examples of Cores











httpwwwvsiacom







Notes



abc

s-a-1g

d

e

f

h

i

j

k

l

m

n

d

e

h



Fig 6-3[1990] Fig 6-4[1990] Fig 6-5[1990] Fig 6-10[1990]

Fig 6-23[1990] Fig 6-27[1990](pp 166 done)

Fig 6-29[1990] Fig 6-30[1990]

Fig 6-34[1990] Fig 6-37[1990]











Acknowledgements



An Example of SOC

ADC

DAC

PLL

RAMROM


ASIC 1

UDL

DSP CPU ASIC 2IP 2

Documents

Introduction to VLSI Testing and Design For Testability(DFT) TESTING...• Design for testability (DFT) – Chip area overhead, i.e., yield loss – Performance overhead, i.e., degradation