Introduction to Programmable Logic Devices

Introduction toProgrammable Logic Devices

Edward Freeman

STFC Technology Department

Detector & Electronics Division

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]

Programmable Logic is a Key Underlying Technology for PP Experiments.

First-Level and High-Level Triggering

Data Transport (Networks)

Computers interacting with Hardware (Networks)

Silicon Trackers (Millions of Data Channels)

Commercial Devices. Developments driven by Industry.

Telecomms, Gaming, Aerospace, Automotive, Set-top boxes….

PPD Lectures



CMS

CERN LHC

Particle Physics Electronics

Custom Electronics ChipsASICs ANALOGUE $$$Rad Hard, Low Power



CMS

CERN LHC

Electronics Rooms


Trigger Systems. DAQ Systems.DIGITAL

Custom Electronics ChipsASICs ANALOGUE $$$Rad Hard, Low Power

Custom Digital Processing BoardsVME Bus Crates




Special Dedicated Logic Functions (not possible in CPUs) Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate

Timing Massively Parallel Data Processing (Silicon Trackers with Millions of

Channels)

Custom DesignedPrinted Circuit Boards PCBs.

CommercialProgrammable LogicDevices, FPGAs



CMS DAQ/Trigger Architectures

CMS

“Telecoms Network” ~ 1 Tbps

Fully custom PP ASICs

CPUs Commodity PCs

Programmable LogicDIGITAL



Lecture Outline

Programmable Logic Devices Basics Evolution

FPGA Field Programmable Gate Array Architecture

Design Flow Hardware Description Languages Design Tools



Digital Logic

Logic Gates



Digital Logic

Logic Gates

Transistor Switches



Digital Logic

Logic Gates

Transistor Switches

< 40 nm ! $$$

MOORE’S LAW



Digital Logic

Black BoxSUM of PRODUCTS

Truth Table(Look Up Table LUT)

Digital Logic Function

3 Inputs

Product AND (&)Sum OR (|)



Digital Logic




3 Inputs




Digital Logic




3 Inputs




Programmable Logic Devices PLDs

Un-programmed State

SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC

Logic Functions

Planes ofANDs, ORs

Inputs

Outputs

ANDs

ORs




Un-programmed State


Logic Functions

Planes ofANDs, ORs

Inputs

Outputs

ANDs

ORs




Un-programmed State


Logic Functions

Planes ofANDs, ORs

Inputs

Outputs

ANDs

ORs




Un-programmed State


Logic Functions

Programmed PLD

Product Terms

Sums

Planes ofANDs, ORs

Inputs

Outputs

ANDs

ORs




Logic Functions

Programmed PLD

Product Terms

Sums




Logic Functions

Programmed PLD

Product Terms

Sums

x x

x x x




Logic Functions

Programmed PLD

Product Terms

Sums

x x

x x x x

x

GLUE LOGIC



Complex PLDs

CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links

CPLD Architecture

Feedback Outputs



Sequential Circuits Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)

Inputs



Sequential Circuits

RegisterCLOCK

New Output every clock edge

Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)

Inputs

Intermediate

EDGES



Sequential Circuits

RegisterCLOCK

New Output every clock edge

Shift Registers,Pipelines,Finite State Machines…

Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)

Clock Rate determines speed

Comb Logic Must meet Timing=> Predictable circuits

Inputs

Intermediate

EDGES



Field Programmable Gate Arrays FPGA

Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for

memory chips (Moore’s Law)




Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for

SRAM memory chips (Moore’s Law)

Huge Density of Logic Block ‘Islands’

1,000 … 100,000’s

in a ‘Sea’ of Interconnects

FPGA Architecture






Logic Blocks

Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs)

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

FPGA Fabric Logic Block



Look Up Tables LUTs

LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

3 Inputs LUT -> 8 Memory Cells

SRAM

Static Random Access MemorySRAM cells

SRAM

3 – 6 Inputs

Multiplexer MUX



Look Up Tables LUTs LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

3 Inputs LUT -> 8 Memory Cells

SRAM

Static Random Access MemorySRAM cells

SRAM

3 – 6 Inputs

Multiplexer MUX



Logic Blocks

Larger Logic Functions built up by connecting many Logic Blocks together



Logic Blocks

Larger Logic Functions built up by connecting many Logic Blocks together

Determined by SRAM cells

SRAM SRAM cells



Clocked Logic

Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency)

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

FPGA Fabric

Clock from Outside world (eg LHC bunch frequency)

Special Routing for Clocks



Input Output I/O Getting data in and out

01

54

6

7

3

2

General-purpose I/Obanks 0 through 7Up to > 1,000 I/O “pins” (several 100 MHz)



Input Output I/O Getting data in and out

01

54

6

7

3

2

General-purpose I/Obanks 0 through 7

FPGA

Differential pairs

Transceiver block

Up to > 1,000 I/O “pins” (several 100 MHz)

Special I/O SERIALISERS~ 10 Gbps transfer rates

Optical TRx



Designing Logic with FPGAs

Design Capture. High level Description of Logic Design.

Graphical descriptions Hardware Description Language (Textual)

Graphical State Diagram

Graphical Flowchart

When clock rises If (s == 0) then y = (a & b) | c; else y = c & !(d ^ e);

Textual HDL

Top-levelblock-levelschematic

Block-level schematic



Hardware Description Languages

Language describing hardware (Engineers call it FIRMWARE) Doesn’t behave like “normal” programming language ‘C/C++’ Describe Logic as collection of Processes operating in

Parallel Language Constructs for Synchronous Logic

Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic

Not all constructs can be implemented in FPGA!

2 Popular languages are VHDL , VERILOG Easy to start learning… Hard to master!



VHDLENTITY Declaration Input Output to Module (STD LOGIC)

SIGNALS Declaration WIRES

CONCURRENT ASSIGNMENTS

CONDITIONAL ASSIGNMENTS => MULTIPLEXERS



VHDL

COMPONENT Declaration

PROCESS Declaration. CONCURRENT functions. Synchronous Logic.



Designing Logic with FPGAs High level Description of Logic Design

Hardware Description Language (Textual)

Compile (Synthesis) into NETLIST. Boolean Logic Gates.

Target FPGA Device Mapping Routing

Bit File for FPGA

Commercial CAE Tools(Complex & Expensive)

Logic Simulation

Gate-levelnetlist

BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;

GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);

END CIRCUIT=TEST;

Fully-routed physical(CLB-level) netlist

Schematiccapture

Mapping

Packing

Place-and-Route Timing analysis

and timing report

Gate-level netlistfor simulation

SDF (timing info)for simulation

Design Flow







Bit File for FPGA


Logic Simulation

Gate-levelnetlist



END CIRCUIT=TEST;


Schematiccapture

Mapping

Packing


and timing report



Design Flow







Bit File for FPGA


Logic Simulation

Gate-levelnetlist



END CIRCUIT=TEST;


Schematiccapture

Mapping

Packing


and timing report



Design Flow



Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is

turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile

Memory e.g. PROM or Digital Camera card Configuration takes ~ secs

Configuration data in

Configuration data out

= I/O pin/pad

= SRAM cell

SRAM

JTAG Port



Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is

turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile

Memory e.g. PROM or Digital Camera card Configuration takes ~ secs

Configuration data in

Configuration data out

= I/O pin/pad

= SRAM cell

SRAM

JTAG Testing

JTAG Port

ProgrammingBit File




Large Complex Functions Re-Programmability, Flexibility.

Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor

Fast Turnaround Designs Standard IC Manufacturing Processes. Moore’s Law Mass produced. Inexpensive. Many variants. Sizes. Features.

PP Not Radiation Hard Power Hungry No Analogue



FPGA Trends

State of Art is 40nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA)

Logic Block cost ~ 1$ in 1990 Today < 0.1 cent

Problems Power. Leakage currents. Design Gap

CAE Tools 0.0001

0.001

0.01

0.1

1

1990 1995 2000 2005 2010 2015$

/ L

C

1.00E+02

1.00E+03

1.00E+04

1.00E+05

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1985 1990 1995 2000 2005 2010 2015 2020 2025

Year

Nu

mb

er

of

LC

s



Summary

Programmable Logic Devices Basics Evolution

FPGA Field Programmable Gate Arrays Architecture

Design Flow Hardware Description Languages Design Tools

Importance for Particle Physics Experiments



References

The Design Warrior’s Guide to FPGAs Clive Maxfield, Newnes Elsevier

VHDL for Logic Synthesis Andrew Rushden, Wiley

FPGA manufacturer web sites www.xilinx.com www.altera.com

FPGA Online www.pldesignline.com www.fpgajournal.com www.doulos.com



Spare Slideslibrary IEEE; -- call some library'suse IEEE.STD_LOGIC_1164.ALL; -- “--” is a commentUSE ieee.std_logic_arith.all;

-- define a black box for the component neededentity counter is -- what is the component called

port( -- what IO dose it haveclk : in std_logic; -- clk = Clock. All synchronous logic has a clockrst : in std_logic; -- rst = reset. Most synchronous logic has a reset.count : out std_logic_vector(7 downto 0) -- 8 wires in a bundle with no interpretation. );

end counter;

-- what logic should be in the black boxarchitecture RTL of counter is -- this version on the content of the black box is called “RTL”

begin -- start the logic that is inside the black boxprocess (clk,rst) -- start a process i.e. Sequential logic. The list in brackets is a sensitivity

listvariable v_count : unsigned ( 7 downto 0); -- declare a local variable called v_count

begin -- start logic processif rst = '1' then -- async reset i.e. It dose not wait for a clock edgecount <= (others => '0'); -- set all the bits of count to zerov_count := (others => '0'); -- set all bits to zero note variable assignment not signal assignment.elsif clk'event and clk = '1' then -- wait for the rising edge of clock

v_count := v_count + 1; -- add one to current value of count and asign to end if;end process;

count <= conv_std_logic_vector(v_count,8);end RTL;

Documents

Introduction to Programmable Logic Devices