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Case study

On

Microprocessors

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Intel processor Family

Integrated electronics popularly known as Intel is the worlds largest manufacturer of

silicon based Microprocessors and Microcontrollers. Intel have introduced a very vast

generation of microprocessors to the world. Some of them made a lasting impact on theindustry. Few of its remarkable processors are listed below:

Intel 8008 Processor:

8008 instruction set consists of 48 instructions:

Data moving instructions. Arithmetic - add, subtract, increment and decrement. Logic - AND, OR, XOR, compare and rotate.

Control transfer - conditional, unconditional, call subroutine, return from subroutineand restarts.

Input/output instructions. Other - Halt instruction.

Instruction length can be from 1 to 3 bytes.

Addressing Modes:

Register - references the data in a register.Register indirect - instruction specifies HL register pair containing address, where the data

is located.

Immediate.

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Intel 8080 Processors:

8008 instruction set consists of 75 instructions.

Instruction set: ADD, ADC, ADI, ANA, ANI, CALL, CNZ, CZ, CNC, CC, CPO, CPE, CP, CM, CPI, CMA,

CMC, CMP, DCR, DCX, DAD, DAA, DI, EI, HLT, IN, INR, INX, JMP, JNZ, JZ, JNC, JC, JPO, JPE, JP, JM,LXI, LDAX, LHLD, LDA, MOV, MVI, NOP, OUT, ORA, ORI, PCHL, POP, PUSH, RET, RNZ, RZ, RNC, RC,

RPO, RPE, RP, RM, RST, RLC, RRC, RAL, RAR, SBI, SUI, SHLD, STA, STAX, SPHL, STC, SBB, SUB, XRA,

XRI, XTHL, XCHG.

Addressing modes:

Implied addressing Register addressing Register indirect addressing

Immediate addressing Direct addressing

Intel 8085 Processors:

8085 instruction set consists of 246 instructions.

Ex: JMP, JC, JZ, CALL, CZ, RST, AND, OR,ANA, XRA, ORA, CMP, and RAL etc.

Addressing Modes:

Direct Addressing Mode Register Addressing Mode Register Indirect Addressing Mode Immediate Addressing Mode Implicit Addressing Mode

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Intel 8086 Processors:

8086 instruction set consists of:

Data moving instructions. Arithmetic - add, subtract, increment, decrement, convert byte/word and compare. Logic - AND, OR, exclusive OR, shift/rotate and test. String manipulation - load, store, move, compare and scan for byte/word. Control transfer - conditional, unconditional, call subroutine and return from

subroutine.

Input/output instructions. Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes:

Implied - the data value/data address is implicitly associated with the instruction. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is located. Register indirect - instruction specifies a register containing an address, where data is

located. This addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register(BX or BP), the resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an indexregister (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of anindex register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to thecontents of a base register (BX or BP) and index register (SI or DI), the resulting value is a

pointer to location where data resides.

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Intel Core i7 Processors:

Architecture:

Intel Microarchitecture Code Name Nehalem

Intel microarchitecture code name Nehalem provides the foundation for many innovative

features of Intel Core i7

Processors it builds on the success of 45nm Intel Core microarchitecture and provides the

following feature

Enhancements:

Enhanced processor core

Improved branch prediction and recovery from misprediction.

Enhanced loop streaming to improve front end performance and reduce power

consumption.

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Deeper buffering in out-of-order engine to extract parallelism.

Enhanced execution units to provide acceleration in CRC, string/text processing and data

shuffling.

Smart Memory Access

Integrated memory controller provides low-latency access to system memory and scalable

memory

Bandwidth

New cache hierarchy organization with shared, inclusive L3 to reduce snoop traffic

Two level TLBs and increased TLB size.

Fast unaligned memory access.

Hyper Threading Technology

Provides two hardware threads (logical processors) per core.

Takes advantage of 4-wide execution engine, large L3, and massive memory bandwidth.

Dedicated Power management Innovations

Integrated microcontroller with optimized embedded firmware to manage power

consumption.

Embedded real-time sensors for temperature, current, and power.

Integrated power gate to turn off/on per-core power consumption

Versatility to reduce power consumption of memory, link subsystems.

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Intel Core i7 instruction set consists of:

GENERAL-PURPOSE INSTRUCTIONS:

The general-purpose instructions preform basic data movement, arithmetic, logic, program

flow, and string operations that programmers commonly use to write application and system

software to run on Intel 64 and IA-32 processors. They operate on data contained in memory, in

the general-purpose registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP) and in the EFLAGS

register. They also operate on address information contained in memory, the general-purpose

registers, and the segment registers (CS, DS, SS, ES, FS, and GS).

This group of instructions includes the data transfer, binary integer arithmetic, decimal

arithmetic, logic operations, shift and rotate, bit and byte operations, program control, string,

flag control, segment register operations, and miscellaneous subgroups, the sections that

following introduce each subgroup.

1.Data Transfer InstructionsThe data transfer instructions move data between memory and the general-purpose and

segment registers. They also perform specific operations such as conditional moves, stack

access, and data conversion.

Example:

MOV-Move data between general-purpose registers; move data between memory and general

purpose or segment registers; move immediate to general-purpose registers

CMOVE/CMOVZ-Conditional move if equal/Conditional move if zero

2. Binary Arithmetic InstructionsThe binary arithmetic instructions perform basic binary integer computations on byte, word,

and double word integers located in memory and/or the general purpose registers.

Example:

ADD Integer add

ADC Add with carry

SUB Subtract

SBB Subtract with borrow

IMUL Signed multiply

MUL Unsigned multiplyIDIV Signed divide

DIV Unsigned divide

INC Increment

DEC Decrement

NEG Negate

CMP Compare

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3. Decimal Arithmetic InstructionsThe decimal arithmetic instructions perform decimal arithmetic on binary coded decimal (BCD)

data.

Example:

DAA Decimal adjust after additionDAS Decimal adjust after subtraction

AAA ASCII adjust after addition

AAS ASCII adjust after subtraction

AAM ASCII adjust after multiplication

AAD ASCII adjust before division

4. Logical InstructionsThe logical instructions perform basic AND, OR, XOR, and NOT logical operations on byte, word,

and double word values.

Example:

AND Perform bitwise logical AND

OR Perform bitwise logical OR

XOR Perform bitwise logical exclusive OR

NOT Perform bitwise logical NOT

5. Shift and Rotate InstructionsThe shift and rotate instructions shift and rotate the bits in word and doubleword operands.

Example:SAR Shift arithmetic right

SHR Shift logical right

SAL/SHL Shift arithmetic left/Shift logical left

SHRD Shift right double

SHLD Shift left double

ROR Rotate right

ROL Rotate left

RCR Rotate through carry right

RCL Rotate through carry left

6. Bit and Byte InstructionsBit instructions test and modify individual bits in word and doubleword operands. Byte

instructions set the value of a byte operand to indicate the status of flags in the EFLAGS

register.

Example:

BT Bit test

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BTS Bit test and set

BTR Bit test and reset

BTC Bit test and complement

BSF Bit scan forward

BSR Bit scan reverse

SETS Set byte if sign (negative)SETNS Set byte if not sign (non-negative)

SETO Set byte if overflow

SETNO Set byte if not overflow

TEST Logical compare

7. Control Transfer InstructionsThe control transfer instructions provide jump, conditional jump, loop, and call and return

operations to control program flow.

Example:JMP Jump

JE/JZ Jump if equal/Jump if zero

JC Jump if carry

JNC Jump if not carry

JO Jump if overflow

JNO Jump if not overflow

JS Jump if sign (negative)

JNS Jump if not sign (non-negative)

LOOPLoop with ECX counter

LOOPZ/LOOPE Loop with ECX and zero/Loop with ECX and equal

LOOPNZ/LOOPNE Loop with ECX and not zero/Loop with ECX and not equal

CALLCall procedure

RET Return

IRET Return from interrupt

INT Software interrupt

INTO Interrupt on overflow

BOUND Detect value out of range

ENTER High-level procedure entry

LEAVE High-level procedure exit

8. String InstructionsThe string instructions operate on strings of bytes, allowing them to be moved to and from

memory.

Example:

MOVS/MOVSB Move string/Move byte string

MOVS/MOVSW Move string/Move word string

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MOVS/MOVSD Move string/Move doubleword string

CMPS/CMPSB Compare string/Compare byte string

CMPS/CMPSW Compare string/Compare word string

CMPS/CMPSD Compare string/Compare doubleword string

REP Repeat while ECX not zero

REPE/REPZ Repeat while equal/Repeat while zeroREPNE/REPNZ Repeat while not equal/Repeat while not zero

9. I/O InstructionsThese instructions move data between the processors I/O ports and a register or memory.

IN Read from a port

Example:

OUT Write to a port

INS/INSB Input string from port/Input byte string from port

INS/INSW Input string from port/Input word string from portINS/INSD Input string from port/Input doubleword string from port

OUTS/OUTSB Output string to port/Output byte string to port

OUTS/OUTSW Output string to port/Output word string to port

OUTS/OUTSD Output string to port/Output doubleword string to port

10. Enter and Leave InstructionsThese instructions provide machine-language support for procedure calls in block-structured

languages.

Example:

ENTER High-level procedure entry

LEAVE High-level procedure exit

11. Flag Control (EFLAG) InstructionsThe flag control instructions operate on the flags in the EFLAGS register.

Example:

STC Set carries flag

CLC Clear the carry flag

CMC Complement the carry flag

CLD Clear the direction flagSTD Set direction flag

LAHF Load flags into AH register

SAHF Store AH register into flags

PUSHF/PUSHFD Push EFLAGS onto stack

POPF/POPFD Pop EFLAGS from stack

STI Set interrupt flag

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CLI Clear the interrupt flag

12. Segment Register InstructionsThe segment register instructions allow far pointers (segment addresses) to be loaded into the

segment registers.

Example:

LDS Load far pointer using DS

LES Load far pointer using ES

LFS Load far pointer using FS

LGS Load far pointer using GS

LSS Load far pointer using SS

13. Miscellaneous Instructions

The miscellaneous instructions provide such functions as loading an effective address,executing a no-operation, and retrieving processor identification information.

Example:

LEA Load effective address

NOP No operation

UD2 Undefined instruction

XLAT/XLATB Table lookup translation

CPUID Processor identification

MOVBE Move data after swapping data bytes

14. Random Number Generator InstructionRDRAND retrieves a random number generated from hardware.

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Addressing modes:

The addressing modes describe how the processor can specify theaddress of an object.

Intel core i7 supports the following addressing modes:

1.Register -Register addressing mode is similar to direct addressing. The only difference is that

the address field of the instruction refers to a register rather than a memory location 3 or 4 bits

are used as address field to reference 8 to 16 generate purpose registers. The advantages of

register addressing are Small address field is needed in the instruction.

2. Immediate - This is the simplest form of addressing. Here, the operand is given in the

instruction itself. This mode is used to define a constant or set initial values of variables. The

advantage of this mode is that no memory reference other than instruction fetch is required to

obtain operand. The disadvantage is that the size of the number is limited to the size of the

address field, which most instruction sets is small compared to word length.

3. Displacement-In displacement addressing mode there are 3 types of addressing mode. They

are:

1) Relative Addressing

2) BaseRegister Addressing

3) Indexing Addressing.

This is a combination of direct addressing and register indirect addressing. The value contained

in one address field. A is used directly and the other address refers to a register whose contents

are added to A to produce the effective address.

4. Indirect - Indirect addressing mode, the address field of the instruction refers to the address

of a word in memory, which in turn contains the full length address of the operand. The

advantage of this mode is that for the word length of N, an address space of 2N can be

addressed. He disadvantage is that instruction execution requires two memory reference to

fetch the operand Multilevel or cascaded indirect addressing can also be used.

5. Indexed - This also requires space in an instruction for quite a large address. The address

could be the start of an array or vector, and the index could select the particular array element

required. The processor may scale the index register to allow for the size of each array element.

Note:- that this is more or less the same as base-plus-offset addressing mode, except that the

offset in this case is large enough to address any memory location.

6. Direct -In direct addressing mode, effective address of the operand is given in the address

field of the instruction. It requires one memory reference to read the operand from the given

location and provides only a limited address space. Length of the address field is usually less

than the word length.

http://en.wikipedia.org/wiki/Stride_of_an_arrayhttp://en.wikipedia.org/wiki/Stride_of_an_array

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7. Memory indirect - Any of the addressing modes mentioned in this article could have an extra

bit to indicate indirect addressing, i.e. the address calculated using some mode is in fact the

address of a location (typically a complete word) which contains the actual effective address.

Indirect addressing may be used for code or data. It can make implementation ofpointers or

references orhandlesmuch easier, and can also make it easier to call subroutines which are not

otherwise addressable. Indirect addressing does carry a performance penalty due to the extra

memory access involved.

http://en.wikipedia.org/wiki/Word_(data_type)http://en.wikipedia.org/wiki/Handle_(computing)http://en.wikipedia.org/wiki/Handle_(computing)http://en.wikipedia.org/wiki/Handle_(computing)http://en.wikipedia.org/wiki/Word_(data_type)