Integrated, Quad RF Transceiver with Observation Path Data 2019-12-03آ  Integrated, Quad RF Transceiver

Integrated, Quad RF Transceiver with Observation Path

Data Sheet ADRV9026

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FEATURES 4 differential transmitters 4 differential receivers 2 observation receivers with 2 inputs each Center frequency: 650 MHz to 6000 MHz Maximum receiver bandwidth: 200 MHz Maximum transmitter large signal bandwidth: 200 MHz Maximum transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated independent fractional-N radio frequency

synthesizers Fully integrated clock synthesizer Multichip phase synchronization for all local oscillators and

baseband clocks Support for TDD and FDD applications 16 Gbps JESD204B/JESD204C digital interface

APPLICATIONS 3G/4G/5G TDD and FDD massive MIMO, macro and small cell

base stations

GENERAL DESCRIPTION The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.

The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.

The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital- to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated.

To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.

A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.

The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 16 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.

The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm × 14 mm, 289-ball chip scale ball grid array (CSP_BGA).

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ADRV9026 Data Sheet

Rev. 0 | Page 2 of 117

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4

Transmitters and Receivers ......................................................... 4 Synthesizers, Auxiliary ADCs, Reference ............................... 11 Digital Specifications ................................................................. 14 Power Supply Specifications...................................................... 15 Current Consumption ............................................................... 16 Digital Interface and Timing Specifications ........................... 17

Absolute Maximum Ratings .......................................................... 18 Junction Temperature ................................................................ 18 Reflow Profile .............................................................................. 18 Thermal Resistance .................................................................... 18 ESD Caution ................................................................................ 18

Pin Configuration and Function Descriptions ........................... 19 Typical Performance Characteristics ........................................... 24

800 MHz Band ............................................................................ 24

1800 MHz Band .......................................................................... 39 2600 MHz Band .......................................................................... 54 3800 MHz Band .......................................................................... 69 4800 MHz Band .......................................................................... 84 5700 MHz Band .......................................................................... 99

Theory of Operation .................................................................... 114 General....................................................................................... 114 Transmitter ................................................................................ 114 Receiver...................................................................................... 114 Observation Receiver ............................................................... 114 Clock Input ................................................................................ 114 Synthesizers ............................................................................... 114 SPI Interface .............................................................................. 115 GPIO_x Pins ............................................................................. 115 Auxiliary Converters ................................................................ 115

Applications Information ............................................................ 116 Power Supply Sequence ........................................................... 116 Data Interface ............................................................................ 116

Outline Dimensions ..................................................................... 117 Ordering Guide ........................................................................ 117

REVISION HISTORY 11/2019—Revision 0: Initial Version

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Data Sheet ADRV9026

Rev. 0 | Page 3 of 117

FUNCTIONAL BLOCK DIAGRAM

22 38

2- 00

1

SERDOUTA± SERDOUTB±

SYNCOUT1± SYNCOUT2±

ORX_CTRL_x

RXx_EN GPINT2 GPINT1

TXx_EN

RESET TEST_EN

SPI_DIO SPI_DO SPI_EN SPI_CLK

SYSREF± DEVCLK±

GPIO_x AUXADC_x GPIO_ANA_x

JESD204B/ JESD204C

SERIAL INTERFACE

RX1+ RX1– RX2+ RX2–

RX3+ RX3– RX4+ RX4–

ADC

ADC

Rx1

Rx2

RX1, RX2, TX1, TX2, ORX1/ORX2

RX3, RX4, TX3, TX4, ORX3/ORX4

0° 90° M

U X LO1

LO2

M U

X LO1

LO2 M

U X

LO3

DECIMATION, PROGRAMMABLE FIR,

AGC, DC-OFFSET,

QEC, TUNING,

RSSI, OVERLOAD

TX1+ TX1– TX2+ TX2–

TX3+ TX3– TX4+ TX4–

DAC

DAC

Tx1

Tx2

pFIR, LO LEAKAGE,

QEC, TUNIN