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C. Schrader; Sept. 2011, Mont Sainte Odile, Workshop Ins

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The CBM-MVD read-out system

Christoph Schrader for the CBM-MVD Collaboration

1

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2

Demo(MI20)

data synchronization…

Prototype v2 (MI26) optical readout sensor ladder compatible to a

dedicated MVD sensor

Prototype SIS-100

(MISTRAL)

2009

2010

2011

2012

2013

2014

DAQ project phases

Prototype v1 (MI26) conservative approach (based on LVDS signals) full readout concept full bandwidth

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3

Prototype

Version 1

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pixel array:1152 columns x 576 rows

(18.4 µm pitch and 115.2 µs readout time)

JTAG Digitalinput

Digital output

DACs4 x memory banks

PLLTempprobe

Discritest Power

1152 discriminatorszero suppression logic

CDS

2 channels D0,D1+clock80 MHz

160 Mbit/s

9 hits/ row

∑ 570 hits

multiplexer

4~ 80 Mbit/s (570 words of 16 bit

~ 9120 bit/frame)

available

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FPC

based on MIMOSA-26

FEB

. . .

vacuum

clockstartresetJTAG

converterboard

converterboard

converterboard

. . .

readout controller

board

driver board

FEB

sensors

. . .

readout controller

board

FEB

LVDS, 1m4x 80 Mbit/s (MIMOSA-26)

LVDS4 x 80 Mbit/s

FPC

2 Gbit/soptical fiber to theMVD network

FPC

Slow control board

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material material budget [% x/Xo]

Polyimide (12.5 µm) 0.0044

Adhesive (15 µm) 0.0043

Copper (18 µm) 0.063 (Alu 0.011)

Adhesive (20 µm) 0.0057

Polyimide (25 µm) 0.0087

∑Cu~0.0861 % x/Xo*

sensor

copper/ aluminum

Adhesive (20 µm)

polyimide

wire bonds

2018

50

µm

10

µm

polyimideconnector pads

1525

12.5

Flex-Print Cable

# of wires 50

wire length 500 mm

pitch 200 µm

resistance 2.47 Ω (measured 2.75Ω)

capacity 12 pF

inductivity 12 µH

max. frequency 400 MHz (LVDS)∑Alu~0.032 % x/Xo * **

* 100% fill factor ** same dimension as copper

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C. Schrader; Sept. 2011, Mont Sainte Odile, Workshop7

Flex-Print Cable

10 MHz

- 22 dB

Single-ended crosstalk

B.

Neu

man

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C. Schrader; Sept. 2011, Mont Sainte Odile, Workshop8

- 22 dB

Flex-Print Cable

could be better to have differential signal for JTAG

B.

Neu

man

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9

. . .

clockstartresetJTAG

FPCFPC

The FEB:• transfer D0,D1,clock to

the converter boards (0.5 m away)• to loop clock, reset, start, JTAG• passive filters for power supply

FPC

D0,D1clockTDOTempcurrent

FEB

FPC FPC FPC

full passive board(more radiation tolerant)

FEB FEB FEB

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• signal conditioning for data transfer

• power supply for LVDS drivers• diode based temperature measurement

(internal sensor diode)• 6 channel ADCs to transfer in serial

the current and temperature• current monitor and protection to

disable the power of the sensors (in case of latch-up)• switch for JTAG chain

shutdown <2 µs

power on 200 µs

10

Converter Board

FEB

converterboard

converterboard

converterboard

readout controller

FEB FEB

readout controller

see talk: M.Koziel

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11

Sensor slow control via JTAG

Requirements for the slow control system: Initializing of each sensor via JTAG Scalability: > 100 MAPS Sequential reading of the sensor ID Triggered monitoring/reprogramming of the sensor parameters (during a spill break) Error detection and error logging Automatic hardware bypassing/unbypassing by hardware switch for faulty sensors New arrangement and initialization of prober sensors left (40 sensors < 10ms) Compatible to the control software “EPICS”

Switch should be integrated in the sensor

Slow control board

Converter board

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TrbNet

converter boards converter boards

4 optical links up to 3.8 Gbit/s each

readout controller

board

readout controller

board

LVDS4 x 80 Mbit/s

Readout ControllerBoard

HADES optical Hub

PexorPCI-Express card

20x up to 3.125 Gbit/s

LVDS4 x 80 Mbit/s

MVD Network

see talk:J.Michel

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Data checking- Is the MAPS turned on?- HDR/TRA has arrived- Is the frame number OK?- Is the data length OK?- Is the entire frame OK?- Is the time between frames 115,2 us?- Are the MAPS out-of-sync?- Is the Arbiter SYNC pulse OK?- Buffer overflow

Data is consistent!consecutive frame numbers is 0x2D00 cycles, or 11520!

= 115,2 usNumber of data packets isalways 0x023a, or 570!

0x84a8 – 0x57a8 ------------ 0x2D00

B.

Mila

novi

c

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14

Prototype

Version 2 compatible to dedicated MVD SIS-100 sensor sensor ladder optical readout

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15

32 m

m

pixe

l arr

ay

~10 mm

digi

tal d

ata

spar

sific

ation

~2.5 mm

readout readout

Available in 2014 double side readout based on MIMOSA-26 readout protocol 2 output pairs with 200 MHz

MISTRAL

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16

see talk:T.Tischler

MISTRAL sensors

2st Station @ 10 cm

FEB

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FPCFPC

Flex-Print Cable

FEB

pads sensorsbonds

FPC pads (FEB side) for MIMOSA-26

bus (signal chain)Individual signals/sensor 7 lines/sensor

17

∑Cu~0.075 % x/Xo∑Alu~0.036 % x/Xo

Copper (18 µm) 0.0315

Adhesive (20 µm) 0.0057

Polyimide (12.5 µm) 0.0044

Adhesive (15 µm) 0.0043

Copper (18 µm) 0.0158

Adhesive (20 µm) 0.0057

Polyimide (12.5 µm) 0.0044

% x/Xo

The half sensors has to be reversed left to right

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Sensor (50 µm Si)0, 0.0534

FPC (copper/alu) 0.08/0.04

CVD (150 µm) 0.11

Adhesive (20 µm) 0.0057

Polyimide (25 µm) 0.0087

18

CVD

Σcu~0.40 % x/Xo

10 mm

< 8 mm

active

ΣAlu~0.30 % x/Xo

adhesive 9%poly-imid

e6%

copper31%sensors

26%

CVD27%

adhesive9%

poly-imid

e6%

ALU5%

26%sensors26%

CVD27%

see talk: T.Tischler

FPC

FPC

% x/Xo

~ 17

0 µm

150

µm

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CBMNet19

. . .

vacuumclockstartresetJTAG

converterboard

converterboard

converterboard . . .

readout controller

board

driver board

10x 200 Mbit/sLVDS, 1m

1 Gbit/soptical fibers

. . .

readout controller

board

Prototype Version2

LVDS10 x 200 Mbit/s

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Thank you

20

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C. Schrader; Sept. 2011, Mont Sainte Odile, Workshop21

Flex-Print Cable

20 MHz

log20 ≥ -1.58 dB

1.58 dB

Single-ended power attenuation

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C. Schrader; Sept. 2011, Mont Sainte Odile, Workshop22

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C. Schrader; Sept. 2011, Mont Sainte Odile, Workshop23

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24

Devices:

• FPC: FCI opuserie62684-362100

• JTAG switch: SN65LVDCP22PW

• 6 channel ADC: LTC1408

• optical links: normal SFPs

• ROC FPGA: ECP2M Lattice

• 8b/10b encoding: TLK2501IRCP

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25

Synchronization

and time management

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26

Hub

Arbiter

Synchronization

Slow control board

MAPS MAPS MAPS

ROC ROC ROC There is one common clockfor all devices!Arbiter provides clock(LVDS, optical)

clockequally long

LVDS

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27

Synchronization

Hub

Arbiter

MAPS MAPS MAPS

ROC ROC ROCSync

equally long LVDS

During each SYNC pulse from the Arbiter, the ROCs detect if the MAPS are running out-of-sync(10 ns resolution) Errors are reported to the Arbiter,which can schedule a reset andreprogramming during next spill-break.The OOS resolution depends on FPGA frequency.

Time between SYNCs is the readout time of one frame (115,2 us). If using one common clock the SYNCs can be issued with 100% accuracy (no time delays!).

Slow control board

start

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28

Hub

Arbiter

MAPS MAPS MAPS

ROC ROC ROC

buf buf buf

Frame Req.

The Arbiter sends to the ROCs a frame request to save the next frame data in the buffer. The latency for that message can be several microseconds.(<<30 µs)

The frame request contains the frame number and further processing information.

Data readout

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Data readout

Hub

Arbiter

MAPS MAPS MAPS

ROC ROC ROC

Frame data are buffered in the ROCs.

ROCs report about their status to the arbiter (error handling).

buf buf buf

In case of buffer overflow the arbiter decide to throw the data away for the given frame of all boards.

acknowledge Req.

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30

Hub

Arbiter

MAPS MAPS MAPS

ROC ROC ROC

buf buf buf

If JTAG detects a JTAG error in the sensor, it will remove it from the chain and turn it off.

If any sensor is showing errors in its data or is turned-offthe data are marked as false.

Error handling

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31

Data readout

Hub

Arbiter

MAPS MAPS MAPS

ROC ROC ROC

Readout for one frame is requested ROCs send the corresponding data to the hubs.

buf buf buf

dataReadout Req.

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• high data-rate digital interface connector (15 Gbit/s)

• FPGA configuration• high data transfer with optical link

(2 Gbit/s)• application process interface (API)• power supply +5V, 10A• clock distribution • slow control via

ethernet optical link (TrbNet)

A standard platform

the TRBv2 (HADES) provides a flexible add-on board concept

32

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• sensor controlling• handle up to 4 digital

channels (2 sensors)• platform to study online data

sparsifications- for data reduction- fake hit suppression

• compatibility with HADES DAQ (TrbNet) for data transfer

developed by IKF electronic workshop

the add-on board with a FPGA is mounted on the TRBv2 back side

The controller board

future upgrade:to handle several prototype modules

33

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• 20x up to 3.125 Gbit/s

• capable of Gigabit-Ethernet to

send data to standard PCs (TCP)

• implements basic data processing

features

• de-multiplexer for I/O’s

• buffered readout

34

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furt PC-Interface: PEXOR 3

• PCI-Express card

• fast Lattice SCM40 FPGA

• TrbNet (HADES)

• 4 optical links up to 3.8 Gbit/s each

35

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hub

Controllerboard

Controllerboard

Trbv2

Trbv2

readout of several prototypes is possible

36

to test:• data protocol• data reduction 160Mbit/s 80Mbit/s• network

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Number of ROCs

station @5cm @10cm

# sensors 40 120raw data rate[Gbit/s]

40 120

compressed data rate [Gbit/s] for Au-Au @ 10A.GeV

12 8

compressed data rate [Gbit/s] for p-Au @ 30GeV

14 20

station @5cm @10cm

# of input channels 40 120

# number of ROCs 8 15

max. output data rate [Gbit/s] 48 90

load/station [%](Au-Au @ 10A.GeV) 32 11

load/station [%](p-Au @ 10A.GeV) 36 28

ROC with one FPGA: 8x input (1Gbit/s)2x output (3 Gbit/s)1x slow control

~ factor 3for safety

data rates hardware required

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Front side

number of sensors tocover the CBM acceptance at:

~ 5cm

~ 1cm

distance from target 5 cm 10 cm

# sensorsMIMOSA-26 16 48

MIMOSIS-1 40 120

The MVD detector design

FPC

FPC

FPC

FPC back side

inactive area

first station based on MIMOSA-26 form factor

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FPC

39

FEB

. . .

driver board

FEB FEBFPC

The FEB:• full passive board• transfer D0,D1,clock to

the converter boards (<1m away)• to loop clock, reset, start, JTAG• passive filters for power supply

The driver board:

- feed through for the

vacuum vessel

- to loop clock, reset, start, JTAG

- converts JTAG, start, reset (LVDS) LVTTL

- <2m away from the FEB

FPC as FEB

first version for prototype (MIMOSA-26)

repla

ced b

y FPC

with

passi

ve filte

r

FPC

material budget:∑Cu~0.086 % x/Xo∑Alu~0.032% x/Xo

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.

.

.

de-MU

X

frame HDRdata 0data 1data 2

…

channel pattern

word

pattern

word

pattern

.

.

.

.

.

.

time stampsslow control…

8 bitin parallel @100 MHz

FPGA

8 bit/channelin serial@400 MHz

8 bit/channelin parallel @50 MHz

16 bit/channelin parallel @50 MHz800 Mbit/s

16 bit/channelin parallel @50 MHz< 300 Mbit/s

Word/channel patternbuffer

RAM

FIFO

FIFO

select out the place holderand words which are send twice like HDR and trailer

10b/

8b datareduction

infos.flags

FEE??

FEEprocessing

D0

D1

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FEB

buffer?clock

reset

start

JTAG

FP

C FPC

pads for sensors

converterLVDSLVTTL

cloc

k (L

VD

S)

rese

t

star

t

JTA

G

LVT

TL

cloc

k (L

VD

S)

D0,

D1

(LV

DS

)

buffer?

TD

O (L

VT

TL

)

converterLVTTLLVDS

+ amplification

Tem

p (L

VT

TL

)

TDI (LVDS)

FPC to converter board

buffers/converters are critical in case of radiation damage and need cooling first studies with a passive board (prototype)

pass. filter

power

next FEB

?

?

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FEB

. . .

vacuum

clockstartresetJTAG

converterboard

converterboard

converterboard

. . .

readout controller

board

driver board

FEB FEB

sensors

. . .

readout controller

board

FPC

Hardware is under test

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sensor1

TMS

TCK

TDITDO

sensor2TDO

last TDOis used

select(FPGA)

TDI

select(FPGA)

JTAG chain

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MIMOSA-26 protocol

and readout protocol

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sensor

line D0

8 bit word

multiplexer

line D1

8 bit word

data reduction

sensor readoutprotocol

sparsification

network protocol TrbNet (HADES network protocol)

data reduction and fake hit selection

scalable sensor protocol with unique sensor ID and time stamp architecture

sensor readout: line merging and first level data reduction

45

. . .

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lineD0

HDR

16 bit with serial output

Sensor Output Protocol

HEADER: fix bit pattern

Frame counter: 32 bit

Data Length: < 570 # words/frame

Colm. Address:

Row Address:< 9 hits/row+ neighbor pixel

Trailer: same as header

lineD1

F 1 D L CA RA 1 T…

HDR F 2 D L RA 0 RA 2 T…

46

continuous readout: zeros as place holder first data reduction

HDR words zeros HDR

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channel pattern

line D0

lineD1

output

enable

enable

enable

HDR …

…

F 1 D L L A

…HDR F 1 DL L AHDR F 2 DL

14 clock cycles

HDR F 2 D L RA

T

T

T T

create 16 bit words form serial channel input

Data handover

47

one 16 bit word/clock cycle

15 clock cycles

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enable

…HDR D L L A T

enable…

HDR D LF 1 L AHDR D LF 2 T TRA

F 1 F 2

First level data reduction

output

output

removed

RA

…

48

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• header/trailer: shows start and end of a frame

• scalable system • unique ID for sensor• unique ID for readout board

• time stamp: 32 bit frame counter• data length: gives the number of

words/frame• address of the hit pixel + neighbor

pixels

Header: new frame

data length for a frame< 570 word/frame

frame

time stamp: second 16 bit for frame counter

line address: in case of a hit

row address: in case of a hit> 9 hits/row

…trailer: unique sensor ID

data flow

49

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

data length 1 0 1 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

sensor-ID: 64 sensors/board board-ID: 64 boards/node parity 1 1 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

frame counter 1 0 0 1 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

frame counter 1 0 0 1 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

frame counter 1 0 0 1 1

HDR

datalength

32 bit framecounterortime stamp

Sensor readout protocol

50

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

ADDR line ovf 1 0 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

N N ADDR column 0 0 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

N N ADDR column 0 0 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

trigger counter 0 0 0 1 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

trigger counter 0 0 0 1 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

trigger counter 0 0 0 1 1

32 bit triggercounterortime stamp

Sensor readout protocol

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.

.max. 570 words

Sensor readout protocol

52

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

sensor-ID: 64 sensors/board board-ID: 64 boards/node parity 1 1 1

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backslides

53

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simulation results:MIMOSIS needs an output buffer of ~ 24 Kbit/frameMIMOSIS needs a readout frequency of ~ 800 MHz to transfer (serial) 24 kbit in 30µs Max. data rate: 800 Mbit/s Mean data rate: < 300 Mbit/s

[Byte]Byte

simulations of S. Seddiki- MIMOSA-26 protocol (16 bit)- 30 µs integration time- max. pileup ~5 coll/frame (Au-Au)- HADES beam fluctuations

Data Volume per Sensor

maxmean

107

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55

first data reduction (<300Mbit/s)

pixel array:± 1152 columns x ~256 rows

(18,4 µm pitch and 115,2 µs readout time)

JTAG Digitalinput Digital output

DACs

4 x memory banks

PLLTempprobe

Discritest Power

1152 discriminators

zero suppression logic

CDS

2 channels D0,D1+clock80 MHz

9 hits/ row

∑ 570 hits

multiplexer

2014 for SIS-100

Requirements for R/O 2 output channels/sensor

with 800 Mbit/s

readout frequency

400 MHz

8 bit word length

for 3 stations (400 sensors)

> 800 LVDS cables

30 µs

400 MHz

800 Mbit/s

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max 24 Gbit/station/s for p-Au @ 30GeV max. 12 Gbit/station/s for Au-Au @ 10A.GeV Higher data flow in p-Au since the δ electron hot spot in Au-Au limits the beam intensity

simulations of S. Seddikibased on MIMOSA-26 protocol

(with data reduction)

Data flow per station

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58