Inf3430 Xilinx Timing Constraints

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ISE Tool Flow Overview

ImplementationConstraints

Silicon

Design Entry

Synthesis

Delay SimulationFloor-Planning

MapPlace & Route

Translate

Simulation

Timing Analysis

SynthesisConstraints

™

Support Across The Board™

V9_2_2_0

Improving Performance Workshop

Fundamental Timing Constraints

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What Needs Constraining?

• Internal clock speed for one or more clocks• I/O speed• Logic using multi-cycle clocks• Pad to Pad timing• Pad Locations & Logic Locations

OUT1X

Y

Z<0:9>

OUT22 Levels of Logic

Clk & CE SpeedI/O Speed

Pin 2 Pin Speed

I/O Speed

PinLocations

PinLocations

LogicLocations

1 Level of Logic

QD QD

CLK


• PERIOD– Constrain all paths, sync element to sync element

• OFFSET– Constrain I/O paths, ie. pad to sync element, sync element to pad

(these are not covered by PERIOD constraints)• FROM-TO

– Specify Slow/Fast paths and Multi-Cycle paths • FROM-THRU-TO

– Constrain specific path thru logic between sync elements• TIG (Timing Ignore)

– Remove slow or static paths from Timing Analysis

Most Common Timing Constraints


Timing Constraint Precedence

• Within a particular source

Highest Priority TIG (Timing Ignores)

FROM-THRU-TO specs

FROM-TO specs

OFFSET specs

Lowest Priority PERIOD specs


Constraint Entry Methods

• Constraint Editor

– Preferred method

– Tools manage constraint syntax

• Text Editor

– User must manage syntax

• PACE

– Physical constraints only


IO TimingClock Timing

PAD to PAD Timing

Generated UCF Constraints:

PERIOD, OFFSET,

PAD TO PAD

Xilinx Constraints Editor (Old style)


New Constraints editor GUI (9.2 ->)


PERIOD Constraint

• PERIOD accounts for data path delay• PERIOD accounts for duty cycle – in this case 45/55• PERIOD accounts for first clock edge – in this case HIGH• PERIOD is specified with the clock period• PERIOD accounts for clock skew on global and local clocks• PERIOD accounts for clock phase including DCM phase and negative edge clocking

UCF Example:NET “CLKA" TNM_NET = “CLKA_Group";TIMESPEC "TS_CLKA_Group_Spec " = PERIOD “CLKA_Group" 10 ns HIGH 45%;

Period = 10 ns

HIGH = 45% LOW = 55%

= Constrained Data Path

BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

G

CLKB = Unconstrained Data Path


Logic LevelsOnly levels of logic, not Clock to Out and Setup

Updated!

Slack equation

Data path with Cross Probing

Links to Floorplanner or Synthesis Tool

(In Timing Analyzer)

Web link to graphicalpicture of

delay type! (In Timing Analyzer)

Clock names

and time of active

edge.Includes

Clock Phase

Basic element type is listed

Basic Period Report


OFFSET IN Constraint

• The OFFSET IN constraint covers paths from the input pads to synchronous elements taking clock delay into account

• The OFFSET IN constraint does NOT optimize paths clocked by internally generated clocks (including DCM’s)

• OFFSET IN only covers PAD to registered element data paths• OFFSET IN does not constrain the delay or skew of clock path itself


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



OFFSET IN Constraint

• OFFSET IN is used to constrain input data paths• OFFSET IN clock is specified to the clock PAD• OFFSET IN clock can not be an internal clock – DCM output• OFFSET IN only covers PAD to registered element data paths• OFFSET IN does not constrain the delay or skew of clock path itself


OFFSET IN BEFORE Constraint

• OFFSET IN BEFORE Is time data is VALID prior to capture clock• VALID Duration is time data remains VALID – data eye width• VALID is required for hold time analysis and error reporting• Without explicit VALID, implied VALID = OFFSET• In this example, implied VALID is not correct• Without VALID, hold time can be reported with TRCE –fastpaths• -fastpaths reports delays only and does not check for hold errors

ExternalClock

Valid DataExternalData

OFFSET IN BEFORE

VALID

FPGA

REG

D Q

CLK

TClk

TData

ExternalClock

ExternalData

TSU / TH

ø

ø


OFFSET IN Report Example

Clock name

and time of active

edge

Slack equation

Data Path Delay

Clock Path Delay


System Synchronous Interface

• One common system clock for both source and destination• Board level skew and data path delays limits performance• Typically Single Data Rate (SDR) applications

Source Device FPGA

REG

D Q

CLK

TSrcClk TDestClk

TCKO

TData TData

TDataTrace

System Clock

REG

D Q

CLK

TSU/ TH

DCM


System Synchronous Inputs

• This example shows Data Valid Window less than PERIOD• Start of data is 9 ns before the capture clock edge• Data remains VALID for 8 ns

OFFSET IN 9 ns VALID 8 ns BEFORE SysClk;

SysClk

Valid DataDataIn

OFFSET IN BEFORE = 9 ns

VALID = 8 ns

PERIOD = 10 ns

TransmitEdge

CaptureEdge


System Synchronous Data Sheet


OFFSET OUT Constraint

• The OFFSET OUT constraint covers paths from synchronous elements to output pads taking clock delay into account

• The OFFSET OUT constraint does NOT optimize paths clocked by internally generated clocks


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



OFFSET OUT Constraint

• Defines maximum time in which data can leave the chip• Used for destination device setup time verification• OFFSET OUT clock is specified to the clock PAD• OFFSET OUT clock can not be an internal clock• Best used for system synchronous interfaces

OFFSET = OUT 10 ns AFTER "SYS_Clk";


OFFSET OUT Report

Slack equation

Clock Path Delay

Clock name

and time of active

edge

Data Path Delay


Constraining Specific Delays

• A FROM-TO constraint defines the delay between two groups of logic– Logic paths typically start and stop at pads, registers, latches, RAM,

multipliers, CPUs and high speed IOs (MGT)• It is used to constrain the following types of paths (more details later):

– Multi-cycle paths --If not expected to meeting the original single cycle clock period

– Data paths between unrelated clocks– False Paths --If paths/net that are known not to have a timing

requirement• No HOLD violation check is done for FROM:TO paths


Basic FROM-TO Examples

• A FROM-TO constraint defines the delay between two groups of logic– Logic paths typically start and stop at pads, registers, latches, RAM, multipliers,

CPUs and high speed IOs (MGT/GTP)

• UCF TIMESPEC command using default keywords– TIMESPEC TS_C2S=FROM FFS TO FFS 30;– TIMESPEC TS_P2S=FROM PADS TO FFS 25;– TIMESPEC TS_P2P=FROM PADS TO PADS 26;– TIMESPEC TS_C2P=FROM FFS TO PADS 9;

TS_C2P

TS_C2STS_P2S

TS_P2P

OUT1QD QD

CLK

OUT2


FROM:TO Report

Slack equation

Data Path Delay

Requirement is < twice TS_clk (40ns)


PAD to PAD Constraint

• Purely combinatorial delay paths start and end at I/O pads and are often left unconstrained by users

• Placing a FROM:TO constraint on pads-to-pads is necessary if there is a timing requirement– TIMESPEC TS_P2P = FROM PADS TO PADS 15 ns;


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



PAD to PAD Report

Slack equation

Data Path Delay

Source and Destination elements are PADS


Pre-Defined Groups

• Timing constraints are applied to logic paths• Logic paths typically start and stop at pads, and synchronous elements• The tool recognizes the following keywords to define endpoints or time groups:

PADS All I/O padsFFS All flip-flopsLATCHES All latchesRAMS All RAM elementsBRAMS_PORTA All Port A Dual Block RAM elementsBRAMS_PORTB All Port B Dual Block RAM elements HSIOS All High Speed I/O elements (RocketI/O)CPUS All PowerPC elementsMULTS All Multiplier elementsDSPS All DSP48 and derivatives (DSP48A, DSP48E)

• Keywords can be used globally, and to create design sub-groups


Using TNM_NET to create Groups on Nets

NET clock TNM_NET=clk_group;• TNM_NET is equivalent to TNM on a net except for pad nets.• If you place a TNM on a pad net, it will trace backwards to the pad and not

trace forward through the buffer to the next synchronous element. TNM_NET was created for this purpose.

• If you place a TNM_NET on a pad net, it will trace through the buffer to the next synchronous element.

• TNM_NET is extremely useful for synthesis designs. The ports are directly connected to pads.

• TNM_NET can be used in UCF or NCF only.


Auto-Related DCM Paths

• PERIOD constraint applied to CLKIN• CLK2X Period automatically defined as related to CLK1X• Cross-clock paths are automatically analyzed

FROM-TO constraints are not required !


ISE Tool Flow Review

ImplementationConstraints

Silicon

Design Entry

Synthesis

Delay SimulationFloor-Planning

MapPlace & Route

Translate

Simulation

Timing Analysis

SynthesisConstraints


• Pipeline• Reduce combinatorial delays• Register block outputs• Register duplications

Source Code Changes to Improve Timing

In general, source code changes have greater effect in improving performance than software switches

In general, source code changes have greater effect in improving performance than software switches


• MAP -timing (Use Timing-Driven Packing and Placement Algorithm)

– MAP runs normally, then examines timing• If timing is not met, MAP tries to re-pack and place critical logic in order to

meet constraints• Runtime for MAP increases but this should be offset by a reduction in the

PAR runtime• Greatest benefit is seen in high density designs with unrelated logic packing

– Typical performance improvement of 5 percent is achievable

– Maximum performance improvement of 30 percent is possible

Timing-Driven MAP


• Other options used with -timing option– Set -ol overall effort level {std | med | high}– Extra effort -xe {n | c}– Register duplication: -register_duplication

• Allows MAP to duplicate registers to improve timing

– Starting placer cost table: -t {1-100}

Timing-Driven MAP Options


Timing-Driven MAP Options – GUI

Right click Implement Design and pick Properties

Pick Map Properties

PickAdvanced


Timing-Driven MAP Options – GUI

Enable advanced placement options

Check Timing Driven

Packing and Placement

Set High to enable Extra

Effort

AdvancedOptions enabled


Timing Constraints

• In order to enable timing optimization you must set “Optimization Goal” to “Speed” in XST synthesis options

Documents

Inf3430 Xilinx Timing Constraints