IL2207 SoC Architecture Course Jan – March 2010, KTH Zhonghai Lu / Axel Jantsch [email protected]

IL2207SoC Architecture Course

Jan – March 2010, KTH

Zhonghai Lu / Axel Jantsch

[email protected]

April 21, 2023 SoC Architecture 2

Course Information Course staff

Responsible: Dr. Zhonghai Lu, [email protected] Examiner: Prof. Axel Jantsch, [email protected] Assistant: Lic. Jun Zhu, [email protected]

13 Lectures, 4 Tutorials, 3 Labs Home page: www.ict.kth.se/courses/IL2207/1001 Course Material

Dally, Towles: Principles and Practices of Interconnection Networks

Distributed Materials and slides

Advanced-level course, more demanding


Lecture Overview

L1: Introduction L2: Buses and Arbitration (Dally: 22, 18) L3: Shared Memory Multiprocessors L4: Cache Coherency Protocols L5: Memory Consistency L6: Introduction to Network-on-Chip, Topologies (Dally: 1, 2, 3, 4, 5) L7: Routing Algorithms and Mechanics (Dally: 8, 9, 10, 11) L8: Flow Control (Dally: 12, 13) L9: Deadlock and Livelock (Dally: 12, 13, 14) L10: Router Architecture and Network Interface (Dally: 16, 17, 20) L11: Network Performance and Analysis (Dally: 23) L12: Quality of Service in Communication Networks (Dally: 15) L13: Course Summary


Tutorial Overview

T1: Bus, arbitration and cache coherency After Lecture 5, on Jan. 28 By Prof. Jantsch

T2: Memory consistency and network topology After Lecture 7, on Feb. 4 By Dr. Lu

T3: Interconnection networks (routing, flow control, deadlock etc.) After Lecture 10, on Feb. 15 By Dr. Lu

T4: Router architecture, QoS and performance analysis After Lecture 13, on March. 1. By Prof. Jantsch


Lab Overview

Laboratory 1: Uniprocessor SoC Design with Altera Laboratory 2: Multiprocessor SoC Design with Altera Laboratory 3: Wormhole Networks

Each lab has 4 sessions: a, b, c, d. Students work in groups of max. 2 Good preparation is required.


Course Requirements

To pass the course the student has to fulfill the following requirements:

Pass the final exam. The grade for the exam will be the grade of the course. Final exam: March 16, 2010, 14:00-18:00,

* Register the exam in Daisy 2 weeks before the

exam date in order to guarantee a seat ! Complete all labs Attend lectures, tutorials and labs

Observations in System Design


Advances in Integration

If automobile speed had increased similarly over the same period, we could now drive from Stockholm to Shanghai in about 23 seconds.

Intel 4004(1971)

108 KHz2,300 transistors

Intel Pentium 4 (2000)

1.5 GHz42 million transitors

Advances in Integration - 2007

Intel Terflop Chip 2007

http://techresearch.intel.com/articles/Tera-Scale/1449.htm


Growing Design-Productivity GapDesign Productivity Crisis

Potential Design Complexity and Designer Productivity

Lo

gic

Tra

nsi

sto

r p

er C

hip

( M

)

Pro

du

ctivity ( K

) Tran

s./Staff – M

o.

19811983

19851987

19891991

19931995

19971999

20012003

20052007

2009

100,000,000

0.01

0.1

1

10

100

1,000

10,000

Equivalent Added Complexity

1,000

100

10

1

0.1

0.01

0.001

10,000

21% / yr compounded

Productivity Growth Rate

xxx

xxx

x x

58% / yr c

ompounded

Complexity Growth Rate

Logic Tr. / Chip

Tr. / S.M.

20012003

20052007

20092011

20132015

10,000

1,000

100

Den

sity

(K

gat

es / m

m2)

AS

IC c

lock

(M

Hz)

Clock Gates

Moore’s Law: Standard cell density and speed

Source: (SRC 1997)

Designs do not only get more complex, but also much more expensive!


The Role of the Market!

Source: Smith 1997


Moore’s Law drives the development of System-in-Chip Architectures

Yesterday’s SOC

Processor

Memory

RTL function 1

RTL function 2

RTL function 3

RTL I/O

Today’s SOC

Ctl Proc

Mem

DSP RTL I/O

RTL RTL

Mem

RTL RTL

RTL RTL RTL RTL RTL RTL

RTL

RTL

RTL

RTL

RTL

RTL

The growing number of transistors on an SOC drives the trend towards more RTL blocks on the chip

Source: Leibson (DAC2004)


Verification Costs

The percentage of the verification costs of the total design costs is continuously increasing (at present 50-70% for large designs)


$10M design cost, $15 manf. cost, 5% premium for programmability

0

20

40

60

80

100

120

1 2 3 4 5 6 7

100 000

1 000 000

System designs per chip design

To

tal

pe

r u

nit

co

st

SOC Flexibility = Per-Unit Cost Reduction (Model: 100K and 1M system volumes)

Platforms reduce Costs

Low-endstill camera

High-endstill camera

Video camcorder

One Chip Many System Designs

Source: Leibson 2004


Platform Example: Nexperia


Nexperia Instance: Viper


Arm based MPSoC Platform

Texas Instruments OMAP

A SOC Platform

based on

Peter Cumming: ”The TI OMAP Platform Approach to SOC”


The OMAP platform

OMAP products are combinations of hardware and software allowing mutimedia capabilities to be included in 2.5G and 3G wireless handsets and PDAs

Critical design paramters are: Performance, Power, Cost and Time-to-Market

First Approach: ”Opportunistic Reuse” No planned reuse, but try to reuse whenever possible

Second Approach: ”Structured Approach” Systematic Reuse, SoC Platform


What is a platform?

OMAP defines a platform as ”a packaged capability used in subsequent stages of the

development to reduce development costs” Platforms have the following characteristics:

Between silicon and systems many platforms may be developed and used in subsequent stages of the development

Platforms are valuable due to the notion of reuse (good for economy)

They include hardware, software, assemblies and tools!


Examples for platforms

Transistor and ASIC libraries are the lowest hardware platforms

Instruction Set Architecture and associated Assembly Language Tools are the lowest levels in Software

These well-understood levels are used by other OMAP platforms


OMAP: Hierarchy of Platforms

OMAP uses platforms on different levels This is a precondition for reuse

Silicon Technology

ASIC Library & Tools

SoC Platform

Appl. Platform

RefDesign

Reuse

OMAP Infrastructure

OMAP Products

Application Specific


SoC Platform

The SoC platform consists of A library of hardware components An architecture for their interconnection

The Application Platform (the OMAP product) Processor and Peripherals Low-Level Software (Drivers) Development Environment

The System Platform The platform includes the code that controls all aspects of the

system from device driver to system interface TI has a reference design group in order to understand the new

demands for OMAP


OMAP Products

The OMAP product range consists of several families of devices for different markets, e.g. Application processors for 3G: OMAP 1510 and

1610 Application processors for 2.5G: OMAP 710 and

730


OMAP 1510

OMAP 1510 is based on Enhanced ARM 925 core (RISC processor) TI C55x core DMA, SRAM, Busses, Peripherals


Current OMAP platform for Wireless Handset & PDA

OMAP™ 3 architecture combines mobile entertainment with high performance productivity applications (Source: Texas Instruments)


Strength of the OMAP concept The main strength of the OMAP concept is that several actors can

make extensive Reuse of development efforts at several levels of the design process

Actors: Mobile Device Manufacturers Software Developers TI’s internal Development Teams

Levels: Common Hardware and Software Interfaces Common Development Environment Single Low-Level Software Framework (Code can be used for several

products) Single SoC Platform

OMAPI is an interface standard for OMAP founded by TI and ST


OAMP Architecture

The OMAP architectute consisting of general purpose processor and DSP has been chosen because of the application area Need for Performance Energy and Area Constraints Two Main Tasks: User Interface and Signal

Processing Flexibility and Reuse


Requirements on Software Platform

Hardware architecture requires a matching software approach Well-defined Set of Application Programming

Interfaces in the high-level OS running on the general purpose processor

System Software that links General Purpose Applications to DSP components

Well-defined Standard for DSP Components (TMS320 Algorithm Standard or eXpressDSP)


Summary

The OMAP platform Covers a wide range of products allowing to

reuse Hardware and Software Hardware Architecture adopted to Application

Area Software Architecture using features of Hardware

Architecture Efficient SOC Platform with Definitions for

Hardware and Software Reuse

Emerging Architectures


System-on-Chip Architectures A system-on-chip architecture integrates several

heterogeneous components on a single chip

Micro-controller

FPGA

DSPCustom

Hardware

Analog-Digital

Digital-Analog

Memory

CommunicationStructure


A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead


System on a chip

System-on-Chip Architecture:A bus-based SoC

Memory DSPMicro-

processor

CustomLogic

I/O


System-on-Chip Architecture: Network-on-Chip

The resources are connected to the network via network interfaces

The topology of the network and the capability of the switches and communication channels determines the capacity of the network

PE1

PE2

PE3

MEM

Switch

Channel

NI

NI

NI

NI

Network Interface

Resource

ASIC Technologies


What is an ASIC?

ASIC = Application Specific Integrated Circuit An ASIC is an integrated circuit for a specifc

application and (generally) produced in relatively small volumes.

An ASIC-technology helps to shorten the design time by providing a semi-fabricated integrated circuit


ASIC families

Programmable Logic Programmable Logic Device

(PLD) Field Programmable Gate

Array

ASIC Standard Cell Gate Array

The term ASIC is often reserved for circuits that are fabricated in a silicon foundry, while circuits that can be programmed at the customer’s site are called Programmable Logic.

The term full custom is reserved for circuits where all silicon layers can be optimized. This implies a long design process and thus full custom is mainly used for high-volume high-end circuits.


Standard Cell

Standard cells are often referred as Cell-Based Integrated Circuits (CBIC)

All mask layers are customized The standard cell library defines

logic elements of varying complexity: SSI, MSI logic, data path blocks, memories and system-level blocks.


Standard Cells

Cells are configured in rows and have constant height and variable width

Each cell is optimized for an efficient implementation


Gate Array

A gate array chip contains prefabricated adjacent rows of PMOS and NMOS transistors

The gate array is configured by the interconnect structure


Channeled Gate Array

Only the interconnect is customized

The interconnect uses spaces between rows of base cells


Channelless Gate Array(Sea of Gates)

Only the interconnect is customized

Cells are connected via unused transistors


Field Programmable Gate Arrays

None of the layers are customized

Basic logic cells and interconnect can be programmed

Basic cells can be SRAM based, Flash Memory based or fuse-based (one time programmable)


Programmable Logic Device

• No customized mask layers or logic cells

• A single large block of interconnects

• Macrocells consist of programmable array logic followed by a flip-flop or latch


Comparison FPGA, Gate Array, Standard Cell

Initial Cost Cost per part Performance Fabrication Time

FPGA Low High Low Short

Gate Array

Standard Cell High Low High Long


Design Trade-Offs

Design Time

Performance

Microprocessor

ProgrammableLogic

Gate Array

Standard Cell

Full Custom

Challenges for System Design


Challenge for System Design!

How to design a system-on-chip?

Specification Design productivity increases

with the level of abstraction The task of functional verification

is very difficult at low abstraction levels

Idea (Specification)

Design

Product (Implementation)

abstract

detailed

Abstraction Gap Implementation

Efficient implementations require to exploit the low-level features of the target architecture


SoC Design The continuous progress in silicon process technology allows

to increase more and more functionality on a single chip => Systems on a chip become reality

Market-driven forces: Shorter product design schedules and life spans Products have to confirm to standards The design has to be right from the start. An

implementation error means heavy loss of money or product death

Large designs are integrated into a single chip

The SoC design process must address these driving forces


The Design Process

Design Space

Design Step

Intermediate Model

Abs

trac

tion

Leve

l

Implementation

Design Specification

Abs

trac

tion

Gap


Requirements on Design Flow

Design Entry Well-defined abstract specification model Efficient verification methodology

Design Refinement Well-defined models at all abstraction levels Well-defined refinement steps Verification at all levels


Requirements on Design Flow

Implementation Mapping Efficient platform architecture with well-defined

API Mapping detailed implementation model to API

services Tool Support

Verification Design Refinement Implementation Mapping Estimation of Properties


Design Process A design specification has to be mapped on an

architecture

Architecture Specification

DesignProcess

DesignImplementation

Design Specification


Design Process(Uniprocessor)

A program is compiled to assembler code for a chosen uniprocessor and operative system

Uniprocessor+

Operating Syst.

Compilation

ExecutableCode

Program(Parallel Tasks)


Design Process

The design process for a SoC applications is a very complex task Many components work in parallel and communicate with

each other A task can be mapped on different components The overhead for communication depends on how tasks

are located The designer has to choose an appropriate SoC

architecture, since different architectures have different strength and weaknesses


Design Process(System-On-Chip)

A specification shall be mapped onto a SOC-Architecture with several heterogeneous components

SoC Arch.with severalcomponents

Partitioning, Mapping, Compilation

Specification(Parallel Tasks)

CodeProcessor X

CodeProcessor Y

HW Descr.Comp. A

HW Descr.Comp. B


Platform-Based Design

Micro-controller

FPGA

DSPCustom

Hardware

Analog-Digital

Digital-Analog

Memory



Hardware Platform

Hardware Abstraction

Programmers Model

The idea of a platform is to simplify the design process


System-on-Chip Platform

Layered Concept allows to Change the physical

architecture of the SoC without affecting the application

Add new services on top of existing architecture

Changes in one layer affect only the layer itself and its interfaces

PhysicalWires, Clocks

TransportPackets

TransactionMessages, Load/Store

APIServices with Guarantees

Concurrency


Embedded Systems have to cope with Parallelism

Provides an alternative to faster clock for performance Applies at all levels of system design Is essential within embedded system design, where the

system has to react to several inputs from the environment

EmbeddedSystem

EmbeddedSystem

A

B D

C

Source

Sink

Reactive Environment


System-on-Chip:A Parallel Architectures

A parallel computer is a collection of processing elements that cooperate to solve large problems fast Resources

Processing capacity of the components Distributed and/or global memory

Data access, Communication and Synchronization Communication protocol Communication capacity Communication abstraction and primitives

Objectives Performance and Scalability


Components in a Parallel SoC

Microprocessor cores or DSP:s are cheap and optimized for their application area

Customizable hardware can be used to guarantee a high performance for a special task

Often each parallel task does not need a tremendous processing power

It is important, how the parallel tasks can be mapped onto the SoC so that the parallel nature of the system can be fully exploited


Communication PrimitivesSystem on Chip

There are two main paradigms Shared Memory Message Passing


Communication PrimitivesSystem on Chip

Shared memory is typical for bus-systems, since naturally a memory is connected to the bus that all processing entities can access

System on a chip

Memory DSPMicro-

processor

CustomLogic

(ASIC)I/O


Communication PrimitivesNetwork on Chip

Message passing looks very natural for networks-on-chip, since a shared memory is usually not available

However, locality is important, since otherwise huge amounts of data have to be sent over a network

PE1

PE2

PE3

MEM

Switch

Channel

NI

NI

NI

NI

Network Interface


Message Passing

Processes send messages between processes A message has a sender and and receiver(s) Primitives are Send and Receive Programming does not include a shared memory

P1 P2

Message


Programming Model for Message Passing

Natural Model for NoCs: Communicating Finite State Machines

Communication is done by message passing (languages like SDL are suitable)

A

B

C

D

Process

SendMessage

Receive Message (Wait for message)


Implementation of a Message Passing Programming Model

Mem P1 P2

uses Hardware Drivers

Hardware

Operating Systemuses Low-Level Comm. Primitives

Compiled Programuses High-Level Comm. Primitives

Source Code

here Shared Memory Comm.(can also be NoC)

A programming model based on message passing can still be implemented by a shared memory architecture

Each layer has to use the primitives that are provided by their lower layer neighbour


Summary

System-on-Chips are heterogeneous and parallel

A good communication is the key to an efficient parallel architecture

In the course we will mainly focus on comunnication architectures

Buses Network-on-chip

Documents

IL2207 SoC Architecture Course Jan – March 2010, KTH Zhonghai Lu / Axel Jantsch [email protected]