Hspice Lab Manual

KAVAR NILESH 1305042006 VLSI SYSTEM DESIGN Page 1

EXPERIMENT NO. 1

Introduction to VLSI-design lab and tool


INTRODUCTION:

This experiment is outlines how to run HSPICE in Windows then delves into

the details of creating net lists, simulating them, and using Awaves to plot the results.

HSPICE is just a program that takes in a net list (a simple text file), containing a

circuit description and analysis options, and outputs the analysis it has done on that

circuit. An HSPICE net list typically has a .sp extension, for example circuit.sp.

Although HSPICE produces many output files, the only one that you will need to look

at is the file with a .lis extension, for example circuit. Is. This file contains all of the

important results from the HSPICE analysisoperating points, measurement results, error messages everything is in this file. Typically after simulating a circuit, its best to check this file first to ensure there were no errors in your netlist.

The other files that HSPICE generates are used by Avanwaves or Awaves for

short. Awaves is a program that allows you to graphically plot the results of the

analysis that HSPICE did. You have to explicitly tell HSPICE to generate the extra

files that Awaves needs, and well show you how to do that in this tutorial. Generally, when you run Awaves, youll open the .sp of the circuit you analyzed. Awaves will automatically find the analysis files that it needs and allow you to plot the results of

the analysis that you specified in the netlist.

RUNNING HSPICE:

Were going to go through a sample HSPICE simulation and analysis in Awaves in order to teach you how to run these programs.

Start Notepad. You can do this either by clicking Start -> Run, typing Notepad, and hitting Enter.Or, you can click Start -> Programs -> Accessories ->Notepad.

Write the following program in hspice for given circuit:

HSPICE CODE:

vsvsgnd PWL(0s 0V 5ms 0V 5.001ms 5V 10ms 5V)

r1vsvo 1k

c1vognd 1uF

.tran 0.01ms 10ms

.option post=2

.end

Save this file into a folder called Tutorial. Name it rc circuit.sp. Note: To ensure the filename has a .sp extension, be sure to select All Files in the Save as type listbox. You can put the filename in quotations if you want to be extra careful.


Click Start -> Programs -> HSPICE V-2004.03-SP1 ->Hspui V-2004.03-SP1. This is called the HSPICE UI (HSPUI for short), a graphical user interface to HSPICE. Although you can run HSPICE and Awaves

individually, HPSPUI puts HSPICE, Awaves, your netlist, and the HSPICE

outputin a convenient panel for easy access.

Click Simulate to simulate the circuit. HSPUI will open HSPICE for you and run your netlist through HSPICE, producing rccircuit.lis and other output files

used by Awaves.

Click Edit LL to view the output from HSPICE. This file contains information about the analysis done by HSPICE. Typically, you would look here for

measurement results, operating points, and error messages. You should see no

error messages at this time. If you do, check to make sure you copied the

netlist. Once youve verified there are no error messages, close the output file.

Click Avanwaves to start Awaves. Youll see that HSPUI opens your circuit in Awaves and you can immediately begin plotting data. Well cover Awaves through some examples later, but you can see the results of your analysis here

by selecting Transient: ee105 spice tutorial example 1 - simple rc circuit in the

Results Browser and double-clicking vs and vo to plot them in the graph. You

may have been able to guess from the netlist, but youll see that vs is a step function input and vo is the output taken across a capacitor when the step

function is applied as the input.

OUTPUT WAVEFORM:


EXAMPLE 1. DC ANALYSIS OF A DIODE:

HSPICE CODE:

KAVAR NILESH_PRACTICAL_RC_CRICUIT

.model tut_diode d (is=1e-14 vj=0.6 rs=10)

vs vs gnd 5V

rs vs vd 5k

d1 vd gnd tut_diode

.dc vs 0V 5V 0.01V

.option post=2

.end

OUTPUT WAVEFORM:

Another type of analysis we can do is DC analysis. DC analysis allows us to measure

values in our circuit as we sweep a voltage. For example, lets look again at our diode circuit. Instead of looking at vd for vsat just 5 V, maybe we want to sweep vs from 0

V to 5 V and see how vd changes as a result. we are sweeping vs from 0 V to 5 V in

steps of 0.01 V.

INCLUDING ANOTHER FILE:

During the course of the semester, youll often have to use models that we provide on

the course website. Instead of copying and pasting the models, you can just include

the model file

in your circuit. To do this, place the model file in the same directory as your netlist

(for example, circuit.sp and 2N4401.mod). Then, in your netlist, include the following

line:

.inc In this case, we would use 2N4401.mod for the filename.


EXAMPLE: 2 AC ANALYSES OF A HIGH-PASS FILTER:

HSPICE CODE:

KAVAR NILESH_PRACTICAL_RC_CRICUIT

vs vs gnd ac 1V

c1 vs vo 1nF

r1 vo gnd 1k

.ac dec 500 100 1G

.option post=2

.end

Lets take a look at a basic RC high-pass filter, First lets look at how the netlist has changed once again. Look at Line 2. Although this looks extremely similar to all of

our other voltage definitions, it has one extra parameter specified before the value: ac.

This tells HSPICE that the AC analysis should be done by varying the frequency of

this source. If you try to do an AC analysis of a circuit without any AC sources

specified, HSPICE will give you an error.

Now look at the new analysis statement on Line 5. The .ac command tells HSPICE to

do an AC analysis by sweeping the frequency of the AC source as you specify. The

first parameter passed to this command, in our case dec, tells HSPICE whether to do a

linear (lin) sweep, a sweep by octaves (oct), or a sweep by decades (dec). In this class,

well be using dec for all of our AC analyses. The second parameter tells HSPICE

how many sample points to take per decade. The third parameter is the starting

frequency of the sweep, and the fourth parameter is the ending frequency of the

sweep. In this case, were taking 500 points per decade from f = 100 Hz to f = 1 GHz.

Simulate this circuit and open it in Awaves. Youll notice that in the Results Browser

you can plot real and imaginary components, magnitudes, and phases of voltages and

currents. Youll also notice that your x-axis has been conveniently set to

frequency in Hertz. Lets make a Bode plot (magnitude and phase) of this high-pass filter to confirm that it behaves as we expect

TRANSFER FUNCTION ANALYSIS:

Lets try to find the voltage gain (output over input) for the circuit in Figure 9. Since this a simple resistive network, you can hand-calculate the answer and compare it to

the result you get in HSPICE. Ive used more convention notation in the diagram this time and havent labelled the nodes. At this point, you should be able to recognize


what is going on without those labels. Figure 10 shows the net list for this circuit

diagram.

The only new feature here is the analysis statement on Line 11, which is a .tf

statement, short for transfer function. This calculates the DC gain, input resistance,

and output resistance between the voltage node specified first (the output) and the

voltage source specified second (the input).

We dont need the .option post=2 statement since we will not be using Awaves for this analysis. Simulate the circuit in HSPICE and open the output file. Look for a line

that says small-signal transfer characteristics. Underneath that, you should see values for v(vo)/vs, or the gain from vs to vo, the input resistance at vs, and the output

resistance at vo. In this case, the gain is 109.8628 m _ 0.110. If you were to calculate

the voltage at node vo by hand, you would get the same result.

THE .MEASURE COMMAND:

The .measure command is used to measure almost any parameter in your circuit under

some specified conditions. For example, it can be used to measure rise time, fall

time, delay, maxima and minima, etc. Here we will cover just one use of the

.measure command.

TRIG/TARG One use of the .measure command involves specifying a trigger and a

target (TRIG and TARG, respectively). A trigger tells the command when to start

measuring, and the target tells the command when to stop measuring. The command

will then report the value you want to measure at the trigger condition, target

condition, and the difference between its

values under those conditions. This is best illustrated through an example. Consider

the RC circuit in Figure 3. Lets say we want to measure the rise time of this RC circuit. First, we need to define the rise time metriclets say its the time it takes for voto go from 10 % to 90 % of its final value (i.e. from 0.5 V to 4.5 V). Now, lets take a look at the netlist that will perform this measurement, shown in Figure 12. Pay close

attention to line 6, which contains the .measure command. The structure of the

command is as follows (note that the plus signs allow you to continue a command on

the next line and are not necessary):

.measure

+ trig val==

+ targval==


The first argument specifies what analysis statement to associate the measurement

with. For example, if measuring time the first argument should be tran. If measuring

frequency, it should be ac, and if voltage, dc. The second argument is simply a name

for your measurement. In the example for computing rise time, I use the name trise

for my measurement. Now you must specify the trigger and target, which have

identical structure. For each, you must specify what node you want to trigger/target

on, the value it needs to equal at the time of the trigger/target, and how many

rises/falls/crosses have occurred prior to the node reaching that value. You should

understand the concept of rising and falling, i.e. a signal going from low to high or

high to low. A cross is simply the sum of rises and falls.

Lets look at our example again. I am triggering when v(vo), the voltage at the output node, is equal to 0.5 V, or 10 % of its final value. I want it to measure this value on

the first rise, so I specify rise=1. I am targeting when v(vo) is equal to 4.5 V, or 90 %

of its final value. Again, I want the value on the first rise, so I again specify that

rise=1. Thats all there is to it. If you simulate this netlist in HSPICE and look at the output, under a line labeled transient analysis you should see values for trise, trig, and targ, where trise is just targ - trig.

One issue to watch out for is that you cannot set your trigger to at zero. If you want to

trigger at zero, you can approximate the measurement by using a very small, but non-

zero, trigger value. For example, I could trigger on the value 1n.

1 EE105 SPICE Tutorial Example 7 - Computing rise time

2 vs vs gnd PWL (0s 0V 5ms 0V 5.001ms 5V 10ms 5V)

3 r1 vs vo 1k

4 c1 vo gnd 1uF

5 .tran 0.01ms 10ms

6 .measure tran trise trig v(vo) val=0.5 rise=1 targ v(vo) val=4.5 rise=1

7 .end

SYNTAX REFERENCE:

Any bracketed labels must be replaced entirely (i.e. if you want a value of 5 V, you

should replace with 5V).

Independent voltage source: v

Independent current source: i

Voltage-controlled voltage source: E

Current-controlled voltage source: H

Voltage-controlled current source: G

Current-controlled current source: F


Sinusoidal source (used as a ): sin()

Square wave source (used as a ): pulse()

Piece-wise linear source (used as a ): pwl( ...)

Resistor: r

Capacitor: c

Inductor: l

Model (type can be nmos, pmos, NPN, PNP, or D for diode): .model ()

MOSFET: m

BJT: q

Diode: d

AC analysis: .ac

DC analysis: .dc

Nested DC analysis (source1 is swept, source2 is stepped) .dc

Transient analysis: .tran

TF analysis: .tfv()

PZ analysis: .pzv()

CONCLUSION:

Date: Signature of Faculty:

__/__/____


EXPERIMENT -02

To Plot input-output characteristic for nMOS and analyse the effect

of Vsb on threshold voltage


TRANSISTOR OPERATION:

A cross sectional view of an NMOS transistor is shown in Figure 4-3. When the

potential difference between the source (S) and drain (D) is small (~ 0V), and a large

potential (> VT0) is applied between the gate (G) and source, the transistor will be

operating in the linear or ohmic region. The positive gate potential causes electrons to

gather below the surface of the substrate near the gate in a process called inversion.

This region of mobile charge forms a channel between the source and drain. The

amount of charge is a function of the gate capacitance (Cox) and the gate-to-source

overdrive voltage.

CROSS-SECTIONAL VIEW OF AN NMOS TRANSISTOR:

The term VT0 is the threshold voltage. When the gate-to-source voltage (VGS),

exceeds this value, an inversion region is formed. Before reaching the inversion

region, as the gate-to-source voltage is increased, the transistor passes through the

accumulation region where holes are repelled from and electrons are attracted to the

substrate region under the gate. Immediately before inversion, the transistor reaches

the depletion region (weak-inversion) when the gate-to-source voltage is

approximately equal to the threshold voltage. In this region a very small current

flows.

In the linear region, the MOSFET acts as a voltage-controlled resistor. Resistance is

determined by VGS, transistor size, and process parameters.

When the drain-to-source voltage (VDS) is increased, the quantity and distribution of

mobile charge carriers becomes a function of VDS as well. Now the total charge is

given by:

As VDS increases, eventually the drain current saturates. That is, an increase in VDS

does not cause an increase in current. The saturation voltage depends on VGS and is

given by VDS(sat) = VGS VT. The equation for the drain current becomes:


When VGS is less than the threshold voltage, the channel also conducts current. This

region of operation is called weak-inversion or sub-threshold and is characterized by

an exponential relationship between VGS and ID.

CIRCUIT DIAGRAM:

HSPICE CODE & SIMULATION:

//*V-I CHARACTERISTIC OF nMOS transistor:*//

HSPICE CODE: kavar_nilesh_practical_2

.inc 'cmosedu_models.txt'

vgs G 0 5

vds D 0 5

vsb 0 S 5

*V-I CHARACTERISTICS CONSIDERING Vsb

m1 D G 0 S N_1u l=1u w=10u

.dc vgs 0 5 0.1 vsb 0 5 1

.option nmod post=2

.probe i(m1)

.end


SIMULATION RESULT:

CONCLUSION:


__/__/____


EXPERIMENT -03

Plot input-output characteristic for p-mos and analyse the effect of

vsb on threshold voltage


TRANSISTOR OPERATION:

In addition to an n-channel MOSFET device (i.e., NMOS), we can build p-channel

MOSFET (i.e., PMOS) device.

The structure of a PMOS device is essentially the same as an NMOS transistor, except

that wherever there was n-type Silicon there is now p-type Siliconand wherever

there was p-type Silicon there is now n-type Silicon!

Specifically, the PMOS channel is part of a n-type substrate lying between two

heavily doped p+ wells beneath the source and drain electrodes

The operation of a PMOS transistor is in many ways similar to that of the NMOS

device, but in many ways they are also quite different!

For example, for a PMOS device we find:

To create an inversion layer in the n-type substrate, we must attract holes to the gate electrode.

As a result, a p-type channel will be induced, connecting the p+ wells at the drain and the source.

However, to attract holes toward the gate, the voltage vGS must be sufficiently negative! The threshold voltageVt is thus a negative value, so that a channel is

induced only if GS t v


HSPICE CODE & SIMULATION:

HSPICE CODE: kavar_nilesh_practical_3


vgs 1 0 0

vds 2 0 0

m1 2 1 0 0 P_1u l=1u w=10u

.dc vds -1.8 0 0.05 vgs -1.8 0 0.3

.option nomod post=2

.probe i(m1)

.end

SIMULATION OUTPUT:

CONCLUSION:


__/__/____


EXPERIMENT 04

Design inverter with resistive load

1. Find threshold voltage, noise margin and delay times

2. Plot transfer characteristics for different values of

W/L& resistors


RESISTIVE-LOAD INVERTER:

Figure 4.1 Resistor Load Inverter

The basic structure of the resistive-load inverter circuit is shown in Fig. 4.1.

As in the general inverter circuit already examined in Fig. 5.3, an enhancement-type

nMOS transistor acts as the driver device. The load consists of a simple linear resistor,

RL. The power supply voltage of this circuit is VDD. Since the following analysis

concentrates on the static behaviour of the circuit, the output load capacitance is not

shown in this figure. As already noted in Section 5. 1, the drain current ID of the

driver MOSFET is equal to the load current R in DC steady-state operation. To

simplify the calculations, the CHAPTER S channel-length modulation effect will be

neglected in the following, i.e., A = 0. Also, note that the source and the substrate

terminals of the driver transistor are both connected to the ground; hence, VSB = 0.

Consequently, the threshold voltage of the driver transistoris always equal to V..We

start our analysis by identifying the various operating regions of the driver transistor

under steady-state conditions.

For input voltages smaller than the threshold voltage V., the transistor is in cut-off,

and does not conduct any drain current. Since the voltage drop across the load resistor

is equal to zero, the output voltage must be equal to the power supply voltage, VDD.

As the input voltage is increased beyond V7.,the driver transistor starts conducting a

non-zero drain current. Note that the driver MOSFET is initially in saturation, since

its drain-to source voltage. (VDs = V0,t) is larger than (V,, - V.). Thus,

With increasing input voltage, the drain current of the driver also increases, and the

output voltage V0,, starts to drop. Eventually, for input voltages larger than Vut+ V.,

the driver transistor enters the linear operation region. At larger input voltages, the

transistor remains in linear mode, as the output voltage continues to decrease.

The various operating regions of the driver transistor and the corresponding input-output


conditions are listed in the following table.

Figure 4.1 shows the voltage transfer characteristic of a typical resistive-load inverter

circuit, indicating the operating modes of the driver transistor and the critical voltage

points on the VTC. Now, we start with the calculation of the five critical voltage

points, which determine the steady-state input-output behaviour of the inverter.

CALCULATION OF VOH:

CALCULATION OF VOL:

CALCULATION OF VIL:

CALCULATION OF VIH:

Resistive Load Inverter with threshold voltage, noise margin and delay

times


HSPICE CODE:

Inverter with resistive load

Vgs vg 0 5

vddvd 0 5

r1vdvo 10k

m1vo vg 0 0 N_1u l=1u w=10u

.inccmosedu_models.txt

.dc vgs 0 5 0.1


.end

SIMULATION RESULT:

CALCULATION:

Voh=4.9843V

Vih=1.9883V

Vol=0.4877V

Vil=0.8004V

NMh=Voh Vih =4.9843-1.9883

=2.996V

NMl=Vil Vol =0.8004-0.4877


=0.3127V

Thresold voltage

Vth=Vin=Vout=1.6V

Inverter with resistive load transfer characteristics for different values of

resistor

HSPICE CODE:

Inverter with resistive load

vgs vg 0 5

vddvd 0 5

*for r=100k

r1vdvo 100k


*for r=10k

r2vd vo1 10k

m2 vo1 vg 0 0 N_1u l=2u w=15u

*for r=5k

r3vd vo2 5k

m3 vo2 vg 0 0 N_1u l=2u w=15u

.inc cmosedu_models.txt

.dc vgs 0 5 0.1

.option nomod post=2.end


SIMULATION RESULT:

Inverter with resistive load transfer characteristics for different values of

w/l.

HSPICE CODE:

vgs vg 0 vo2

vddvd 0 vo2

*for w1/l1

r1vdvo 100k


*for w2/l2

r2vd vo1 100k

m2 vo1 vg 0 0 N_1u l=5u w=20u

*for w3/l3

r3vd vo2 100k

m3 vo2 vg 0 0 N_1u l=1u w=10u

.inc cmosedu_models.txt

.dc vgs 0 5 0.1


.end


SIMULATION RESULT:

CONCLUSION:


__/__/____


EXPERIMENT 05

Design CMOS inverter


2. Plot transfer characteristics for different values of W/L


CMOS INVERTER:

Fig 5.1 CMOS inverter

All of the inverter circuits considered so far had the general circuit structure shown in

Fig.5.1 consisting of an enhancement-type nMOS driver transistor and a load device

which can be a resistor, an enhancement-type nMOS transistor, or a depletion-type

nMOS transistor acting as a nonlinear resistor. In this general configuration, the input

signal is always applied to the gate of the driver transistor, and the operation of the

inverter is controlled primarily by This configuration is called Complementary MOS

(CMOS). The circuit topology is complementary push-pull in the sense that for high

input, the nMOS transistor drives (pulls down) the output node while the pMOS

transistor acts as the load, and for low inpu the pMOS transistor drives (pulls up) the

output node while the nMOS transistor acts as the load. Consequently, both devices

contribute equally to the circuit operation characteristics.

switching the driver. Now, we will turn our attention to a radically different inverter

structure, which consists of an enhancement-type nMOS transistor and an

enhancement-type pMOS transistor, operating in complementary mode (Fig. 5.1).

The CMOS inverter has two important advantages over the other inverter

configurations.

The first and perhaps the most important advantage is that the steady-state power

dissipation of the CMOS inverter circuit is virtually negligible, except for small

power dissipation due to leakage currents. In all other inverter structures examined so

far, a nonzero steady-state current is drawn from the power source when the driver

transistor is turned on, which results in a significant DC power consumption. The

other advantages of the CMOS configuration are that the voltage transfer

characteristic (VTC) exhibits a


full output voltage swing between 0 V and VDD, and that the VTC transition is

usually very sharp. Thus, the VTC of the CMOS inverter resembles that of an ideal

inverter.Since nMOS and pMOS transistors must be fabricated on the same chip side-

by-side,the CMOS process is more complex than the standard nMOS-only process. In

particular, the CMOS process must provide an n-type substrate for the pMOS

transistors and a p-type substrate for the nMOS transistors. This can be achieved by

building either n-type tubs(wells) on a p-type wafer, or by building p-type tubs on an

n-type wafer (cf. Chapter 2).In addition, the close proximity of an nMOS and a pMOS

transistor may lead to the formation of two parasitic bipolar transistors, causing a

latch-up condition. In order top revent this undesirable effect, additional guard rings

must be built around the nMOS and the pMOS transistors as well (cf. Chapter 13).

The increased process complexity ofCMOS fabrication may be considered as the

price being paid for the improvements achieved in power consumption and noise

margins

Calculation of VOH

VOH = VDD

Calculation of VIL

Calculation of VOL

VOL = 0

Calculation of VIH


Calculation of VTH

1. Static characteristic of CMOS inverter

HSICE CODE:

cmos


vddvdgnd 5v

vin vi gnd 5v

m2vd vi vovd P_1u l=1u w=2.5u

m3vo vi gndgnd N_1u l=1u w=1u

.tran 0.01ms 10ms

.dc vin 0 5 0.1


.probe i(m2)

.probe i(m3)

.end


SIMULATION OUTPUT:


HSICE CODE:

CMOS


.subcktinvvivovdgnd

.ends

Vddvdgnd 5v

vin vi gnd pulse(0v 5v 0ns 0.5ns 0.5ns 2ns 4ns)



*measurement of propagation delay

.measure trantplh trig v(vi)val=2.5 fall=2.5 targ v(vo) val=2.5

rise=2.5

.measure trantphl trig v(vi) val=2.5 rise=2.5 targ v(vo) val=2.5

fall=2.5

.measure trantpdparam ='(tplh+tphl)/2'


*measure critical voltage

x1 vi vovdgndinv

x2 vi1 vo1 vdgndinv

vex vi1 vi 0.05

.measure dc voh find v(vo) at 0

.measure dc vol find v(vo) at 5

.measure dc vil find v(vi) when par('(v(vo1)-v(vo))/0.05')=-1

cross=1

.measure dc vih find v(vi) when par('(v(vo1)-v(vo))/0.05')=-1

cross=2

.dc vin 0 5 0.01

.tran 0.01ns 10ns


.probe i(m2)

.probe i(m3)

.end

voh= 5.0000E+00

vol= 0.0000E+00

vil= 3.6257E+00

vih= failed

transient analysis

tnom= 25.000 temp= 25.000

tplh= 3.5055E-11 targ= 6.7851E-09 trig= 6.7500E-09

tphl= 7.4542E-11 targ= 4.3245E-09 trig= 4.2500E-09

tpd= 5.4798E-11


SIMULATION OUTPUT:

3. Plot transfer characteristics for different values of W/L

HSICE CODE:

cmos


vddvdgnd 5v

vin vi gnd 5v


m1vd vi vo1 vd P_1u l=4u w=4.5u

m4 vo1 vigndgnd N_1u l=2u w=2u


.tran 0.01ms 10ms

.dc vin 0 5 0.1


.probe i(m2)

.probe i(m3)

.end


SIMULATION OUTPUT:

CONCLUSION:


__/__/___


EXPERIMENT 06

Design NAND gate and plot switching characteristics for same


TWO-INPUT NAND GATE:

The circuit diagram, the logic symbol, and the corresponding truth table of the gate

are given in Figure The Boolean AND operation is performed by the series

connection of the two enhancement type nMOS driver transistors. There is a

conducting path between the output node and the ground only if the input voltage VA

and the input voltage VB are equal to logic-high, i.e., only if both of the series-

connected drivers are turned on. In this case, the output voltage will be low, which is

the complemented result of the AND operation. Otherwise, either one or both of the

driver transistors will be off, and the output voltage will be pulled to a logic-high level

by the depletion-type nMOS load transistor.

Figure shows that all transistors except the one closest to the ground are subject to

substrate-bias effect, since their source voltages are larger than zero. We have to

consider this fact in detailed calculations. For all of the three input combinations

which produce a logic-high output voltage, the corresponding VOH value can easily

be found as VOH = VDD. The calculation of the logic-low voltage VOL, on the other

hand, requires a closer investigation.

SCHEMATIC DIAGRAM:


HSPICE CODE:

cmos


Vddvdgnd 5v

vin vi gnd pulse(0v 5v 0ns 0ns0ns 2ns 4ns)

vin1 vi1 gndpulse(0v 5v 0.5ns 0ns 0ns 4ns 8ns)

*different values for measuring voltage

m1vo vi1 vdvd P_1u l=1u w=2.5u

m3vo vi vdvd P_1u l=1u w=2.5u

m2vo vi vo1 gnd N_1u l=1u w=1u

m4 vo1 vi1 gndgnd N_1u l=1u w=1u

*defining output capacitance

cloadvognd 0.5ff

.tran 0.01ns 10ns

.probe

.end


SIMULATION OUTPUT:

CONCLUSION:


__/__/____


EXPERIMENT 7

Design DRC free layout of CMOS inverter and plot dynamic

characteristics


INTRODUCTION:

Full-Custom Mask Layout Design:

The basic mask layout design guidelines for CMOS logic gates will be presented here.

The design of physical layout is very tightly linked to overall circuit performance

(area, speed, power dissipation) since the physical structure directly determines the

transconductances of the transistors, the parasitic capacitances and resistances, and

obviously, the silicon area which is used for a certain function. On the other hand, the

detailed mask layout of logic gates requires a very intensive and time-consuming

design effort, which is justifiable only in special circumstances where the area and/or

the performance of the circuit must be optimized under very tight constraints.

Therefore, automated layout generation (e.g., standard cells + computer-aided

placement and routing) is typically preferred for the design of most digital VLSI

circuits. In order to judge the physical constraints and limitations, however, the VLSI

designer must also have a good understanding of the physical mask layout process.

After a topologically feasible layout is found, the mask layers are drawn (using a

layout editor tool) according to the layout design rules. This procedure may require

several small iterations in order to accommodate all design rules, but the basic

topology should not change very significantly. Following the final DRC (Design Rule

Check), a circuit extraction procedure is performed on the finished layout to

determine the actual transistor sizes, and more importantly, the parasitic capacitances

at each node. The result of the extraction step is usually a detailed.

CMOS Layout Design Rules:

The main objective of design rules is to achieve a high overall yield and reliability

while using the smallest possible silicon area, for any circuit to be manufactured with

a particular process.

The design rules are usually described in two ways:

Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute

dimensions in micrometers, or, Lambda rules, which specify the layout constraints in terms of a single

parameter and, thus, allow linear, proportional scaling of all geometrical

constraints.


MOSIS Layout Design Rules (sample set)

Rule number Description L-Rule

R1 Minimum active area width 3 L

R2 Minimum active area spacing 3 L

R3 Minimum poly width 2 L

R4 Minimum poly spacing 2 L

R5 Minimum gate extension of poly over active 2 L

R6 Minimum poly-active edge spacing 1 L

(poly outside active area)

R7 Minimum poly-active edge spacing 3 L

(poly inside active area)

R8 Minimum metal width 3 L

R9 Minimum metal spacing 3 L

R10 Poly contact size 2 L

R11 Minimum poly contact spacing 2 L

R12 Minimum poly contact to poly edge spacing 1 L

R13 Minimum poly contact to metal edge spacing 1 L

R14 Minimum poly contact to active edge spacing 3 L

R15 Active contact size 2 L

R16 Minimum active contact spacing 2 L

(on the same active region)

R17 Minimum active contact to active edge spacing 1 L

R18 Minimum active contact to metal edge spacing 1 L

R19 Minimum active contact to poly edge spacing 3 L

R20 Minimum active contact spacing 6 L

(on different active regions)


Figure-2: Illustration of some of the typical MOSIS layout design rules listed

above.

CMOS Inverter Layout Design:

In the following, the mask layout design of a CMOS inverter will be examined

step-by-step. The circuit consists of one nMOS and one pMOS transistor; therefore,

one would assume that the layout topology is relatively simple. Yet, we will see

that there exist quite a number of different design possibilities even for this very

simple circuit First, we need to create the individual transistors according to the

design rules. Assume that we attempt to design the inverter with minimum-size

transistors. The width of the active area is then determined by the minimum

diffusion contact size (which is necessary for source and drain connections) and the

minimum separation from diffusion contact to both active area edges. The width of

the polysilicon line over the active area (which is the gate of the transistor) is

typically taken as the minimum poly width (Fig. 3). Then, the overall length of the

active area is simply determined by the following sum: (minimum poly width) + 2

x (minimum poly-to- contact spacing) + 2 x (minimum spacing from contact to

active area edge). The pMOS transistor must be placed in an n-well region, and the

minimum size of the n- well is dictated by the pMOS active area and the minimum

n-well overlap over n+. The distance between the nMOS and the pMOS transistor

is determined by the minimum separation between the n+ active area and the n-well

(Fig. 4). The polysilicon gates of the nMOS and the pMOS transistors are usually

aligned. The final step in the mask layout is the local interconnections in metal, for

the output node and for the VDD and GND contacts (Fig. 5). Notice that in order to


be biased properly, the n-well region must also have a VDD contact.

Figure-3: Design rule constraints which determine the dimensions of a minimum

size transistor. .

Figure-4: Placement of one Nmos and one pMOS transistor


The initial phase of layout design can be simplified significantly by the use of stick

diagrams - or so-called symbolic layouts. Here, the detailed layout design rules are

simply neglected and the main features (active areas, polysilicon lines, metal lines)

are represented by constant width rectangles or simple sticks. The purpose of the stick

diagram is to provide the designer a good understanding of the topological

constraints, and to quickly test several possibilities for the optimum layout without

actually drawing a complete mask diagram. In the following, we will examine a series

of stick diagrams which show different layout options for the CMOS inverter circuit

LAYOUT: CMOS INVERTER


SIMULATION OUTPUT:

Figure-6: Complete Output wave form of the CMOS inverter.

CONCLUSION:


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EXPERIMENT 8

Design DRC free layout of CMOS-NAND AND CMOS-NOR and

plot dynamic characteristics


Layout of CMOS NAND and NOR Gates:

The mask layout designs of CMOS NAND and NOR gates follow the general

principles examined earlier for the CMOS inverter layout. Figure 7 shows the sample

layouts of a two- input NOR gate and a two-input NAND gate, using single-layer

polysilicon and single-layer metal. Here, the p-type diffusion area for the pMOS

transistors and the n-type diffusion area for the nMOS transistors are aligned in

parallel to allow simple routing of the gate signals with two parallel polysilicon lines

running vertically. Also notice that the two mask layouts show a very strong

symmetry, due to the fact that the NAND and the NOR gate are have a symmetrical

circuit topology. Finally, Figs 8 and 9 show the major steps of the mask layout design

for both gates, starting from the stick diagram and progressively defining the mask

layers.

Figure-7: Sample layouts of a CMOS NOR2 gate and a CMOS NAND2 gate.


1. NAND GATE:

MICROWIND LAYOUT:

figure: Complete mask layout of the CMOS NAND gate.


MICROWIND SIMULATION:

figure: Complete Output wave form of the CMOS NAND gate


2. NOR GATE:

MICROWIND LAYOUT:

Figure:Complete mask layout of the CMOS NOR gate.


MICROWIND SIMULATION:

figure: output wave form of nor gate

CONCLUSION:


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