High Efficiency Amplifiers for EDGE Applications Based on Enhancement-Mode Junction PHEMT

J.C. Clifton, L.Albasha

Sony Semiconductor & Electronic Solutions

M.Willer

Sony CSBD

13th September 2004

Technology: Sony J-PHEMT

pn Junction Gate → High Vf → High Drain Current

Source p-Gate Drain

GaAs Sub.

InGaAs Channel

JPHEMT Vf = 1.2 (V)

Id

Ig

Schottky HEMTVf = 0.7 (V)

Ig

Vg

Id, Ig

Id

Vth

JPHEMT Structure•Higher forward voltage enables positive drive.

Objectives: Designing an EDGE PA

• EDGE functionality required from iteration of current GSM PA: Dualmode PA.

• Interface to a Direct Modulation Transceiver: to allow future inclusion of WCDMA for future single GSM/EDGE/WCDMA TX Architecture.

• Inclusion of EDGE functionality with only a small impact to the size and cost of the basic GSM solution.

• Meet EVM specifications over VSWR of 3:1 without isolator and avoid complex calibration/set-up.

• Target EDGE efficiencies 25%+ whilst maintaining current GSM performance of 55-60%.

Types of EDGE (8PSK) Power Amplifier

GSM/EDGE PA

Increased Vgg for linear operation

Fixed Vdd=3.5V Operation

Backed off Input Power, Pin

Coupler for PACL

Pout=28.5dBm

            

LimiterS(t) PA

Log Amplifier

Limiter

VCO

Phase detector

Sin(wt)

Amplitude Modulator

Limiter

Log Amplifier

S(t) PA 

Phase detector

Sin(wt)

Phase Modulator or VCO

Linear/Backed-Off PA Approach

• J-PHEMT gives respectable efficiency at several dB back-off whilst maintaining EVM & ACPR

• Simple and robust architecture

• Also suited for WCDMA

• Sometimes issues meeting EVM spec under mismatch conditions: Isolator.

• Efficiency suffers under back-off

PA

Polar Loop Approach

• J-PHEMT gives good saturated efficiency

• Additional efficiency comes at the expense of much greater complexity

• Difficult to adopt for WCDMA and use with direct modulator transceiver

• Headline efficiency impacted by consumption within AM-AM and AM-PM feedback loops

Simulation Test Bench

• 3 Stage PA model based on Agilent Eesof model on ADS.

• System simulation tool ptolemy to allow inclusion of AM and PM correction loops. Simulation of ACPR, EVM, output power and efficiency.

• Used to simulate Linear/Back-off PA in addition to various different types of saturated PA.

Envelope Elimination and Restoration (EER) Power Amplifiers for EDGE

Advantage: Drive Level and Power Control (eg drain regulation) similar to GMSK (constant Envelope)

Issue: Method of Envelope insertion and correction

Amplitude Modulator

Delay matching

Limiter

Envelope Detector

S(t) PA

Envelope Detector

Amplitude Modulator

Delay matching

Limiter

Envelope DetectorEnvelope Detector

S(t) PA

Envelope DetectorEnvelope Detector

Corrected Envelope inserted onto drain or gate supply

Saturated PA Architectures

Control Characteristics (1mm, 900MHz)

20mm E-pHEMT Pin=15dBm

0

2

4

6

8

10

12

14

16

18

20

0 0.5 1 1.5

Gate Bias V

EV

M % EVM%

Gate Drain

0

5

10

15

20

25

30

1 1.5 2 2.5 3 3.2

Drain Voltage (V)

Ga

in (

dB

)

Gain (dB)

EVM (%)

00.5

11.5

22.5

3

1 1.5 2 2.5 3.5

Drain Voltage (V)

EVM (%)

EER Based on Drain Voltage

Amplitude Modulator

Delay matching

Limiter

Envelope Detector

S(t) PA

Envelope Detector

Amplitude Modulator

Delay matching

Limiter

Envelope DetectorEnvelope Detector

S(t) PA

Envelope DetectorEnvelope Detector

RF Output Signal make to track EDGE Envelope by AM Correction Loop

 

Loop Dynamics optimised to minimise Error Voltage whilst ensuring loop stability over range of control and supply voltages

Corrected Drain Voltage (max=3.5V)

Associated Drain Current

DRAIN VOLTAGE/CURRENT CHARACTERISTICS

PAE: 40-45% using fast DC-DC converter

Corrected RF Output Signal

Phase Distortions

60° Phase variation over

envelope

EVM> 11%. AM-PM Correction loop required to reduce EVM to 1.5% and bring ACPR inside specification:

Limiter PA

Log Amplifier

VCO

Sin(wt)

Amplitude Modulator

Limiter

Log Amplifier

PA

Phase Modulator or VCO

S(t)

Limiter

–Phase detector

EER Based on Gate Voltage

Amplitude Modulator

Delay matching

Limiter

Envelope Detector

S(t) PA

Envelope Detector

Amplitude Modulator

Delay matching

Limiter

Envelope DetectorEnvelope Detector

S(t) PA

Envelope DetectorEnvelope Detector

20 Degrees

  

 Phase error significantly reduced. Resulting EVM of 3.2%. Further reduced with the addition of simple pre-distortion circuit. Simulated PAE of 44%.

Adaptive Bias Control Based on Gate Voltage

PA operated in saturated mode. Gate tracking circuit designed to exhibit constant gain over input envelope. Simulated efficiency of 50%.

Resulting phase variation of <10° over envelope and EVM of 1%.

Phase error due to compression is partly offset by impact of phase variation caused by gate bias shifts required to keep gain constant

Delay matching

PA

Delay m atching

PA

Input Signal: Including Envelope

Gate bias correction loop

LOG Amp

LOG Amp

Amp. Mod.

Practical Measurements of Gate Correction Circuit with Class A/B PA out of Compression

Implementation Issues for PA in compression: AM Correction loop design –extreme sensitivity of gate voltage to EVM and ACPR.

A

Unit dBm

Ref Lvl

0 dBm

Ref Lvl

0 dBm

RF Att 30 dB

Center 900 MHz Span 2 MHz200 kHz/

RBW 30 kHz

VBW 30 kHz

SWT 6 ms

1AVG 1SA

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

1

1

Delta 1 [T1]

-36.14 dB

400.00000000 kHz

Date: 17.JUN.2004 11:39:04

A

Unit dBm

Ref Lvl

0 dBm

Ref Lvl

0 dBm

RF Att 30 dB

Center 900 MHz Span 2 MHz200 kHz/

RBW 30 kHz

VBW 30 kHz

SWT 6 ms

1AVG 1SA

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

1

1

Delta 1 [T1]

-54.30 dB

400.00000000 kHz

Date: 17.JUN.2004 11:42:32

-36.1dBc, 400KHz offset -54.3dBc, 400KHz offset

Gate AM correction circuit reduced EVM from 16% down to 3%.

Linear PA Investigations

Required improvements for product:

• Elimination of output isolator: meet EVM spec in 3:1 Antenna VSWR

• Elimination of output coupler/detector and control feedback loops: Open Loop Control

• Avoidance of 30-40dB VGA/VVA which impacts power consumption, size and RX Noise performance (TX SAW not acceptable)

• Improve efficiency compared to conventional EDGE Linear Power Amps

Objectives Met with Modified Linear PA

Modifications compared to conventional Linear PA to Improve Efficiency at back-off and simplify power control scheme

Modified Linear PA: Measured Performance

0.00

5.00

10.00

15.00

20.00

25.00

30.00

0.00 0.50 1.00 1.50 2.00

Vramp

Ou

tpu

t P

ow

er(d

Bm

) &

PA

E (

%)

Output Pow er (dBm)

Efficiency (%)

EVM(%)

Gate Supply= V1 for GSM

V2 for EDGE

(V2>V1)

Vd supply=Vbattery

DualMode PA

GMSK: Compressed

EDGE: Linear

Input Step Attenuation: EDGE HI, GMSK LO

GMSK O/P Matched

RFin

Vramp (GSM & EDGE)

RFout

34.5dBm GMSK

28.5dBm EDGE

(excluding VGA consumption required for conventional PA)

PAE comparison between New Linear EDGE PA and Conventional Type

0

5

10

15

20

25

0 10 20 30

Output Power(dBm)

Eff

icie

ncy

(%

)

Modified Linear PA

ConventionalLinear PA

-30

-20

-10

0

10

20

30

40

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vramp (Volts)

Pout

(dB

m) -20C

20C

85C

Measured Pout/Temperature Characteristics

Modified Linear PA

Open-Loop Operation and Mismatch: Measurements

Temperature stable, variable gain PA

Power Error BudgetFrequency Variation < +/-1.0dBTemperature Variation < +/-1.0dB

WORST CASE < +/-2.0dBSPEC(E2) +/-4.0dB

G01 - EVM vs VSWR at 900MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

VSWR

EV

M /

%

28.5dBm (High)

20.0dBm (High)

20.8dBm (Low)

5.1dBm (Low)

G01 - Pout vs VSWR at 900MHz

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

18.0

20.0

22.0

24.0

26.0

28.0

30.0

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

VSWR

Po

ut

/ d

Bm

28.5dBm (High)

20.0dBm (High)

20.8dBm (Low)

5.1dBm (Low)

Without isolator

RX Noise: -82.3dBm/100KHz @20Mhz offset from carrier

(-10dBm input power, 28.3dBm Output)

Conclusions

• Promising simulation results for JPHEMT PA in both Saturated (Polar Loop/EER) and Linear modes, proving capabilities of the device.

• Adaptive Bias Control of Compressed PA based on gate envelope tracking looks promising from viewpoint of reduced complexity and performance. However, significant implementation issues exist.

• Approach based upon modified linear PA proved best suited to meeting original objectives.

• EDGE RF functionality possible with very small size/cost impact to GSM solution. Forward compatibility with WCDMA.

Acknowledgements

• Colleagues at Atsugi Technology Centre: H. Kawasaki, H. Kawamura and H. Motoyama

• Support from Thomas LeToux, project student from ULP France/UCL UK.

• Agilent ADS UK team for simulation support.