Hardware Test Bed Development

Of LTE Physical Layer

By:

Suvra Sekhar Das,

Saifudeen A R,

G.S.Sanyal School of Telecommunication

Indian Institute of Technology Kharagpur

Activities Undertaken till date

19th January 2012 2IIT Kharagpur Extension Centre,Kolkata

Hardware (Phy)

MATLAB/ HW

System Simulator

PS/RRA-MIMO

Fractional Reuse

Algorithm

WORK PLAN

Optimal Packet Scheduling

and RRA

OLLA FPGA/ HW

Software (Phy)

Fractional Load

MIMO Mode Selection

PMI Coordination

Coordinated Scheduling

Test Bed

Phy Simulator

Fractional Load

Fractional Reuse

Hardware Test Bed DevelopmentUsing WARP

3

Development Approach

Matlab / HW

Pros:

Fast Prototyping,

Need Only Matlab Programming

Cons:

TxRx Delay of order ~0.5-2sec

WARPLab framework limitation (Eg, Frame Buffer Size of 2^14 samples)

FPGA / HW

Pros:

Real Time performance

Delay of order ~1-5ms only

Full utilization of WARP Hardware

Cons:

Longer Development Time,

Needs Matlab/Simulink, Xilinx FPGA DSP and Embedded tools expertise

TestBed - Matlab/HW Approach

-> write I/Q values

<- read I/Q values

EthernetMATLAB

WARPLab FPGA Analog

Radio 3 Radio 2

Radio 1

Ethernet

WARP NodeWARP Bitstream

4

Tx Rx

Binary input Binary output

ECC Enc ECC Dec

Constellation Mapp Constellation DeMapp

OFDM Generation OFDM, Ch Est, Ch Eq

CP Addition CP Remove

I/Q Tx I/Q Rx I/Q Tx I/Q Rx

DAC ADC

Up conversionRF Tx

Down conversion RF Rx

Test Bed - FPGA/HW Approach

-> send packet

<- receive packet

EthernetMATLAB

Host Computer

FPGA Analog

Radio 3 Radio 2

Radio 1

Ethernet

WARP Node

5

Tx Rx

Binary input Binary output Binary input Binary output

Rate Match, ECC Enc Rate Match, ECC Dec

Constellation Mapp Constellation DeMapp

OFDM Generation OFDM, Ch Est, Ch Eq

CP Addition CP Remove

I/Q Tx I/Q Rx

DAC ADC

Up conversionRF Tx

Down conversion RF Rx

Hardware Design Flow

Xilinx ISEEDK

(BitstreamOut)

Xilinx ISESystem

Generator

Custom design

*.m (Matlab)

*.mdl(Simulink)

*.c/c++

pcore

WARP

pcore device driver

Custom bitstream

Matlab/HW Setup

Transmitter

Antenna 1

Receive

Antenna 1

Node1

Transmitter

Antenna 1

Host PC

Receive

Antenna 1

Receive

Antenna 2

WARP

Board

Experiment ConductedI. CP-OFDM based transceiver

II. Link adaptation and Effect of

Interference

III. Error correction, Interleave,

Scrambler

IV. 1x2 MIMO MRC EGC and SC

combining

6

Matlab/HW - Link Adaptation With SNR Output

Real time status for MRC 1x2 MIMO Tx/Rx setup

Receive Antenna 1

Receive Antenna 2

BER Threshold 10-2

M C Index

64 QAM 2/3 7

64 QAM 1/2 6

16 QAM 2/3 5

16 QAM 1/2 4

QPSK 2/3 3

QPSK 1/2 2

QPSK 1/3 1

7

Matlab/HW - Interference Experiment

Transmitter

Antenna 1

Host PC

Receive

Antenna 1

Receive

Antenna 2

WARP

Board 1

Interference

Antenna

WARP

Board 2

8

Matlab/HW - Interference experiment output

BER Threshold 10-2

Receive Antenna 2

Receive Antenna 1

M C Index

64 QAM 2/3 7

64 QAM 1/2 6

16 QAM 2/3 5

16 QAM 1/2 4

QPSK 2/3 3

QPSK 1/2 2

QPSK 1/3 1

9

Matlab/HW - 1x2 MIMO combining techniques

Tx/Rx Image for Equal Gain and

Maximum Ratio Combining

(1x2 MIMO setup)

10

Work Status Matlab/HW

19th January 2012 IIT Kharagpur Extension Centre,Kolkata 11

Activity Year 1 Year 2 Year 3

OFDM-CP + Link

Adaptation

Turbo

PRB

TBS/CBS

MAC Scheduler

MAC on 2 boards

12

MAC Application: top-level C code for

MAC protocol

LTE PHY/MAC framework: Low-level

PHY control and MAC primitives,

implemented in C code

LTE PHY: FPGA implementation of the

LTE physical layer, built in System

Generator

Support Peripherals: Other peripherals

cores in the FPGA (timer, radio bridges,

etc.)

LTE FPGA/HW Design

LTE PHY LTE MAC

MAC Algorithm and Application

PHY Driver

Timer Driver

DMA Driver

Ethernet MAC

Driver

Misc. Driver

Custom PHY

RadioController

LTETx

PacketBuffers

RadioBridges

Ethernet MAC

Timer

LTERx

AGC PacketDetect

Radios 1-4Ethernet

PowerPCC/C++

FPGALogic

Hardware

Processor Local Bus

Control

I/Q &RSSI

Digital I/Q

Digital I/Q

a) OFDM Based Transmitter Block Diagram(Tx)

IFFT +

CP+

P/S(OFDM)

DACRF

(BB, RF Gain)

Power Amp

Transmitter Blocks

S/P+

Symbol Mapper(QPSK,

16-QAM64-QAM)

IFFT Sub Carrier MappingBuffer

(RateMatching) C

RC

Code Block

Segmentation

FECrate1/3,1/2,2/3

Inte

rlea

ver

Scra

mb

ler

Binary I/P

13

b) OFDM Based Receiver Block Diagram

Packet Detect

Frame SynchRF Stage

LNA + MixerAGC A/D

Sync

Symbol DeMapperQPSK,16,64-QAM

De-

Inte

rlea

verBuffer Fill CRC

Co

de

Blo

ckC

on

cate

nat

ion

De-

Scra

mb

ler

FEC

Dec

od

ing

Dec

Coarse Freq. Offset Est.+ Compen+ FFO

FFTDe Mappier

CP Remove +S/P + FFT

Ch

ann

el E

st

Equalize

Receiver Blocks

Binary O/P

14

c) Baseband Tx-Rx Simulink Prototype

15

d) System Generator Simulation

Transmitted ‘I’ value

Received

‘Real’ value

Matched

Filter O/P

Sampling

Instants

Detected ‘I’

value

16

e) Channel

D/A Gateway Output Port

A/D GatewayInput Port

Experiment Setup DAC - ADC

17

I/Q 64 QAM

f) I/Q signal output from hardware DAC

64QAM Constellation18

Root Raised Cosine Pulse1. Received signal after ADC

2. Receiver filter output (MF)

Modulation - 64 QAM

Symbol Period - 1us

g) Baseband Signal Through True Channel

Transmitter

I/Q

Transmitter I

Received I

Integrator o/p

Detected I

Received I

MF sampling Pulses

~300ns

19

h) Symbol Synchronization Error 16 QAM

Detected I/Q

ConstellationDetected I/Q

Constellation

With Symbol

timing Error

Detected I

With Symbol

timing Error of 4

samples

(32 sample/symb)

Detected I

With proper

Symbol timing

(32 sample/symb)

20

Work Status FPGA/HW

19th January 2012 IIT Kharagpur Extension Centre,Kolkata 21

Activity Year 1 Year 2 Year 3Mapp/Demapp

Baseband TxRx

OFDM+CP

Channel Est/Eq(1)

Turbo EncDec

PRB, Frame,TBS

AGC, Packet Det

Frame Sync, RF Radio

Carrier-CFO,FFO

Symbol Clock Recovery

Channel Est/Eq(2)

Thank You

22