Hardware Reference Manualbrads/Manuals/Hardware/XVR16... · 2017-11-10 · Hardware Reference Manual ... Intel 64 and IA-32 Architectures Optimization Reference Manual. 8 XVR16* 4th

Hardware Reference ManualXVR16* 4th Generation Intel® Core™ i7 Based Rugged VME S i ng le Boar dComputerTHE XVR16 IS DESIGNED TO MEET THE EUROPEAN UNION (EU) RESTRICTIONS OF HAZARDOUS SUBSTANCE (ROHS) DIRECTIVE (2002/95/EC) CURRENT REVISION.

Publication No. 500-9300007876-000 Rev. C.0

2 XVR16* 4th Generation Intel® Core™ i7 Based Rugged VME Single Board Computer Publication No. 500-9300007876-000 Rev. C.0

Document History

Waste Electrical and Electronic Equipment (WEEE) Returns

Revision Date Description

A December 2014 Original Release

B.0 October 2015 ECR-00027119 In Section 5.4 Table 5-20, replace table with three other tables detailing the P0 connector built options: Partial, Limited, and Full. In Section 1.1.6 Table A-11, correct the DMS59 Connector Digital PinAssignments DVI1 and DVI2.

C.0 September 2016 Reformatting

Abaco Systems is registered with an approved Producer Compliance Scheme (PCS) and, subject

to suitable contractual arrangements being in place, will ensure WEEE is processed in accordance

with the requirements of the WEEE Directive.

Abaco Systems will evaluate requests to take back products purchased by our customers before

August 13, 2005 on a case-by-case basis. A WEEE management fee may apply.

Publication No. 500-9300007876-000 Rev. C.0 About This Manual 3

About This Manual

Conventions

NoticesThis manual may use the following types of notice:

WARNINGWarnings alert you to the risk of severe personal injury.

CAUTIONCautions alert you to system danger or loss of data.

NOTENotes call attention to important features or instructions.

TIPTips give guidance on procedures that may be tackled in a number of ways.

LINKLinks take you to other documents or websites.

NumbersAll numbers are expressed in decimal, except addresses and memory or register data, which are expressed in hexadecimal. Where confusion may occur, decimal numbers have a “D” subscript and binary numbers have a “b” subscript. The prefix “0x” shows a hexadecimal number, following the ‘C’ programming language convention. Thus:

One dozen = 12D = 0x0C = 1100b

The multipliers “k”, “M” and “G” have their conventional scientific and engineering meanings of x103, x106 and x109 respectively. The only exception to this is in the description of the size of memory areas, when “k”, “M” and “G” mean x210, x220 and x230 respectively.

NOTEWhen describing transfer rates, “k”, “M” and “G” mean x103, x106 and x109 not x210, x220 and x230.

In PowerPC terminology, multiple bit fields are numbered from 0 to n where 0 is the MSB and n is the LSB. PCI terminology follows the more familiar convention that bit 0 is the LSB and n is the MSB.

TextSignal names ending with a tilde (“~”) denote active low signals; all other signals are active high. “N” and “P” denote the low and high components of a differential signal respectively.


Further Information

Abaco WebsiteYou can find information regarding Abaco products on the following website:

LINKhttps://www.abaco.com

Abaco DocumentsThis document is distributed via the Abaco website. You may register for access to manuals via the website.

LINKhttps://www.abaco.com/products/

Third-party DocumentsANSI/VITA 1.1-1994American National Standard for VME64(R2002)

ANSI/VITA 1.1-1997American National Standards for VME64 Extensions (R2003)

ANSI VITA 20-2001American National Standard for Conduction Cooled PMC

ANSI/TIA/EIA-485-AMarch 1998

ANSI/TIA/EIA-422-BJanuary 2000

ANSI/VITA 31.1-2003 VMEbus International Trade Association

ANSI/VITA 32-2003PMC Standard for Processor /PCI Mezzanine Cards (R2009)

ANSI/VITA 35-2000American National Standard for PMC-P4 Pin Out Mapping to VME-P0 and VME64x-P2 April 2000

ANSI/VITA 38Intelligent Platform Management (IPMI) with VME(R2008)

ANSI/VITA 39.1-2003 American National Standard for PCI-X Auxiliary Standard for PMCs and Processor PMCsAugust 2003

https://www.abaco.com/

https://www.abaco.com/products/



ANSI/VITA 42.0American National Standard for XMC December 2008

ANSI/VITA 42.3American National Standard for XMC PCI Express Protocol Layer Standard June 2006

ANSI/VITA 61.0 XMC 2.0November 2011

European Union Directive 2002/95/EC of the European Parliament of 27 January 2003 on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment (RoHS)

European Union, Directive 2002/96/EC of the European Parliament of 27 January 2003 on Waste Electrical and Electronic Equipment (WEEE)

IEEE 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture June 1993

IEEE 1386-2001, IEEE Standard for a Common Mezzanine Card (CMC) Family June 2001

IEEE 1386.1-2001/IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC)October 2001

IPC, IPC-A-600 Acceptability of Printed Board Rev F,November 1999

IPC, IPC-A-610, Acceptability of Electronic Assemblies, Rev CJanuary 2000

IPC, IPC-CC-830B, Qualification and Performance of Electrical Insulating Compound for Printed Wiring Assemblies, Rev BAugust 2000

MIL-HDBK-217F, Military Handbook, Reliability Prediction of Electronic Equipment December 1991

Underwriterʹs Labs, UL-94 V0 and V1, Standard for Tests for Flammability of Plastic Materials for Parts in Devices and Appliance, Edition 5October 1996

Intel, Low Pin Count (LPC) Interface Specification, Rev 1.1, Document Number: 251289-001, August 2002


PICMG 2.9 System Management Specification, Rev 1.0, May 2002

PCI Special Interest Group (SIG), PCI Local Bus Specification, Revision 2.2 December 1998

PCI Special Interest Group (SIG), PCI Express Base Specification, Revision 1.1 March 2005

S-ATA, Serial ATA: High Speed Serialized AT Attachment, Revision 1.0AJanuary 2003

Universal Serial Bus 3.0 Specification, Revision 1.0November 2008

Intel DocumentsIntel Haswell Mobile Processor, External Design Specification (EDS) Volume 1 of 2, Document No.487246-1.0v1May 2012

Intel Shark Bay Mobile Platform Design GuideFor use with Haswell Mobile (rPGA 7 BGA) Processor And Lynx Point Platform Controller Hub (Pch), Revision 1.5 Document Number 486713 September 2012

Intel Lynx Point Platform Controller Hub (PCH) External Design Specification (EDS), Revision 1, June 2012

Intel Lynx Point Platform Controller Hub (PCH) External Design Specification (EDS), Revision 1.5April 2013


The following documents are continuously updated and are available at:

LINKwww.intel.com/products/processor/manuals/

Intel 64 and IA-32 Architectures Software Developerʹs Manual Volume 1: Basic Architecture

Intel 64 and IA-32 Architectures Software Developerʹs Manual Volume 2A: Instruction Set Reference, A-M

Intel 64 and IA-32 Architectures Software Developerʹs Manual Volume 2B: Instruction Set Reference, N-Z

Intel 64 and IA-32 Architectures Software Developerʹs Manual Volume 3A: System Programming Guide Part 1

Intel 64 and IA-32 Architectures Software Developerʹs Manual Volume 3B: System Programming Guide Part 2

Intel 64 Architecture x2APIC Specification

Intel 64 and IA-32 Architectures Application Note TLBs, Paging-Structure Caches, and Their Invalidation

Intel 64 and IA-32 Architectures Optimization Reference Manual

http://www.intel.com/products/processor/manuals/


Technical Support Contact Information

You can find technical assistance contact details on the website Embedded Support page.

LINKhttp://www.abaco.com/embedded-support

Abaco will log your query in the Technical Support database and allocate it a unique Case number for use in any future correspondence.

Alternatively, you may also contact Abaco’s Technical Support via:

[email protected]

Returns

If you need to return a product, there is a Return Materials Authorization (RMA) form available via the website Embedded Support page.

LINKhttp://www.abaco.com/embedded-support

Do not return products without first contacting the Abaco Repairs facility.

Additional Notes

This document provides technical information for Abaco Systems’ XVR16*, a rugged single slot VME Single Board Computer (SBC) in 6U VME form factor equipped with the quad core 4th Generation Intel® Core™ i7 (Haswell) processor and the Mobile Intel QM87 Chipset.

Because the board is available in several options, the descriptions in this Manual are related to the standard configuration, unless otherwise indicated.

LINKhttps://www.abaco.com/products/

References

Below are websites that may be useful references. Registration may be required for access to some sites or specific documents.

LINKwww.vita.comwww.ami.com/support/doc/AMI_TSE_User_Manual_PUB.pdfwww.ieee.comwww.vesa.orgwww.intel.comwww.latticesemi.com

http://www.abaco.com/embedded-support

http://www.abaco.com/embedded-support


http://www.vita.com

http://www.ami.com/support/doc/AMI_TSE_User_Manual_PUB.pdf

http://www.ieee.com

http://www.vesa.org

http://www.intel.com

http://www.latticesemi.com


Safety Summary

The following general safety precautions must be observed during all phases of the operation, service and repair of this product. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture and intended use of this product.

Abaco assumes no liability for the customerʹs failure to comply with these requirements.

Ground the SystemTo minimize shock hazard, the chassis and system cabinet must be connected to an electrical ground. A three-conductor AC power cable should be used. The power cable must either be plugged into an approved three-contact electrical outlet or used with a three-contact to two-contact adapter with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet.

Do Not Operate in an Explosive AtmosphereDo not operate the system in the presence of flammable gases or fumes. Operation of any electrical system in such an environment constitutes a definite safety hazard.

Keep Away from Live CircuitsOperating personnel must not remove product covers. Component replacement and internal adjustments must be made by qualified maintenance personnel. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust AloneDo not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present.

Do Not Substitute Parts or Modify SystemBecause of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification to the product. Return the product to Abaco for service and repair to ensure that safety features are maintained.

10 XVR16*4th Generation Intel® Core™ i7 Based Rugged VME Single Board Computer Publication No. 500-9300007876-000 Rev. C.0

Table of Contents

1 • Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201.2 Software Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

1.2.1 Device Driver Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211.2.2 BIOS Infrastructure Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211.2.3 Target Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2 • Unpacking and Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232.1 Available Accessories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232.2 Unpacking/Handling Warnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.2.1 Electrostatic Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232.2.2 Unpacking the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242.2.3 Inspect Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

2.3 Handling Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262.3.1 Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262.3.2 Handling the Convection Cooled Heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272.3.3 Installation and Power-Up/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3 • Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.1 Installation Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.1.1 VMEbus Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.1.2 Replacing/Disposing of Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.2 Required Items. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.1 Backplane and Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.2 Keyboard and Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.3 Video Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.4 Minimum System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.5 POST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.3 Installing XVR16 into Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313.4 Installation of the Rear Transition Module (VTM26 or VTM28). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313.5 Initial Power-On Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.6 Entering the UEFI Firmware SETUP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4 • Power-up/Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334.1 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334.2 Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.2.1 Clear CMOS/RTC/Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334.2.2 BIOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.3 Unexpected Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344.4 Remote Ethernet Booting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5 • Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355.1 Front Panel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365.2 Front Panel Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.2.1 DisplayPort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375.2.2 Ethernet Interface RJ45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385.2.3 Serial Port COM3 (J28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395.2.4 USB 2.0 Interface (J29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405.2.5 USB 3.0 Interface, Optional (J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415.2.6 LAN, Optional (J34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Publication No. 500-9300007876-000 Rev. C.0 Table of Contents 11

5.2.7 eSATA Interface, Optional (J32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.3 Onboard Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3.1 PMC I/O Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.3.2 PMC1 Connectors (J11, J12, J13, J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.3.3 PMC1 I/O Connector (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475.3.4 PMC2 Connectors (J21, J22, J23, J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485.3.5 PMC2 I/O Connector (J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525.3.6 XMC1 Connector (J15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545.3.7 XMC1 Connector (J16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.3.8 XMC2 Connector (J25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565.3.9 XMC2 Connector (J26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4 Backplane Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585.4.1 VMEbus Connector P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585.4.2 VMEbus Connector P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615.4.3 VMEbus Connector P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625.4.4 Transition Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6 • Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636.1 4th Generation Intel Core i7 Processor Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.1.1 4th Generation Core i7 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646.1.2 Processor Supported Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646.1.3 Processor to PCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.2 QM87 Express Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656.3 CPU Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.3.1 Memory Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656.4 Graphics Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666.5 PCI Express Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676.6 Mezzanine PMC/XMC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686.7 VME Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.7.1 VMEbus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686.7.2 PCI-X to VME Bridge (Tsi148) Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696.7.3 VME \SYSRESET Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.8 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706.9 Timer (8254). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706.10 Real Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716.11 UEFI Firmware - Backup UEFI Firmware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726.12 BMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.12.1 IPMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726.12.2 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.13 Elapsed Time Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.14 Keyboard and Mouse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.15 SATA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.16 Gigabit Ethernet Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.17 Additional Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.17.1 XVR16 Field Programmable Gate Array Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.17.2 Temperature Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.17.3 Geographic Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766.17.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766.17.5 Power Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776.17.6 HD Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7 • System Resources, Memory Mapping, and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787.1 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787.2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79


7.2.1 Standard Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .797.2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

7.3 Advanced Programmable Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .817.4 Message Signaled Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

8 • FPGA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .828.1 FPGA Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

9 • Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1099.1 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109.2 Onboard Lithium Battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

9.2.1 Battery Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1119.2.2 Battery in Vertical Holder; Removal/Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

9.3 External Battery Input (+5VSTDBY). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1139.4 Environmental Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1139.5 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

9.5.1 Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1149.5.2 GPIO 0...11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1159.5.3 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

A • Transition Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116A.1 VTM26 Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

A.1.1 VGA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116A.1.2 Serial Interfaces COM1 (P2100) and COM2 (P2200, P2201) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118A.1.3 Ethernet Interface 10/100/1000BASE-T (P5300, P5400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119A.1.4 USB Connectors (P1600, P1601) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120A.1.5 SATA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121A.1.6 Digital Video Connector DVI 1/2 (P4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122A.1.7 GPIO Connector (P2002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123A.1.8 Miscellaneous Connector (P2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124A.1.9 Audio Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124A.1.10 PMC I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125A.1.11 Write Protection (J2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126A.1.12 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

A.2 VTM28 Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126A.2.1 VGA1 Interface (J31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128A.2.2 Serial Interfaces COM1 (J100) and COM2 (P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128A.2.3 Ethernet Interface 10/100/1000BASE-T (J29, J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129A.2.4 USB Connectors (J23, J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130A.2.5 Digital Video Connector DVI 1/2 (J27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131A.2.6 PMC I/O Connectors (J21/J22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133A.2.7 Write Protection (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135A.2.8 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

B • BIOS Setup Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136B.1 First Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136B.2 Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137B.3 Advanced Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

B.3.1 Set Processor Speed from the Advanced Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139B.3.2 Enabling/Disabling the GbE Boot-from-LAN BIOS Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

B.4 Chipset Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140B.5 Server Management Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141B.6 Boot Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142B.7 Security Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143B.8 Save & Exit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

C • Mezzanine Sites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145C.1 PMC/XMC Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

C.1.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145C.1.2 Mounting of PMC or XMC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145C.1.3 Secondary Thermal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

C.2 Installing HD-ADAP8 SATA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Publication No. 500-9300007876-000 Rev. C.0 Table of Contents 13

D • Processor Speed and Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149D.1 Quad Core (i7-4700EQ) 47 W, 2.4 GHz Processor Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

E • Statement of Volatility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150E.1 Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150E.2 Non-Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150


List of Figures

Figure 2-1 Board Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 2-2 Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2-3 Handling the Convection Cooled Heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 3-1 6U Board Insertion into a Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 5-1 XVR16 Top View Interface of Levels 1, 2, 3 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 5-2 Front Panel on XVR16 (Levels 1, 2, 3 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 5-3 DisplayPort Front Panel Connector (J31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 5-4 Ethernet RJ45 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 5-5 COM3 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 5-6 USB 2.0 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 5-7 USB Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 5-8 USB 3.0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 5-9 eSATA Front Panel Port (J32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-10 PMC1 Connector Pin Assignments (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 5-11 PMC1 Connector Pin Assignments (J12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 5-12 PMC1 Connector Pin Assignments (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 5-13 PMC1 Connector Pin Assignments (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Figure 5-14 PMC2 Connector Pin Assignments (J21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 5-15 PMC2 Connector Pin Assignments (J22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 5-16 PMC2 Connector Pin Assignments (J23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 5-17 PMC2 Connector Pin Assignments (J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 5-18 XMC Connector J15 and J16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 5-19 XMC Connector (J25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 5-20 XMC Connector (J26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 6-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 6-2 PCI Express Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Figure 6-3 Power Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 8-1 Block Diagram for FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Figure 9-1 Battery Removal/Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112Figure A-1 VTM26 Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116Figure A-2 VGA Interface (P4100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117Figure A-3 Serial Interfaces COM1 and COM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118Figure A-4 Ethernet Interface 10/100/1000BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Figure A-5 USB Connectors (P1600, P1601) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120Figure A-6 eSATA5 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121Figure A-7 DMS59 Connector (P4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122Figure A-8 DMS59 Connector Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122Figure A-9 VTM26 Audio Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124Figure A-10 VTM28 Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127Figure A-11 VGA1 Interface (J31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128Figure A-12 Serial Interfaces COM1 and COM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128Figure A-13 Ethernet Interface 10/100/1000BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129Figure A-14 USB Connectors (J23, J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130Figure A-15 DMS59 Connector (J27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131Figure A-16 DMS59 Connector Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Publication No. 500-9300007876-000 Rev. C.0 List of Figures 15

Figure C-1 Mounting PMC/XMC Module onto XVR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146Figure C-2 Mounting of Secondary Thermal Interface on PMC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147Figure C-3 Installing HD-ADAP8 SATA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148


List of Tables

Table 2-1 Available Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 5-1 DisplayPort (J31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 5-2 LAN Standard GbE (J27) or Optional LAN (J34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 5-3 LEDs on LAN Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 5-4 Serial Port COM3 Connector (J28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 5-5 USB 2.0 Connector Front Panel (J29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Table 5-6 USB 3.0 Connector Front Panel (J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Table 5-7 SATAxx/eSATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 5-8 PMC1 Connector Pin Assignments (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 5-9 PMC1 Connector Pin Assignments (J12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 5-10 PMC1 Connector Pin Assignments (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 5-11 PMC1 I/O Connector Pin Assignments (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 5-12 PMC2 Connector Pin Assignments (J21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 5-13 PMC2 Connector Pin Assignments (J22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 5-14 PMC2 Connector Pin Assignments (J23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 5-15 PMC2 I/O Connector Pin Assignments (J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Table 5-16 XMC1 Connector Pin Assignments (J15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 5-17 XMC1 Connector Pin Assignments (J16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Table 5-18 XMC2 Connector Pin Assignments (J25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 5-19 XMC2 I/O Connector Pin Assignments (J26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 5-20 VMEbus Connector P0 with Full PMC I/O (Ordering Option G = 1 or 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 5-21 VMEbus Connector P0 with Limited PMC I/O (Ordering Option G = 0 or 3) . . . . . . . . . . . . . . . . . . . . . . 59Table 5-22 VMEbus Connector P0 with Partial PMC I/O (Ordering Option G = 2 or 5) . . . . . . . . . . . . . . . . . . . . . . .60Table 5-23 VMEbus Connector P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 5-24 VMEbus Connector P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 6-1 Interval Timer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 6-2 IPMB Backplane Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 6-3 SMBus Backplane Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Table 6-4 Front BIT Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Table 7-1 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 7-2 Standard Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 7-3 Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Table 8-1 XVR16 FPGA Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 8-2 Board ID Register (0x600) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Table 8-4 FPGA Revision Register (0x60B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 8-5 Watchdog Timer (WDT) Refresh (0x60D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 8-6 Watchdog Timer Control/Status Register (CSR) LSB (0x60E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 8-7 Watchdog Timer Control/Status Register (CSR) MSB (0x60F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 8-8 Board ID String Registers (0x610 - 0x61A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 8-3 Board Revision Register (0x601) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 8-10 Reset Cause Register 2 (0x617) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 8-11 BMM/BMC Control Register (0x620) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 8-9 Reset Cause Register 1 (0x616) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 8-12 LED Control Register (0x622) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Publication No. 500-9300007876-000 Rev. C.0 List of Tables 17

Table 8-13 BIOS/SPI Control Register (0x625) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 8-14 BIT Control/Status Register (0x629) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Table 8-15 NVRAM Memory Space Page Register (0x635) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Table 8-16 Timer 0 Control and Status Register 1 (CSR1) (0x650) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 8-17 Timer 0 Control and Status Register 2 (CSR2) (0x651) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 8-18 Timer 0 IRQ Clear Register (0x652) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 8-19 Timer 0 Data Byte 0 (LSB) (0x654) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 8-20 Timer 0 Data Byte 1 (0x655) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 8-21 Timer 0 Data Byte 2 (0x656) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 8-22 Timer 0 Data Byte 3 (MSB) (0x657) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 8-23 Timer 1 Control and Status Register 1 (CSR1) (0x658) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Table 8-24 Timer 1 Control and Status Register 2 (CSR2) (0x659) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Table 8-25 Timer 1 IRQ Clear Register (0x65A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 8-26 Timer 1 Data Byte 0 (LSB) (0x65C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 8-27 Timer 1 Data Byte 1 (0x65D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 8-28 Timer 1 Data Byte 2 (0x65E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 8-29 Timer 1 Data Byte 3 (MSB) (0x65F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 8-30 GPIO 7-0 OUT Register (0x670) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 8-31 GPIO 7-0 IN Register (0x671) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 8-32 GPIO 7-0 Direction Register (0x672) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 8-33 GPIO 7-0 Interrupt Enable Register (0x673) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 8-34 GPIO 7-0 Interrupt Level/Edge Register (0x674) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 8-35 GPIO 7-0 Interrupt Active High/Low Register (0x675) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 8-36 GPIO 7-0 Both-Edge Register (0x676) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 8-37 GPIO 7-0 Interrupt Status Register (0x677) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 8-38 GPIO 7-0 Availability Register (0x678) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Table 8-39 GPIO 15-8 OUT Register (0x67C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Table 8-40 GPIO 15-8 IN Register (0x67D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Table 8-41 GPIO 15-8 Direction Register (0x67E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 8-42 GPIO 15-8 Interrupt Enable Register (0x67F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 8-43 GPIO 15-8 Interrupt Level/Edge Register (0x680) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 8-44 GPIO 15-8 Interrupt High/Low Register (0x681) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 8-45 GPIO 15-8 Both-Edge Register (0x682) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 8-46 GPIO 15-8 Interrupt Status Register (0x683) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 8-47 GPIO 15-8 Availability Register (0x684) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 8-48 Ethernet Port Availability Register (0x6A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 8-49 COM Port Availability Register (0x6A1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 8-50 COM Port Wire Configuration Register (0x6A2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 8-51 COM Port Full Modem Line Configuration Register (0x6A3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 8-52 SATA Port Availability Register (0x6A4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 8-53 USB 2.0 Port 7-0 Availability Register (0x6A5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 8-54 USB 3.0 Port 7-0 Availability Register (0x6A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 8-55 USB 2.0 Port 15-8 Availability Register (0x6A7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Table 8-56 USB 3.0 Port 15-8 Availability Register (0x6A8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Table 8-57 Display Availability Register (0x6A9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Table 8-58 VGA Display Availability Register (0x6AA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Table 8-59 DisplayPort Availability Register (0x6AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Table 8-60 Ancillary/Audio Availability Register (0x6AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101Table 8-61 Front Panel Configuration Register (0x6AE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101Table 8-62 XMC/PMC1 I/O Configuration Register (0x6AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102


Table 8-63 XMC/PMC2 I/O Configuration Register (0x6B0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102Table 8-64 SSD Availability Register (0x6B1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Table 8-65 SSD Hardware Secure Erase Availability (0X6B2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Table 8-66 UART Enable Register (0x6B8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Table 8-67 COM Port Transceiver Enable Register (0x6BB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Table 8-68 COM Port Mode Register (0x6BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Table 8-69 COM Port RS485 Auto Direction Control Enable Register (0x6BD) . . . . . . . . . . . . . . . . . . . . . . . . . . . .104Table 8-70 COM Port Loopback Enable Register (0x6BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104Table 8-71 SSD Erase Control Register (0x6BF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104Table 8-72 SSD Cache Flush Control Register (0x6C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104Table 8-73 Scratch Pad Register (0x6C6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105Table 8-74 PMC1/XMC1 Status Register (0x6C8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105Table 8-75 PMC2/XMC2 Status Register (0x6C9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106Table 8-76 SSD Status Register (0x6CB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106Table 8-77 Write Protection Status Register (0x6CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107Table 8-78 Board Jumper/Link Status Register (0x6CD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107Table 8-79 Board Location Status Register (0x6CE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108Table 8-80 Thermal Status Register (0x6D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108Table 8-81 Thermal Alarm Status Register (0x6D1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108Table 9-1 Levels Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109Table 9-2 CPU Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110Table 9-3 Battery Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111Table 9-4 +5VSTDBY Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113Table 9-5 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113Table 9-6 Maximum Altitude Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114Table 9-7 Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114Table 9-8 Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114Table 9-9 GPIO IN Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115Table 9-10 GPIO OUT Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115Table A-1 VGA1 Interface (P4100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117Table A-2 VTM26 VGA2 (P4300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117Table A-3 VTM26 COM1 (P2100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118Table A-4 VTM26 COM2 (P2200, P2201) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Table A-5 VTM26 Ethernet Connectors (P5300, P5400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Table A-6 VTM26 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120Table A-7 VTM26 USB0 (P1600) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120Table A-8 VTM26 USB1 (P1601) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120Table A-9 SATAxx/eSATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121Table A-10 SATA5 HD Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121Table A-11 VTM26 DMS59 Connector Digital Pin Assignments DVI1 and DVI2 . . . . . . . . . . . . . . . . . . . . . . . . . . .122Table A-12 GPIO Connector (P2002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123Table A-13 VTM26 Miscellaneous Connector (P2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124Table A-14 U1 and P2901 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124Table A-15 PMC I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125Table A-16 Rear BITFail Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126Table A-17 Rear Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126Table A-18 VGA1 Interface (J31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128Table A-19 VTM28 COM1 (J100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129Table A-20 VTM28 COM2 (P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129Table A-21 VTM28 Ethernet Connectors (J29, J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Publication No. 500-9300007876-000 Rev. C.0 List of Tables 19

Table A-22 VTM28 USB0 (J23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130Table A-23 VTM28 USB1 (J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130Table A-24 VTM28 DMS59 Connector Digital Pin Assignments for DVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131Table A-25 Mezzio Connector Rows A-J (J21/J22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133Table A-26 Mezzio Connector Rows K-T (J21/J22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134Table A-27 Rear BITFail Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135Table A-28 Rear Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135Table B-1 BIOS Firmware, First Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136Table B-2 BIOS Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137Table B-3 BIOS Advanced Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138Table B-4 BIOS Chipset Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140Table B-5 Server Mgmt Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141Table B-6 BIOS Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142Table B-7 BIOS Security Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143Table B-8 BIOS Save & Exit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144Table C-1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145Table D-1 Maximum Operating Frequency versus Max Temperature for Quad Processor . . . . . . . . . . . . . . . . . .149Table E-1 Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150Table E-2 Non-Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150


1 • Introduction

Abaco’s XVR16 rugged 6U VME SBC features the Intel 4th Generation Core i7 quad core processor (up to 6 MByte Last Level Cache) with error checking and correction (ECC) support, integrated graphics and PCIe channels. The XVR16 is also equipped with Intel’s QM87 Express Chipset that provides PCI Express (PCIe) channels, SATA, USB, graphic ports, SMBus, LPC, and SPI design.

Supported CPU

NOTECPU speed is dependent on environment. See Section D • Processor Speed and Temperature on page 149 for details.

1.1 Features

• Two channels of soldered DDR3L SDRAM with ECC up to 16 GByte

• Up to 6 MByte shared cache

• Up to 64 GByte NAND Flash

• Front I/O:

– 2x Gigabit Ethernet ports (second port is optionally available)

– 1x DisplayPort

– 2x USB ports (second port is USB 3.0 and optional)

– 1x COM port

– 1x Power button

– 1 x eSATA (optional)

• Rear I/O via Transition Module: (Actual I/O depends on option ordered)

– 2x Gigabit Ethernet ports (VITA 31.1)

– 2x Video Graphics Array (VGA)

– 2x Digital Video Interface (DVI)

– 2x SATA ports, RAID capable

– 2x COM ports

– 2x USB 2.0 ports

– 1x Audio (Line in, Line out)

– 12x General Purpose Input/Output (GPIO)

– 2x PMC rear I/O

– 2x Extended PMC (XMC) rear I/O

LINKThe VTM26 and VTM28 Transition Modules are compatible with the XVR16. See the product website for the latest available compatible RTMs for the XVR16 at: https://www.abaco.com/products/xvr16-vme-sbc

SKU Core Frequency Number of Cores Cache Size Estimated TDP Watts

i7- 4700EQ 2.4 GHz 4 6 MBytes 47

Publication No. 500-9300007876-000 Rev. C.0 Introduction 21

Other Features

• BIOS backup Flash

• Optional conduction cooling

• Optional extended operating temperature range

• Five Levels of Ruggedization

The XVR16 offers up to two onboard option dependent mezzanine expansion sites for enhanced system flexibility, both offer PMC and XMC capability.

Memory resources include up to 16 GByte DDR3 SDRAM, up to 64 GByte NAND Flash, an optional onboard SATA hard drive.

Software choices include comprehensive AXIS and Deployed Test Software (BIT

and BCS) plus OS support for Windows®, Windows 7, Linux® Open Linux, Wind

River Linux, and VxWorks®.

1.2 Software Support

The XVR16 provides 4th Generation Intel Core i7 processor with four cores with a shared memory and I/O resource pool. Customer system applications call for software platforms that support Symmetric Multiprocessing (SMP) operation as well as near real time support of independent application threads.

Generally, these different software needs require the support of multiple operating systems, and also require software driver and Board Support Packages (BSPs) to support the low level hardware functions.

1.2.1 Device Driver SupportThe XVR16 is shipped with a CD containing standard Windows Device Drivers for Chipset, Video, and Networking. These drivers have been tested with the product, and are made available for general customer use. See the ʺReadme.TXTʺ file on the CD for details and general installation instructions. Standard Drivers for Linux should be available from the release OS vendor. Drivers for other specific XVR16 functions are available by purchasing the applicable OS Software Support Package from Abaco.

1.2.2 BIOS Infrastructure SupportXVR16 uses AMI UEFI that includes BIOS firmware which provides all functions required by the processor core and chipset. This package also includes the onboard hardware initialization code that is executed following release from reset.

The BIOS also provides ROM code that supports remote booting from any of the Ethernet ports.

1.2.3 Target Operating SystemsThe XVR16 hardware supports Windows, Linux, and VxWorks operating systems.

Please contact local sales and support services for the most current operating system version information.


Power Requirements

• +5, +3.3 V

• +/-12 V mezzanine only

Mechanical

• 6U, 1 slot (4 HP), conduction cooled, IEEE 1101.2-1992 compliant

Shock and Vibration

• Stiffener bars and wedge locks are available, depending on board level

See Chapter 9 • Specifications on page 109 for further details on the physical/ environmental attributes of the XVR16.

Publication No. 500-9300007876-000 Rev. C.0 Unpacking and Handling 23

2 • Unpacking and Handling

2.1 Available Accessories

The following table lists accessories that are available for the XVR16:

NOTE*The Transition Module is used for Build Levels 1 and 2 only.**The Transition Module is used for Build Level 1 only.

2.2 Unpacking/Handling Warnings

Any precautions found in the shipping container should be observed. All items should be carefully unpacked and thoroughly inspected for damage that might have occurred during shipment. The board(s) should be checked for broken components, damaged printed circuit board(s), heat damage and other visible contamination. All claims arising from shipping damage should be filed with the carrier and a complete report sent to Abaco Systems Technical Support. See About this Manual section.

2.2.1 Electrostatic Discharge (ESD)The discharge of static electricity, known as Electrostatic Discharge or ESD, is a major cause of electronic component failure. The XVR16 has been packed in a static safe bag which protects the board from ESD while the board is in the bag. Before removing the XVR16 or any other electronic product from its static safe bag, be prepared to handle it in a static safe environment.

A properly functioning antistatic strap should be worn and the handler should be fully grounded. Any surface upon which you place the unprotected XVR16 should be static safe, usually facilitated by the use of antistatic mats. From the time the board is removed from the antistatic bag until it is in the card cage and functioning properly, extreme care should be taken to avoid damaging the board with ESD. Damage to the board can occur from an imperceptibly small discharge. Extra caution should be taken in cold and dry weather when static easily builds.

Table 2-1 Available AccessoriesItem Purpose

VTM26* Transition Module, 6U x 4HE/HP

VTM28** Transition Module, 6U x 4HE/HP

YLB-CR12-01 10 pin har-Link® to COM Port Sub-D 9 pins adapter cable (Convection cooled only)


CAUTIONSome of the components assembled on Abaco products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to a high energy electrostatic field. When the board is placed on a bench for configuring, etc., it is suggested that conductive material be inserted under the board to provide a conductive shunt. Unused boards should be stored in the same protective boxes in which they were shipped.

WARNINGUse extreme caution when handling, testing and adjusting this equipment. This device may operate in an environment containing potentially dangerous voltages. Ensure that all power to the system is removed before installing any device. To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground. If AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must meet IEC safety standards.

WARNINGThis is an FCC Class A product for use in an industrial environment. In a home or residential environment, this product may cause radio interference in which case the user may be required to take adequate measures.

NOTEDrain static electricity before you install or remove any parts. Installing or removing modules without observing this precaution could result in damage to this and/or other modules in your system.

2.2.2 Unpacking the BoardPlease read the Manual carefully before unpacking the board or module or installing the device into your system. Also, adhere to the following:

1. Observe all precautions for electrostatic sensitive modules.

2. If the product contains batteries, do not place the board on conductive surfaces, antistatic plastic, or sponge, which can cause shocks and lead tobattery or board trace damage.

3. Do not exceed the specified operational temperatures.

NOTEBatteries and storage devices might also have temperature restrictions.

4. Keep all original packaging material for future storage or warranty shipments of the board.

2.2.3 Inspect PackageAlthough the XVR16 is carefully packaged to protect it against the rigors of shipping, it is possible shipping damages can occur.

After unpacking the XVR16, if damage is observed (usually in the form of bent component leads or loose socketed components), contact Abaco for additional instructions. Depending on the severity of the damage, it may be necessary to return the product to the factory for repair.

CAUTIONDO NOT apply power to the board if it has visible damage. Doing so may cause further, possibly irreparable damage, as well as introduce a fire or shock hazard.


Figure 2-1 Board Packaging

Retain all packing material in case of future need.


2.3 Handling Precautions

Proper handling of the board or module is critical to ensure proper operation and long term reliability. When unpacking the board, and whenever handling it thereafter, be sure to handle the board by the front panel as shown. Do not handle the board by the circuit card edges, the heat sink, or the connectors.

Figure 2-2 Handling the Board

CAUTIONHandle the board by the edges or front panel only.

2.3.1 Handling the Board1. Ensure that both the person handling the board and the surrounding area

are protected from ESD.

2. Carefully remove the board or module from the shipping carton by graspingit by the front panel and the connectors.

3. Place the board, in its antistatic bag, flat, down on a suitable surface.

4. Remove the board from the antistatic bag by tearing the ESD warning labels.


2.3.2 Handling the Convection Cooled HeatsinkUse the handles on the Front Panel when handling.

Figure 2-3 Handling the Convection Cooled Heatsink

CAUTIONUtilizing the heatsink as a handle or handling the board and putting pressure on the heatsink could lead to performance degradation or permanent damage. Always use the handles provided on the Front Panel.

2.3.3 Installation and Power-Up/ResetA reset button is located at the front and rear. Please review the Safety Summary on page 9 before installing the XVR16.

CAUTIONEnsure that the XVR16's power requirements are compatible with those supplied by the backplane. The XVR16 power requirements are up to 60 W across the 5 V, 12 V and 3.3 V rails. See Section 9.5 Electrical Characteristics on page 114.


3 • Installation

This chapter describes the installation of the XVR16 VME Single Board Computer on a VME backplane and initial power-on operations.

3.1 Installation Preparation

Observe all safety procedures to avoid damaging the system and to protect operators and users. Use the following steps to install your Abaco hardware.

1. Ensure that the system power and external supplies have been turned offbefore installing or removing any board.

2. Check that the jumpers and mezzanines are correctly configured for yourapplication.

3. Mount the board/mezzanine/transition module carefully. If applicable, seesection C.1.2 Mounting of PMC or XMC Module.

4. Connect all IO cables.

5. Restore the power once it is certain that all modules are correctly fitted intothe system and all connections have been made properly.

3.1.1 VMEbus ProductsOn a standard VMEbus backplane, remove the jumpers on the IACKIN -IACKOUT interrupt daisy-chain (1 jumper) and on the BGxIN - BGxOUT bus grant daisy-chains (4 jumpers) for the slot where the board is to be mounted. The daisy-chain jumpers on the VMEbus backplane should be mounted on all free slots.

Setting jumpers is not necessary for the Abaco Auto-Daisy-Chain VMEbus backplane.

A board with system controller functionality must be fitted into slot 1.

The backplane must supply +3.3 V and +5 V.

Because the board is available in several options, the description in this chapter is related to the standard configuration. Mount the CPU board carefully in the VME slot.

3.1.2 Replacing/Disposing of BatteriesThere is danger of explosion if the battery is incorrectly replaced. Replace only with the same or equivalent type recommended by Abaco.

Dispose of used batteries according to instructions of Abaco and applicable local regulations. See Section 9.2 Onboard Lithium Battery on page 111.

Publication No. 500-9300007876-000 Rev. C.0 Installation 29

3.2 Required Items

The following items are required to start the XVR16 in a standard configuration.

3.2.1 Backplane and Power SupplyA standard VME backplane, wired into a regulated power supply capable of providing stable low noise +5 V and +3.3 V sources, is required. Make sure that the supply is capable of meeting the total power requirements of the XVR16. See Section 9.5.1 Supply Voltage Range on page 114 for details.

Initially, you may plug the board into your 6U system slot of your VMEbus system. Make sure the power supply is OFF while plugging the board into the backplane.

3.2.2 Keyboard and MouseA compatible keyboard for initial system operation is required. Depending on the application, this keyboard may be a standard keyboard, or one which utilizes membrane switches for harsh environments. The keyboard is attached via a USB connector.

3.2.3 Video MonitorThe XVR16 offers front panel access to the video signal through the DP (DisplayPort). Video is also available via the P2/P0 VME connector. In order to gain access to these pins, it is necessary to use the transition module VTM26 or VTM28.

3.2.4 Minimum System RequirementsThe XVR16 has been thoroughly tested and is ready for use in the target system. In order to verify XVR16 operation for the first time, it is suggested to configure a minimal system only. It is not necessary to have disk drives, a Flash disk or other accessories connected in order to perform the XVR16 Power-On Self Test (POST).


3.2.5 POSTEach time the computer boots up it must pass the POST. The following is the procedure of the POST:

• The first step of POST is the testing of the Power Supply to ensure that it isturned on and that it releases its reset signal

• CPU must exit the reset status mode and thereafter be able to executeinstructions

• UEFI Firmware is readable

• UEFI Firmware checksum must be valid, meaning that it must be readable

• CMOS RAM is readable

• CPU must be able to read all forms of memory such as the memorycontroller, memory bus, and memory module

• The first 1 MByte of memory must be operational and have the capability tobe read and written to and from, and capable of containing the POST code

• I/O bus / controller must be accessible

If the computer passes all POST, then the UEFI video banner will be displayed on the applicable video device, and the board will attempt to boot to the default storage device.

Because the boards are available in several configurations, the description in this chapter is related to the standard configuration.

Publication No. 500-9300007876-000 Rev. C.0 Installation 31

3.3 Installing XVR16 into Chassis

Boards are installed in a VME chassis by:

1. Sliding the board carefully into the guide rails

2. Inserting the board all the way until the handles can be operated to seat andlock the board in place. Handles typically have a lock (snap lever) to unlockthem when extracting a board

Older boards may have screws instead of handles to secure the board in place.

Figure 3-1 6U Board Insertion into a Chassis

3.4 Installation of the Rear Transition Module (VTM26 or VTM28)

The VTM26 or VTM28 is a 6U x 80 mm rear I/O module which plugs into the XVR16 separated by the backplane. These transition modules have a DVI or VGA connector which can be used for monitor connection.

Plug the monitor into this connector. Make sure that the selected chassis supports this type of rear I/O transition module.

After ensuring that the XVR16 is properly installed into the VME backplane, apply power to the monitor and then the VME supply. When the board is completely reset, the processor should begin executing initial UEFI Firmware resident routines.

NOTEIf the XVR16 was ordered without video onboard, you can use an external video VME card or a video PMC module. Consult the technical descriptions of these boards for required voltage and power consumption in the system.


3.5 Initial Power-On Operation

After a few seconds, the XVR16 system UEFI firmware banner will display on the screen. Display of all on-screen messages indicates the board is running properly and is ready to be installed and set up for application.

3.6 Entering the UEFI Firmware SETUP

To enter SETUP during the initial power-on sequence:

• Press the DELETE key during the boot up sequence. Also see the applicableon-screen messages when prompted. See Appendix B BIOS Setup Utility.

LINKConsult the User's Manual www.ami.com for AMI UEFI Firmware Setup for further information onhow to change settings and configurations.

If the board does not perform as described above, damage may have occurred in shipping or the board is not installed or setup properly. Contact Abaco technical support as described in the About This Manual section.

http://www.ami.com

Publication No. 500-9300007876-000 Rev. C.0 Power-up/Booting 33

4 • Power-up/Booting

4.1 Power Supply

For exact power supply values, see Section 9.1 Power Consumption on page 110. For rough data, a current of up to 9.5 A at the 5 V rail and 3.5 A at the 3.3 V rail must be taken into consideration for a basic XVR16 power on. (Typical values, and does not include backplane termination power, or external drive power.) The XVR16 does not use +/-12 V but they are provided to the PMC connectors for the mezzanine which uses these voltages. If there are hard disk or PMC modules attached to the XVR16, their power consumption must also be calculated. Standard power supplies often require minimum loads on every supply voltage for proper operation. It may be necessary to add a load to the +12 V to ensure correct voltage levels on 3.3 V and 5 V.

If there are problems starting the board or doing resets at random states, check the voltage of the two supply voltages at the backplane. Attach a standard digital multimeter to the backplane at positions where no high current is flowing.

It is advisable to use rear contacts of the bus connectors or unused power connectors for measuring. Measuring the voltages at the used power connectors can result in wrong values which are caused by the high current flowing.

The 5 V and 3.3 V should reach their nominal value when measuring with a multimeter. If the voltages are less than 5.0 V or 3.3 V, when the CPU or memory perform intensively the voltage may drop causing the XVR16 to reset.

4.2 Setup

To enter the UEFI Firmware Setup, press the keyboard <DEL> or <F2> key at the right moment. When using a slow starting monitor, it is advisable not to wait for the CRT to show the message ʹPress DEL to enter Setupʹ. When using add-on cards with external Option ROMʹs UEFI Firmware, press the DEL, F2 key while their program runs.

If the right moment was missed to press the <DEL> or <F2> key, use the power button on the front panel to restart the power up sequence or switch off the power supply for a few seconds and restart it.

4.2.1 Clear CMOS/RTC/Password

NOTEThe BIOS has the capability of password protecting casual access to the unit’s CMOS setup screens. Clearing the CMOS allows the user to clear the password in case of a forgotten password. This also clears all CMOS settings and restores factory defaults.

To clear the CMOS password:

1. Turn off power to the unit.

2. Remove the board from the chassis.

3. Remove the onboard lithium battery for one minute. See Section 9.2.2Battery in Vertical Holder; Removal/Replacement on page 112.


4.2.2 BIOS SetupThe XVR16 has an onboard BIOS Setup program that controls many configuration options. These options are saved in a special non-volatile memory area and are collectively referred to as the board’s CMOS Configuration. The CMOS contents are preserved as long as battery power is applied to the VBAT pin on the VME backplane or the onboard battery is installed. (Refer to Section 9.2 Onboard Lithium Battery on page 111.) The CMOS configuration controls many details concerning the behavior of the hardware from the moment power is applied. To clear BIOS settings to factory defaults, refer to Section 4.2.1 Clear CMOS/RTC/Password on page 33.

Details of the XVR16 BIOS setup program are included in B • BIOS Setup Utility.

NOTEThe BIOS referred to in this Manual is an EFI BIOS.

CAUTIONBattery backup of critical CMOS settings is provided by the system via the VBAT signal on the VME backplane. If the board is removed from the backplane, these settings will be lost if no battery is installed onboard.

4.3 Unexpected Resets

A set of special registers is implemented onboard to locate the reset source in the event the XVR16 unexpectedly issues a reset and starts booting again. For every reset source set, there is a special bit that can be read in the next boot up. See Table 8-9, Reset Cause Register 1 (0x616) and Table 8-10 , Reset Cause Register 2 (0x617), on page 87.

4.4 Remote Ethernet Booting

The XVR16 is capable of booting from a server using the 10/100/1000 Mbit Ethernet ports over a network utilizing the Intel Boot Agent. The Intel Boot Agent provides the ability to remotely boot the XVR16 using the PXE protocol. This feature allows users to create systems ensuring disk drive reliability, without the extra cost of adding NAND Flash drives.

Publication No. 500-9300007876-000 Rev. C.0 Connectors 35

5 • Connectors

This chapter describes the connectors and the pin assignments of the XVR16 located at the front panel, onboard and at the backplane.

Figure 5-1 XVR16 Top View Interface of Levels 1, 2, 3 Version

U103

Tsi148

XMC1

PMC1

PMC1

SATASSD1

Battery

SATA SSD2

IntelLynx PointI/O HubIntel

HaswellCPU

LAN

COM3

USB2USB3

(optional)LAN

(optional)eSATA

(optional)

U9

U194

J33

J31J27

DisplayPort

J28 J29

4

5 9J30

U10

S1

P3

P6

P4

XBT1

U191U190

U174

U173

J34

J32

J15

J11

J16

J12

J13

J14

J21

PMC1

PMC2 PMC1J23

J24 J22

PMC2

PMC2 PMC2

J25J26 XMC2 XMC2 XMC1

P4: CMOS Clear Jumper

P6: Onboard Hardware Write Protect Jumper

ETH3

P1P2 P0

64

63 1163

264

64

63

1

1

2

63

64

641

2

63

6363

63

2

2

2

641

1

1

2

264

64

F1E1D1C1B1A1

F19E19D19C19B19A19

U35

U31

U30

U29

U34U36

U37

U32

U25

U33

U20

U21

U27

U26

U24

U23

U28

U22

DRAM

1

5

XDP DebugPort

P3: Flash Descriptor Security Override Jumper

P7

Note: USB3, LAN and eSATA are options in place of PMC2

PowerSwitch

Note: USB3, LAN and eSATA are options in place of PMC2

ClarksvilleEthernet

CODECAudio

P8P8: Backup BIOS Jumper

Reserved


5.1 Front Panel InterfaceThe following drawing illustrates the location of interfaces on the front panel of the XVR16 board. The front panel is available only on Levels 1, 2, and 3 versions.

Figure 5-2 Front Panel on XVR16 (Levels 1, 2, 3 Only)

NOTE*See your Sales Representative for BIT availability.

USB 3.0USB 3.0

LAN (See LAN Link Activity/Speed)

LAN

eSATA

PMC1/XMC1

USB 2.0

COM3 - Communications port (RS232 serial link interface)

Ethernet Activity: L - Blinks green when the Ethernet is linked and active.It remains steady if the Ethernet is linked, with no activity.

Ethernet Speed: S - Indicates at which speed the Ethernet is running:10BASE-T: LED is off100BASE-TX: Green LED1000BASE-T: Amber LED

DP DisplayPort - Two-lane DisplayPort to VGA adapter 3.6

PMC1/XMC1

PMC2/XMC2

USB 2.0

COM3

LAN

DP

Single PMC FP OptionDual PMC FP Option

*BIT LEDS

COM3

PMC1/XM

C1

PMC1/XM

C1

PWR

ResetSTDBY

STDBY

PMC2/XM

C2

BitOK

BitOK

LAN

LAN

Front Panel LEDs: 1x All Power Good: Green LED1x Reset Status: Red LED1x Standby Power Good: Green LED1x BIT Pass: Green LED2x BIT Status: Yellow LEDs1x BIT Fail: Red LED

BitST

BitST

PWR

ResetLAN

PWR

Button

PWR

Button

eSATA


5.2 Front Panel Connectors

The XVR16 Front Panel I/O is included in Levels 1, 2, and 3 with the following interface:

– DisplayPort, GbE, COM3, USB 2.0, dual PMC/XMC, Power Button

– USB 3.0, GbE, eSATA, (optional) in place of PMC2

– LEDs: Power, Reset, BIT Pass, 2x BIT Status/user programmable, BIT FailLEDs

5.2.1 DisplayPort The front panel DisplayPort is one of the four graphic ports available on the XVR16. The front panel DisplayPort is a single, horizontal 20-pin connector that connects to an adapter/cable. For further information on the other video display types that are routed out the backplane, see Section 6.4 Graphics Controller.

Figure 5-3 DisplayPort Front Panel Connector (J31)

Table 5-1 DisplayPort (J31) Pin Signal Pin Signal

1 DPB_LANE0_P 11 GND

2 GND 12 DPB_LANE3_N

3 DPB_LANE0_N 13 AUX_EN_N

4 DPB_LANE1_P 14 GND

5 GND 15 DPB_AUX_P

6 DPB_LANE1_N 16 GND

7 DPB_LANE2_P 17 DPB_AUX_N

8 GND 18 DPB_HPD

9 DPB_LANE2_N 19 GND

10 DPB_LANE3_P 20 3.3 V

2

1

20

19


5.2.2 Ethernet Interface RJ45The XVR16 has up to four Gigabit Ethernet (GbE) channels.

• The XVR16 can have up to two Gigabit RJ45 based Ethernet ports at the frontpanel. The bottom GbE port LAN is always available for Level 1, 2, and 3.The top GbE port LAN is available for Level 1, 2, and 3 when the XMC/PMCsite 2 is not chosen as an option.

• Two GbE channels (ETH3 and ETH4) are routed out the backplane to P0 andare always available.

Figure 5-4 Ethernet RJ45 Interface

Table 5-2 LAN Standard GbE (J27) or Optional LAN (J34)

Two LEDs (LED1-green and LED2-yellow) are integrated in each of the RJ45 connectors. These LEDs indicate the link status of the interface.

LAN 10/100BASE-T 1000BASE-T

1 TxD+ MDI0+

2 TxD- MDI0-

3 RxD+ MDI1+

4 NC MDI2+

5 NC MDI2-

6 RxD- MDI1-

7 NC MDI3+

8 NC MDI3-

Table 5-3 LEDs on LAN Connectors LED Function

LED1 Green (Left)

On Link

Off No link

LED2 Yellow (Right)

On, blink Tx/Rx activity

Off No activity


5.2.3 Serial Port COM3 (J28)The XVR16 offers three serial ports. COM3 is accessible via the front panel connector and is RS232 only. A short custom har-Link adapter cable is available to convert the 10-pin har-Link connector to a standard Sub-D9 connector (Part No. YLB-CR12-01).

Figure 5-5 COM3 Location

Table 5-4 Serial Port COM3 Connector (J28) har-Link Connector RS232 DSUB Male Connector

A1 RXD 2

B1 TXD 3

C1 RS232 driver disablea N/A

D1 DTR 4

E1 DSR 6

A2 RTS 7

B2 RI 9

C2 GND 5

D2 CTS 8

E2 DCD 1a A low on this signal disables this port

E2 E1

A1A2


5.2.4 USB 2.0 Interface (J29)USB 2.0 is available at the front panel. Two USB 2.0 ports are available on the rear I/O at P2.

Figure 5-6 USB 2.0 Port

Figure 5-7 USB Pin Locations

Table 5-5 USB 2.0 Connector Front Panel (J29) Pin Name

1 VCCa

2 USB-

3 USB+

4 GNDa This pin is currently limited at 1.5A. For normal operation, do not exceed 1A current.

1 4


5.2.5 USB 3.0 Interface, Optional (J30)The J30 connector is an optional USB 3.0 Standard A connector. It is completely backward compatible with the USB 2.0 Standard A connector with additional pins provided for USB 3.0 high speed differential signals.

The USB 3.0 connector is available only when the XMC/PMC site 2 is not chosen as an option.

Figure 5-8 USB 3.0 Interface

Table 5-6 USB 3.0 Connector Front Panel (J30)

NOTEa This pin is currently limited at 1.5A. For normal operation, do not exceed 1A current.

5.2.6 LAN, Optional (J34)See Section 5.2.2 Ethernet Interface RJ45.

Pin Name

1 VCCa

2 USB-

3 USB+

4 GND

5 USB_RX-

6 USB_RX+

7 GND

8 USB_TX-

9 USB_TX+


5.2.7 eSATA Interface, Optional (J32)The J32 connector is an optional eSATA connector capable of GEN3 signaling. The eSATA connector is available only when the XMC/PMC site 2 is not chosen as an option.

Figure 5-9 eSATA Front Panel Port (J32)

Table 5-7 SATAxx/eSATA

5.3 Onboard Connectors

5.3.1 PMC I/O OptionsThere are specific versions of PMC plug-on modules which require specific pin assignments on the VME connectors to be able to use the PMC I/O options and to avoid damage to the XVR16.

See Mezzanine Sites.

5.3.2 PMC1 Connectors (J11, J12, J13, J14)The following tables list the pin assignments of the onboard PMC1 connectors (J11, J12, J13, J14). The PMC1 slot is 64-bit, up to PCI-X 133 MHz capable and works with a PCIe-PCI bridge (Pericom PI7C9X130). The PCI bridge and PMC1-bus are disabled when a PMC card is not installed or an XMC card is installed at this slot. PMC disabling can be overruled by UEFI Firmware Setup adjustments. The PCI Signaling voltage is fixed at +3.3 V.

LINKSee the User Manual for AMI UEFI Firmware Setup. www.ami.com.

The PMC is electrically and mechanically compliant to specification IEEE 1386 and 1386.1 with enhancements of the Processor PMC Standard VITA 32-2003. These enhancements provide pins for a secondary agent; (IDSELB and REQB/ GNTB) but do not support a monarch PMC card.

Pin Name

2 SATA_TX+

3 SATA_TX-

5 SATA_RX-

6 SATA_RX+

1, 4, 7 GND

7 1

http://www.ami.com


Legend for PMC Tables

\ Active Low Signal

NC Not Connected

Reserved Do not connect anything

V(I/O) I/O Voltage, connected with +3.3 V


Figure 5-10 PMC1 Connector Pin Assignments (J11)

Table 5-8 PMC1 Connector Pin Assignments (J11) Signal Pin Pin Signal

TCK 01 02 -12 V

GND 03 04 \PMC1INTA

\PMC1INTB 05 06 \PMC1INTC

\PRESENT 07 08 +5 V

\PMC1INTD 09 10 Reserved

GND 11 12 PCI-RSVD/+3V3

PCICLK 13 14 GND

GND 15 16 \GNT0

\REQ0 17 18 +5 V

V(I/O) 19 20 AD31

AD28 21 22 AD27

AD25 23 24 GND

GND 25 26 \CBE3

AD22 27 28 AD21

AD19 29 30 +5 V

V(I/O) 31 32 AD17

\FRAME 33 34 GND

GND 35 36 \IRDY

\DEVSEL 37 38 +5 V

PCIXCAP 39 40 \LOCK

SDONE 41 42 SB0

PAR 43 44 GND

V(I/O) 45 46 AD15

AD12 47 48 AD11

AD9 49 50 +5 V

GND 51 52 CBE0

AD6 53 54 AD5

AD4 55 56 GND

V(I/O) 57 58 AD3

AD2 59 60 AD1

AD0 61 62 +5 V

GND 63 64 \REQ64




+12 V 01 02 TRST

TMS 03 04 TDO

TDY 05 06 GND

GND 07 08 Reserved

Reserved 09 10 Reserved

PUP a 11 12 +3.3 V

PCIRST# 13 14 PDN1 a

+3.3 V 15 16 PDN 2a

\PME 17 18 GND

AD30 19 20 AD29

GND 21 22 AD26

AD24 23 24 +3.3 V

IDSEL) 25 26 AD23

+3.3 V 27 28 AD20

AD18 29 30 GND

AD16 31 32 \CBE2

GND 33 34 IDSELB

\TRDY 35 36 +3.3 V

GND 37 38 \STOP

\PERR 39 40 GND

+3.3 V 41 42 \SERR

\CBE1 43 44 GND

AD14 45 46 AD13

M66EN 47 48 AD10

AD8 49 50 +3.3 V

AD7 51 52 \REQB

+3.3 V 53 54 \GNTB

Reserved 55 56 GND

Reserved 57 58 Reserved/ERDY

GND 59 60 Reserved/RSTOUT

\ACK64 61 62 +3.3 V

GND 63 64 Reserved/MONARCHa Weak (330R) pull-down (PDN) to GND or 4.7k pull-up (PUP) to VIO.




Reserved 01 02 GND

GND 03 04 /CBE7

/CBE6 05 06 /CBE5

/CBE4 07 08 GND

V(I/O) 09 10 PAR64

AD63 11 12 AD62

AD61 13 14 GND

GND 15 16 AD60

AD59 17 18 AD58

AD57 19 20 GND

V(I/O) 21 22 AD56

AD55 23 24 AD54

AD53 25 26 GND

GND 27 28 AD52

AD51 29 30 AD50

AD49 31 32 GND

GND 33 34 AD48

AD47 35 36 AD46

AD45 37 38 GND

V(I/O) 39 40 AD44

AD43 41 42 AD42

AD41 43 44 GND

GND 45 46 AD40

AD39 47 48 AD38

AD37 49 50 GND

GND 51 52 AD36

AD35 53 54 AD34

AD33 55 56 GND

V(I/O) 57 58 AD32


Reserved 61 62 GND

GND 63 64 Reserved


5.3.3 PMC1 I/O Connector (J14)PMC1 I/O are daisy chained between XMC1 connector J16, PMC1 connector J14, and the VME P0 connector. All PMC1 I/O signals are available only in the configuration with full PMC1 I/O. When full PMC1 I/O is not chosen as an option, some PMC1 I/O signals, due to being shared with SATA, DVI2, and VGA2 signals at the rear VME P0 connector, are not available for use. Ensure that the PMC1 I/O pins on the PMC module do not conflict with the shared signals.


Table 5-11 PMC1 I/O Connector Pin Assignments (J14) Signal Pin Pin Signal

XMC1_PMC1_01 1 2 PMC1IO_02

PMC1IO_03 3 4 PMC1IO_04






























5.3.4 PMC2 Connectors (J21, J22, J23, J24)PMC2 is available on the XVR16 when the PMC2/XMC2 is chosen as an option for the board ((i.e. onboard hard drive is not chosen as an option). The PMC2 is in the non-edge slot. The PCI signaling voltage is fixed to 3.3 V.

The following tables list the pin assignments of the PMC2 connectors. The PMC2 slot is 64 bit, PCI-X 133 MHz capable, and works with a PCIe-PCI bridge (Pericom PI7C9X130). The PCI bridge and PMC2-bus is disabled when the PMC card is not installed or an XMC card is installed at this slot. The PMC disabling can be overruled by UEFI Firmware Setup adjustments.

LINKSee the User Manual for AMI UEFI Firmware Setup www.ami.com.

The PMC is electrically and mechanically compliant to the specification IEEE 1386 and 1386.1 with enhancements of the Processor PMC Standard VITA 32-2003. These enhancements provide pins for a second device; (IDSELB and REQB/ GNTB) but they do not support a monarch PMC card.



Table 5-11 PMC1 I/O Connector Pin Assignments (J14) (Continued)Signal Pin Pin Signal

http://www.ami.com




TCK 01 02 -12 V

GND 03 04 \PMC2INTA

\PMC2INTB 05 06 \PMC2INTC

\PRESENT 07 08 +5 V

\PMC2INTD 09 10 PCI-Reserved

GND 11 12 PCI-Reserved/ 3V3

PCICLK 13 14 GND

GND 15 16 \GNT0

\REQ0 17 18 +5 V

V(I/O) 19 20 AD31

AD28 21 22 AD27

AD25 23 24 GND

GND 25 26 CBE3

AD22 27 28 AD21

AD19 29 30 +5 V

V(I/O) 31 32 AD17

\FRAME 33 34 GND

GND 35 36 \IRDY

\DEVSEL 37 38 +5 V

PCIXCAP 39 40 \LOCK

SDONE 41 42 SBO

PAR 43 44 GND

V(I/O) 45 46 AD15

AD12 47 48 AD11

AD9 49 50 +5 V

GND 51 52 CBE0

AD6 53 54 AD5

AD4 55 56 GND

V(I/O) 57 58 AD3

AD2 59 60 AD1

AD0 61 62 +5 V

GND 63 64 \REQ64




+12 V 01 02 TRST

TMS 03 04 TDO

TDI 05 06 GND

GND 07 08 Reserved


PUP a 11 12 +3.3 V

\PCIRST 13 14 PDN1a

+3.3 V 15 16 PDN2a

\PME 17 18 GND

AD30 19 20 AD29

GND 21 22 AD26

AD24 23 24 +3.3 V

IDSEL 25 26 AD23

+3.3 V 27 28 A20

AD18 29 30 GND

AD16 31 32 CBE2

GND 33 34 IDSELB

\TRDY 35 36 +3.3 V

GND 37 38 \STOP

\PERR 39 40 GND

+3.3 V 41 42 \SERR

CBE1 43 44 GND

AD14 45 46 AD13

M66EN 47 48 AD10

AD8 49 50 +3.3 V

AD7 51 52 \REQB

+3.3 V 53 54 \GNTB

Reserved 55 56 GND

Reserved 57 58 Reserved/ERDY

GND 59 60 \RSTIOUT

\ ACK64 61 62 +3.3 V

GND 63 64 MONARCHa Weak (330R) pull-down (PDN) to GND or 4.7k pull-up (PUP) to VIO.




Reserved 01 02 GND

GND 03 04 /CBE7

CBE6 05 06 /CBE5

CBE4 07 08 GND

V(I/O) 09 10 PAR64

AD63 11 12 AD62

AD61 13 14 GND

GND 15 16 AD60

AD59 17 18 AD58

AD57 19 20 GND

V(I/O) 21 22 AD56

AD55 23 24 AD54

AD53 25 26 GND

GND 27 28 AD52

AD51 29 30 AD50

AD49 31 32 GND

GND 33 34 AD48

AD47 35 36 AD46

AD45 37 38 GND

V(I/O) 39 40 AD44

AD43 41 42 AD42

AD41 43 44 GND

GND 45 46 AD40

AD39 47 48 AD38

AD37 49 50 GND

GND 51 52 AD36

AD35 53 54 AD34

AD33 55 56 GND

V(I/O) 57 58 AD32


Reserved 61 62 GND

GND 63 64 Reserved


5.3.5 PMC2 I/O Connector (J24)All PMC2 I/O are daisy chained between XMC2 connector J26, PMC2 connector J24, and the VME P2 connector. All PMC2 I/O signals are available when PMC2/XMC2 is chosen as an option for the board (i.e., onboard hard drive is not chosen as an option). Ensure that the PMC I/O pins on the PMC module do not conflict with the shared signals.


Table 5-15 PMC2 I/O Connector Pin Assignments (J24) Signal Pin Pin Signal

XMC2_PMC2_01 1 2 XMC2_PMC2_02





XMC2_PMC2_11 11 12 XMC2_PMC2_12

XMC2_PMC2_13 13 14 XMC2_PMC2_14

XMC2_PMC2_15 15 16 XMC2_PMC2_16

XMC2_PMC2_17 17 18 XMC2_PMC2_18

XMC2_PMC2_19 19 20 XMC2_PMC2_20

XMC2_PMC2_21 21 22 XMC2_PMC2_22

XMC2_PMC2_23 23 24 XMC2_PMC2_24

XMC2_PMC2_25 25 26 XMC2_PMC2_26

XMC2_PMC2_27 27 28 XMC2_PMC2_28

XMC2_PMC2_29 29 30 XMC2_PMC2_30

XMC2_PMC2_31 31 32 XMC2_PMC2_32

XMC2_PMC2_33 33 34 XMC2_PMC2_34

XMC2_PMC2_35 35 36 XMC2_PMC2_36

XMC2_PMC2_37 37 38 XMC2_PMC2_38

XMC2_PMC2_39 39 40 XMC2_PMC2_40

XMC2_PMC2_41 41 42 XMC2_PMC2_42

XMC2_PMC2_43 43 44 XMC2_PMC2_44

XMC2_PMC2_45 45 46 XMC2_PMC2_46

XMC2_PMC2_47 47 48 XMC2_PMC2_48

XMC2_PMC2_49 49 50 XMC2_PMC2_50

XMC2_PMC2_51 51 52 XMC2_PMC2_52

XMC2_PMC2_53 53 54 XMC2_PMC2_54


XMC2_PMC2_55 55 56 XMC2_PMC2_56

XMC2_PMC2_57 57 58 XMC2_PMC2_58

XMC2_PMC2_59 59 60 XMC2_PMC2_60

XMC2_PMC2_61 61 62 XMC2_PMC2_62

XMC2_PMC2_63 63 64 XMC2_PMC2_64

Table 5-15 PMC2 I/O Connector Pin Assignments (J24) (Continued)Signal Pin Pin Signal


5.3.6 XMC1 Connector (J15)The following tables list the pin assignments of the onboard XMC1 connectors. The XMC1 slot provides an x8 lane wide PCI Express interface. Only if an XMC mezzanine board is installed are the PCI express lanes muxed to the XMC slot; otherwise, these lanes are muxed to the PMC1 bridge.

The XMC1 Connectors J15 and J16 are electrically and mechanically compliant to the specification VITA 42.0 and IEEE 1386.1.

Figure 5-18 XMC Connector J15 and J16

A1A19

F19 F1

Table 5-16 XMC1 Connector Pin Assignments (J15) Pin Row A Row B Row C Row D Row E Row F

1 TX0+ TX0- +3.3 V TX1 TX1- +5 V

2 GND GND TRST GND GND XMCRSTINa

3 TX2+ TX2- +3.3 V TX3+ TX3- +5 V

4 GND GND TCK GND GND XMC1_RSTOUTb

5 TX4+ TX4- +3.3 V TX5+ TX5- +5 V

6 GND GND TMS GND GND +12 V

7 TX6+ TX6- +3.3 V TX7+ TX7- +5 V

8 GND GND TDI GND GND -12 V

9 NC NC RPS NC NC +5 V

10 GND GND TDO GND GND GA0

11 RX0+ RX0- MBIST RX1+ RX1- +5 V

12 GND GND GA1 GND GND XMC1PRESENT

13 RX2+ RX2- +3.3 V AUX RX3+ RX3- +5 V

14 GND GND GA2 GND GND BMC_SDA

15 RX4+ RX4- RPS RX5+ RX5- +5 V

16 GND GND MVMRO GND GND BMC_SCL

17 RX6+ RX6- RFU RX7+ RX7- RFU

18 GND GND RPS GND GND RPS

19 CLK+ CLK- RPS WAKE ROOT RPSa Reset driven by XVR16

b Reset driven by Mezzanine


5.3.7 XMC1 Connector (J16)XMC1 I/O are daisy chained between XMC1 connector J16, PMC1 connector J14, and the VME P0 connector. All XMC1 I/O signals are available only in the configuration with full XMC1 I/O. When full XMC1 I/O is not chosen as an option some XMC1 I/O signals, due to being shared with SATA, DVI2, and VGA2 signals at the rear VME P0 connector, are not available for use.

Table 5-17 XMC1 Connector Pin Assignments (J16) Pin Row A Row B Row C Row D Row E Row F

1 XMC1_PMC1_19 XMC1_PMC1_20 NC XMC1_PMC1_17 XMC1_PMC1_18 NC

2 GND GND NC GND GND NC






8 GND GND XMC1_PMC1_01 GND GND XMC1_PMC1_02

9 XMC1_PMC1_39 XMC1_PMC1_40 XMC1_PMC1_03 XMC1_PMC1_37 XMC1_PMC1_38 XMC1_PMC1_04











GA2 GA1 GA0

XMC1 0 0 0


5.3.8 XMC2 Connector (J25)The following table lists the pin assignments of the onboard XMC2 connectors. XMC2 is available on the XVR16 when the PMC2/XMC2 is chosen as an option for the board (i.e. onboard hard drive is not chosen as an option). The XMC2 slot provides a x4 lane wide PCI Express interface. Only if an XMC mezzanine board is installed are the PCI express lanes muxed to the XMC slot, otherwise these lanes are muxed to the PMC2 bridge.

The XMC2 is electrically and mechanically compliant to the specification VITA 61.0 and IEEE 1386.1.

Figure 5-19 XMC Connector (J25)

A1A19

F19 F1

Table 5-18 XMC2 Connector Pin Assignments (J25) Pin A B C D E F

1 TX0+ TX0- +3.3 V TX1+ TX1- +5 V

2 GND GND TRST GND GND XMCRSTINa

3 TX2+ TX2- +3.3 V TX3+ TX3- +5 V

4 GND GND TCK GND GND XMC2_RSTOUTb

5 NC NC +3.3 V NC NC +5 V

6 GND GND TMS GND GND +12 V

7 NC NC +3.3 V NC NC +5 V

8 GND GND TDI GND GND -12 V


10 GND GND TDO GND GND GA0

11 RX0+ RX0N MBIST RX1+ RX1- +5 V

12 GND GND GA1 GND GND XMC2PRESENT

13 RX2+ RX2- +3.3 V AUX RX3+ RX3- +5 V

14 GND GND GA2 GND GND BMC_SDA


16 GND GND MVMRO GND GND BMC_SCL

17 NC NC RFU NC NC RFU

18 GND GND RPS GND GND RPS

19 CLK+ CLK- RPS WAKE ROOT RPSa Reset driven by XVR16

b Reset driven by Mezzanine


5.3.9 XMC2 Connector (J26)The following table lists the pin assignments of the onboard XMC2 I/O J26 Connector. The J26 signals route to VME P2 and the PMC.

Figure 5-20 XMC Connector (J26)

A1A19

F19 F1

Table 5-19 XMC2 I/O Connector Pin Assignments (J26) Pin A B C D E F




















GA2 GA1 GA0

XMC2 0 0 0


5.4 Backplane Connectors

5.4.1 VMEbus Connector P0

Table 5-20 VMEbus Connector P0 with Full PMC I/O (Ordering Option G = 1 or 4) Pin A B C D E F

1 GND GND GND GND GND GND

2 GETH3_0+ GETH3_0- GND GETH3_2+ GETH3_2- GND




6 GETH3_ACT GETH4_ACT 3.3V GETH3_LINK GETH4_LINK GND

7 PMC1IO_05 PMC1IO_04 PMC1IO_03 PMC1IO_02 PMC1IO_01 GND












19 N/C PMC1IO_64 PMC1IO_63 PMC1IO_62 PMC1IO_61 GND Notes: 1. The LAN pin assignment is compliant to the VITA 31.1 specification Gigabit Ethernet on VME64x Backplanes. 2. Ethernet port numbering adheres to the Intel chipset signal and board BIOS/EFI numbering.

Ethernet VGA2 GND

DVI2 SATA

N/C - No Connect

Audio


Table 5-21 VMEbus Connector P0 with Limited PMC I/O (Ordering Option G = 0 or 3) Pin A B C D E F







7 PMC1IO_05 PMC1IO_04 PMC1IO_03 PMC1IO_02 LINE_IN_L GND

8 PMC1IO_10 PMC1IO_09 PMC1IO_08 PMC1IO_07 LINE_IN_R GND



11 CD_L CD_R PMC1IO_23 PMC1IO_22 LINE_OUT_L GND

12 CD_COM PMC1IO_29 PMC1IO_28 PMC1IO_27 LINE_OUT_R GND


14 VGA2_DDCD PMC1IO_39 PMC1IO_38 PMC1IO_37 PMC1IO_36 GND

15 VGA2_RED VGA2_GREEN VGA2_BLUE VGA2_HSYNC VGA2_DDCC GND

16 DVI2_TXC- DVI2_TXC+ SATA3_RX+ SATA3_RX- VGA2_VSYNC GND

17 DVI2_TX0- DVI2_TX0+ DVI2_HPD SATA3_TX+ SATA3_TX- GND

18 DVI2_TX1- DVI2_TX1+ DVI2_DDCC SATA2_RX+ SATA2_RX- GND

19 DVI2_TX2- DVI2_TX2+ DVI2_DDCD SATA2_TX+ SATA2_TX- GND Notes: 1. The LAN pin assignment is compliant to the VITA 31.1 specification Gigabit Ethernet on VME64x Backplanes. 2. Ethernet port numbering adheres to the Intel chipset signal and board BIOS/EFI numbering.

Ethernet VGA2 GND

DVI2 SATA

N/C - No Connect

Audio


Table 5-22 VMEbus Connector P0 with Partial PMC I/O (Ordering Option G = 2 or 5) Pin A B C D E F
















16 DVI2_TXC- DVI2_TXC+ SATA3_RX+ SATA3_RX- PMC1IO_46 GND

17 DVI2_TX0- DVI2_TX0+ DVI2_HPD SATA3_TX+ SATA3_TX- GND

18 DVI2_TX1- DVI2_TX1+ DVI2_DDCC SATA2_RX+ SATA2_RX- GND

19 DVI2_TX2- DVI2_TX2+ DVI2_DDCD SATA2_TX+ SATA2_TX- GND Notes: 1. The LAN pin assignment is compliant to the VITA 31.1 specification Gigabit Ethernet on VME64x Backplanes. 2. Ethernet port numbering adheres to the Intel chipset signal and board BIOS/EFI numbering.

Ethernet VGA2 GND

DVI2 SATA

N/C - No Connect

Audio


5.4.2 VMEbus Connector P1The following table lists the pin assignments of connector P1. The connector is compatible to the P1 connector of the VMEbus specifications ANSI/VITA 1 (VME64), ANSI/VITA 1.1 (VME64x), and VITA 38 (System Management).

Table 5-23 VMEbus Connector P1 Pin Z A B C D

1 /TRST VMED00 \VMEBBSY VMED08 +5 V

2 GND VMED01 \VMEBCLR VMED09 GND

3 TCK VMED02 \VMEACFAIL VMED10 Reserved

4 GND VMED03 \VMEBG0IN VMED11 Reserved

5 TDC VMED04 \VMEBG0OUT VMED12 Reserved


7 TDI VMED06 \VMEBG1OUT VMED14 Reserved


9 TMS GND \VMEBG2OUT GND \GAP

10 GND VMESYSCLK \VMEBG3IN \VMESYSFAIL \GA0

11 Reserved GND \VMEBG3OUT \VMEBERR \GA1

12 GND \VMEDS1 \VMEBR0 \VMESYSRESET

+3.3 V

13 Reserved \VMEDS0 \VMEBR1 \VMELWORD \GA2

14 GND \VMEWRITE \VMEBR2 VMEAM5 +3.3 V

15 Reserved GND \VMEBR3 VMEA23 \GA3

16 GND \VMEDTACK VMEAM0 VMEA22 +3.3 V

17 Reserved GND VMEAM1 VMEA21 \GA4

18 GND \VMEAS VMEAM2 VMEA20 +3.3 V

19 Reserved GND VMEAM3 VMEA19 SMB_SCL

20 GND \VMEIACK GND VMEA18 +3.3 V

21 Reserved \VMEIACKIN IPMB_SCL VMEA17 SMB_SDA

22 GND \VMEIACKOUT IPMB_SDA VMEA16 +3.3 V

23 Reserved VMEAM4 GND VMEA15 \SMB_ALERT

24 GND VMEA07 \VMEIRQ7 VMEA14 +3.3 V

25 Reserved VMEA06 \VMEIRQ6 VMEA13 Reserved






31 Reserved -12 V +5 V STDBY +12 V GND

32 GND +5 V +5 V +5 V +5 V


5.4.3 VMEbus Connector P2The following table lists the pin assignments of connector P2. Row B of the connector is compatible to connector P2 of the VMEbus specifications ANSI/VITA 1 (VME64) and ANSI/VITA 1.1 (VME64x).

Rows A and C are compliant to the VMEbus specifications ANSI/VITA 1 (VME64) and ANSI/VITA 1.1 (VME64x), ANSI/VITA 35-2000 chapter 2.3 ´Mapping of Single PMC-P4 to VME-P2 Rows A, C´.

5.4.4 Transition ModulesSee A • Transition Modules for interface location and connector pin assignments for the optional extension boards and transition modules.

Table 5-24 VMEbus Connector P2 Pin Z A B C D

1 USB2_1_P XMC2_PMC2_02 +5 V XMC2_PMC2_01 DVI1TXC+ / GPIO0

2 GND XMC2_PMC2_4 GND XMC2_PMC2_03 DVI1TXC- / GPIO1

3 USB2_1_N XMC2_PMC2_06 \RETRY XMC2_PMC2_05 DVI1TX0+ / GPIO2

4 GND XMC2_PMC2_08 VMEA24 XMC2_PMC2_07 DVI1TX0- / GPIO3

5 USB2_3_P XMC2_PMC2_10 VMEA25 XMC2_PMC2_09 DVI1TX1+ / GPIO4


7 USB2_3_N XMC2_PMC2_14 VMEA27 XMC2_PMC2_13 DVI1TX2+ / GPIO6


9 \HW_WP_L XMC2_PMC2_18 VMEA29 XMC2_PMC2_17 DVI1HPD _IN_L

10 GND XMC2_PMC2_20 VMEA30 XMC2_PMC2_19 \PWR_BUT

11 OC2_USB_L XMC2_PMC2_22 VMEA31 XMC2_PMC2_21 CODEC_PCBEEP

12 GND XMC2_PMC2_24 GND XMC2_PMC2_23 DDCC_DVI1/GPIO8

13 RESET_LED_L XMC2_PMC2_26 +5 V XMC2_PMC2_25 DDCD_DVI1/GPIO9

14 GND XMC2_PMC2_28 VMED16 XMC2_PMC2_27 GPIO10

15 BMC_BITFAIL_L XMC2_PMC2_30 VMED17 XMC2_PMC2_29 GPIO11

16 GND XMC2_PMC2_32 VMED18 XMC2_PMC2_31 C1_DSR

17 C1_DCD XMC2_PMC2_34 VMED19 XMC2_PMC2_33 C1_RXD

18 GND XMC2_PMC2_36 VMED20 XMC2_PMC2_35 C1_RTS

19 DDCC_VGA1 XMC2_PMC2_38 VMED21 XMC2_PMC2_37 C1_TXD

20 GND XMC2_PMC2_40 VMED22 XMC2_PMC2_39 C1_CTS

21 DDCD_VGA1 XMC2_PMC2_42 VMED23 XMC2_PMC2_41 C1_DTR

22 GND XMC2_PMC2_44 GND XMC2_PMC2_43 C1_RI

23 HSYNC1 XMC2_PMC2_46 VMED24 XMC2_PMC2_45 C2_DCD

24 GND XMC2_PMC2_48 VMED25 XMC2_PMC2_47 C2_DSR

25 VSYNC1 XMC2_PMC2_50 VMED26 XMC2_PMC2_49 C2_RXD

26 GND XMC2_PMC2_52 VMED27 XMC2_PMC2_51 C2_RTS

27 VGA1_BLUE XMC2_PMC2_54 VMED28 XMC2_PMC2_53 C2_TXD

28 GND XMC2_PMC2_56 VMED29 XMC2_PMC2_55 C2_CTS

29 VGA1_GREEN XMC2_PMC2_58 VMED30 XMC2_PMC2_57 C2_DTR

30 GND XMC2_PMC2_60 VMED31 XMC2_PMC2_59 C2_RI

31 VGA1_RED XMC2_PMC2_62 GND XMC2_PMC2_61 GND

32 GND XMC2_PMC2_64 +5 V XMC2_PMC2_63 +5 V

Publication No. 500-9300007876-000 Rev. C.0 Functional Description 63

6 • Functional Description

This Chapter describes the functions of the XVR16 built on Intel’s architecture of the Shark Bay Operating Platform consisting of the 4th Generation Core i7 Processor and the Mobile Intel QM87 Express Chipset.

The 4th Generation Core i7 processor family provides an integrated memory hub

and 2D/3D graphics controller. Enhanced Intel Turbo Boost® technology provides the ability to adjust the power and performance of the processor based on CPU and graphic demand.

The processor die is thermally protected by two thermal monitor features. When reaching a maximum safe operating temperature, the Thermal Control Circuit in the processor activates a frequency reducing feature and reduces the voltage and frequency dynamically. In case of a catastrophic die overheating (above 125 °C), the XVR16 switches off the processor core voltage. Recovery from this catastrophic event can be accomplished with a power off-on cycle or Power Button.

Figure 6-1 Block Diagram

4/8 GByte DDR3L

HARD DRIVE option

IPMI w/power

monitoring

BIOS / BIT

Backup BIOS

P0 P2 P1

GbE

Gb E

PMC/XMC2 IO (P2)

SATA

2

SATA

3 (n

ot a

vaila

ble i

f rea

r USB

3.0

sele

cted

)

DVI-

D 2

USB

2.0

USB

2.0

DVI-

D 1

COM

1

COM

2

GPIO

VGA

1

P0 P0

GPIO (P2)

COM2 (P2)

COM1 (P2)

SPI

DMI

LPC

COM3

GbE (option)

Disp

layP

ort

Gb E

USB

2.0

SATA

4

FDI

DP RJ45 w/Mag

4/8 GByte DDR3L

MRAM

TPM

Audio (P0)

Audi

o

INTEL Lynx Point

IO HUB SATA0

Optional front IO (precludes use of XMC/PMC site 2

SATA

5

USB 3.0

eSATA GbE

Lattice FPGA

PMC 2

X8 P

CIe

PCI-X

X4 PCIe

PMC 1

XMC 2

PCIe – PCI-X Mux Mux

XMC 1

PCIe – PCI-X

INTEL Haswell CPU

SATA SSD

SATA SSD

Disp

layP

ort

DVI-

D 1

(P2)

DVI-

D 2

(P0)

SpringvilleGbE PCIe x1

SpringvilleGbE

SpringvilleGbE

SpringvilleGbE

PCIe x1

PCIe x1

PCIe x1

ClarksvilleGbE PHY

Audi

o CO

DEC

HDA

Optio

nal

Rear

Gb

E IO

Sou

rce

SATA1 GbE (option)

eDP to VGA2

eDP

VGA1 optioned w/PMCIO out P2

PMC/

XMC2

IO

XMC2/PMC2optioned with onboard Hard Drive.

PCI-X

VGA

2

P1 / P2

VME PCIe to PCIX

PCIe x1

X4 P

CIe

P0

VGA 2

PMC/XMC1 IO


6.1 4th Generation Intel Core i7 Processor Features

6.1.1 4th Generation Core i7 Processor Features• Four or two execution cores

– i7-4700 (Quad Core) @ 2.4 GHz (47W) base frequency, (SeeD • Processor Speed and Temperature).

– BGA Exact SKUs 4C GT2 47W cTDP to 35W

• One x8, two x4 PCIe Gen 3 interface.(See Section 6.5 PCI Express Interfaces)

• Dynamic DDR3 Memory

• Dual 64-bit memory controllers with ECC and SPD, DDR3L, 1600 MHz(See Section 6.3 CPU Memory Controller)

• Internal 3D Graphics processor

6.1.2 Processor Supported Technologies• Graphics support for DX11.1, OpenCL1.2, Open GL3.2

• Intel Hyper-Threading Technology (Intel HT Technology) two threads percore

• Intel 64 architecture

• Intel Turbo Boost Technology

• Intel Advanced Vector Extensions (Default disabled) (AVX 2.0 extensions)

• Advanced Encryption Standard New Instructions (AES-NI)

6.1.3 Processor to PCH• Direct Media Interface (DMI) connects the processor and Peripheral

Controller Hub (PCH)

• Flexible Display Interface (FDI) connects the display engine in the processorwith the analog display interface on the PCH


6.2 QM87 Express Chipset

Intel’s QM87 Express Chipset supports the CPU and provides extensive I/O support for the XVR16. This includes:

• Eight PCI Express ports from the QM87 Express Chipset; Three ports fromthe CPU (See Section 6.5 PCI Express Interfaces)

• ACPI Power Management Logic, Revision 4.0a

• Enhanced Direct Memory Access (DMA) controller, interrupt controller, andtimer functions

• Integrated Serial ATA host controllers

– with independent DMA

– operation of up to six ports, up to 60 Gbit/s on two ports

• USB host interface

– Two EHCI high-speed USB 2.0 Host controllers and two rate matchinghubs

– XHCI Host Controllers supporting SuperSpeed USB 3.0

• System Management Bus (SMBus) interface

• Supports Intel Rapid Storage Technology

• Supports Intel Virtualization Technology for Directed I/O

• Four digital ports are supported in the CPU

– DisplayPort

– Embedded DisplayPort (Drives EDP to VGA)

– Two DVI ports

• Serial Peripheral Interface (SPI) support

• Support for TXT (Trusted Execution Technology)

6.3 CPU Memory Controller

The CPU integrated dual channel memory controller in the XVR16 supports dual data rate synchronous DRAM (DDR3) with a data bus width of 64 bits. The XVR16 offers 8 GBytes or 16 GBytes of SDRAM with full ECC support.

CAUTIONCaution must be used when sharing memory between the local processor and the VME to prevent a VME deadlock and to prevent a VME master from overwriting the local processor’s operating system.

6.3.1 Memory Controller Features • Dynamic DDR3 Memory

– Memory DDR3 data transfer rates of 1600 MT/s

• Dual 64-bit memory controllers with ECC and SPD, DDR3L, 1600 MHz

– 8 GByte and 16 GByte options

• Unbuffered DDR3

• Theoretical maximum memory bandwidth of 21.3 GByte/s in dual channelmode assuming DDR3 1600 MT/s


• Intel Fast Memory Access

– Just-in-time Command Scheduling

– Command overlap

– Out-of-order scheduling

6.4 Graphics Controller

The XVR16 uses integrated 2D/3D Graphics in the Intel 4th Generation Core i7 mobile processor and PCH supporting analog and digital display ports. XVR16 HD Graphics 3000 support for DX11.1, OpenCL 1.2, OpenGL3.2 are integrated into the processor through the following four interfaces:

• One front panel DisplayPort (DP)

• Two DVI ports (via Rear P2 and P0)

• Two VGA ports (via Rear P2 and P0)

NOTEFront panel I/O is only available on Levels 1, 2 and 3 boards.

• VGA1: Analog VGA port with a DP/DAC controller NXP PTN3392 supportsa pixel rate of 154 MHz with a resolution up to 1920x1200. This port isconnected to the rear P2.

• VGA2: Analog VGA port from the integrated RAMDAC, supports up to 180 MHz with a resolution of 1920x2000 at 60 Hz. This port is connected tothe rear P0.

NOTEThe termination (75 Ohm to ground) resistors must be located at a possible interface board, i.e., Transition Module VTM26.

• DVI-1, when chosen as an option, is connected to DisplayPort C of the PCH.The maximum pixel rate is 165 MHz at 1920x1200. The port is connected torear P2.

• DVI-2, when chosen as an option, is connected to DisplayPort D of the PCH.The maximum pixel rate is 165 MHz at 1920x1200. The port is connected torear P0.

NOTEThe rear DVI-1 video port is not available with the GPIO(12:0) build option (E=0). The rear DVI-2 is notavailable in the Full PMC1 I/O configuration (G=1,4). Make sure that the PMC1 I/O pins on the PMC-module do not conflict with the DVI-signals.

At higher resolutions, the cable and connectors have a greater influence on picture quality. Using high quality cables and connectors or reducing resolution enhances display.


6.5 PCI Express Interfaces

The Intel 4th Generation i7 CPU and Intel PCH offers several PCI Express interfaces. The PCI Express channels are dedicated to the following devices:

QM87 Express Chipset Root ComplexFigure 6-2 PCI Express Channels

4th Generation Core i7 CPU Root Complex

– x8 PCIe port connects to XMC site 1 via mux

– Lower x4 muxed to PCIe to PCI-X bridge to PMC site 1

– One x4 PCIe port muxed between XMC site 2 and PCIe to PCI-X bridgeto PMC site 2

– One x4 PCIe port to PCIe to PCI-X bridge to TSI148 VME bridge

[3.0]

[7.4]

[11.8]

[15.12]

CPUPCIe

x4MUX Bridge PMC

x8

x4

x4

x4 XMC

PMC

VME

PMC/XMCSite 1

PMC/XMCSite 2

x4

x4x4 MUX Bridge

[3]

Channels 1

PCHPCIe

GigE

VME P0

Front Panel

[6]

Channels 2

x1

x1

x1

x1

GigE

GigE

GigE

XMC


6.6 Mezzanine PMC/XMC Interface

The two PCI Mezzanine Card (PMC) or XMC interfaces create additional slots for parallel mounted expanders or option cards. The PCI busses for the two PMCs are provided by Pericom PI7c9x130 PCIe to PCI bridges and have a 64-bit wide bus with PCI-X 133 MHz capability. If no PMC module is installed, the PMC bridges are disabled and not visible on the PCI bus. If an XMC mezzanine card is mounted at the slot, the PCI Express lanes of the PCIe to PCI bridge are disconnected and muxed to the XMC connector, disabling the PMC PCI bus. See C • Mezzanine Sites.

NOTEPMC2 is available when no onboard hard Drive is chosen as an option (H=0).

6.7 VME Interface

The PCIe Root Complex for the VME interface is the Haswell CPU. The VME interface is provided with the IDT Tundra Tsi148 controller. It contains a complete high performance 64-bit 2eSST capable VMEbus interface with 64-bit PCI-X master/slave capability. A system controller is implemented in the Tsi148 to allow the XVR16 to reside in slot 1 without the necessity of an extra system controller. The VME controller is connected via a 64-bit PCI-X 133 MHz PCIe to PCI bridge Pericom PI7c9x130.

6.7.1 VMEbus Features• 64-bit, 133 MHz PCI-X local bus interface

• Integral FIFOs for write posting and read pre-fetching to maximize bandwidth utilization

• Programmable DMA controller with linked list support

• Complete suite of VMEbus address and transfer modes

• Master (including RMW) and Slave (including RETRY*) transfer modes:

– BLT, ADOH, RMW, RETRY

– A64 / A32 / A24 / A16

– D64 (MBLT, 2eVME, 2eSST) / D32 / D16 / D8 (SCT, BLT)

• Flexible register set, programmable from both the PCI and VMEbus ports

• Full VMEbus system controller functionality

• Geographical addressing

Tsi148 Register All of the controlling registers are located in the Tsi148. The VME related registers are memory mapped. After power-on, the base address is assigned dynamically by the software.

The PCI related registers can be found in the PCI configuration space.

Tsi148 PCI bus Address Space

By default, the VMEbus interface is disabled. In this case, the PCI address space reserved for the VMEbus is available. If the XVR16 needs to access the VMEbus, the PCI address spaces must be defined in the UEFI Setup screen.

Programming the Tsi148

For detailed information about programming the Tsi148, refer to the ʹTsi148 User Manualʹ and to the ʹTsi148 Programming Manualʹ available from Integrated


Device Technology. These Manuals can be downloaded from the IDT web site (www.idt.com) in PDF Format.

6.7.2 PCI-X to VME Bridge (Tsi148) Software GuidelinesProgrammers writing code or using Abaco computer Board Support Packages (BSPs) for the Tsi148 Bridge as used on the XVR16 single board computer, must be aware of requirements of the Tsi148-based PCI-X to VME architecture.

The XVR16 PCI-X to VME Interface uses the Tundra Tsi148 2eSST Bridge. This architecture interfaces the VME to the onboard SBC PCI-X bus. In doing so, the user must be aware of the following guidelines as related to Software programming of the Tsi148:

Shared XVR16 Memory: Any XVR16 DRAM memory made available to another VME master through the Tsi148 is subject to deadlock that may cause a VMEbus error unless specific precautions are taken. If onboard DRAM memory is slaved to the VME, and a program on the XVR16 with slaved memory attempts to write (from the processor) to the VME through the Tsi148, then the user must first request ownership of the VME through the Device Wants Bus (DWB) Bit in the Tsi148, and be granted the VME, prior to doing writes to the Tsi148.

NOTEPlease see the Tsi148 Manual and Errata regarding the requirements to use the DWB bit of the Tsi148.

The user may also implement other methods of gaining ownership of the VME, such as Tsi148 semaphores. But, regardless of the method used, when using shared memory, the user must gain exclusive VME ownership prior to generating asynchronous VME writes.

Extremely Long VME Slave Response Time: VME slave devices (or VME BERR conditions) that have a DTACK (or BERR) response time of greater than 16 can cause Bridge Ordering rule issues with intermixed reads and writes through the Tsi148. If the SBC user wishes to do an extended number (larger than the depth of the Tsi148 write post buffer) of consecutive writes from the processor to the VME through the Tsi148, and those writes can be intermixed with reads from another task, then the user must verify that all slaves within the system have DTACK response time of less than 16, and that the VME BERR timer of the system is set to 16 max. Also, it is suggested that prior to doing any large VME transfer, the users should first request ownership of the VME through the DWB Bit in the Tsi148, and be granted the VME, prior to doing writes to the Tsi148.

NOTEPlease see the Tsi148 Manual and Errata regarding the requirements to use the DWB bit of the Tsi148.

The user may also implement other methods of gaining ownership of the VME, such as Tsi148 semaphores. But, regardless of the method used, when generating an extended number of consecutive processor to VME writes (larger than the depth of the Tsi148 write post buffer), the user must gain exclusive VME ownership prior to generating these asynchronous VME writes.

NOTEFailure to implement the procedures outlined above may cause some system implementations to lockup or generate unwanted VME errors.

http://www.idt.com


Overlapping Slave DTACK response and System Controller BERR: The VMEbus specification allows the System Controller (or BERR Timer) to generate a VME Bus Error (BERR) without looking at the status of the VMEbus DTACK signal. When these VMEbus signals occur simultaneously (or within +/-15 ns) in response to a local processor generated read cycle that initiates a Tsi148 Master VMEbus read cycle, then the PCI delayed read retry that happens as part of this Tsi148 VME read transaction may hang in retry and never return data to the processor from either the completed read cycle (DTACK) or the BERR.

The user can ensure that this is not a system issue by using either of the following:

1. Always ensure that the BERR timeout of the VME System Controller is set tolonger (at least 10S) than the maximum Slave DTACK response time.

2. If the user cannot ensure that the BERR timeout is longer than the maximumSlave DTACK response time, then the user should use the Tsi148 DMAcontroller to initiate VME read access, instead of the processor initiating theVME read access.

6.7.3 VME \SYSRESET DirectionThe XVR16 provides a non-volatile UEFI setup screen of the VME \SYSRESET direction. In the setup screen the user can decide whether the XVR16 can drive the VME \SYSRESET and also decide whether the VME \SYSRESET should be used as an input.

6.8 Interrupt Controller

The Mobile Intel QM87 Express Chipset provides an ISA compatible Programmable Interrupt Controller (PIC) that consists of two 82C59A devices with eight interrupt request lines each. The two controllers are cascaded so that fourteen external and two internal interrupt sources are available. The master interrupt controller provides IRQ [7...1]; the slave interrupt controller provides IRQ [15...8]. IRQ2 is used to cascade the two controllers, IRQ0 is used as a system timer interrupt and is tied to interval timer 1, counter 0. The remaining fourteen interrupt lines are mapped to various onboard devices. Each 82C59A provides several internal registers. The interrupts on the IRQ input lines are handled by two registers: the interrupt request register IRR and the in-service register ISR. For programming details see the 82C59A data sheet.

The XVR16 also supports the Interrupt handling of the Advanced Programmable Interrupt Controller (APIC). This handling of the APIC interrupt services must be supported by the operating system. The I/O APIC handles interrupts very differently than the 8259.

6.9 Timer (8254)

The XVR16 is equipped with an 8254 compatible timer. This timer contains three counters. Each counter output provides a key system function. Counter 0 is connected to interrupt controller input IRQ0 and provides a system timer interrupt for time-of-day, floppy disk time-out and other system timing functions. Counter 1 generates a refresh request signal and Counter 2 generates the sound for the speaker.


The following table gives an overview of the 8254 timer functions.

The counter/timers are programmed by I/O accesses. A single control word register controls the operation of all three counters. For more information on programming and a detailed register description, see the 8254 data sheet.

6.10 Real Time Clock

The two key functions of the Real Time Clock (RTC) are:

1. Tracking time of day

2. Storing system data, even when the system is powered down

The PCH provides the RTC module that is equipped with a battery backed-up date and time keeping device. The RTC is powered from the +5V_STDBY or VBAT supply. When either of these supplies is present, the system clock is maintained. If all power is removed, the RTC is reset. Valid RAM data and time can be maintained after power down through the use of an external battery source.

The RTC module is comprised of a clock with 1 second resolution and 242 bytes of general purpose CMOS RAM used by system UEFI Firmware. The three maskable interrupts’ features are:

• Time of day alarm with once a second to once a month range

• Periodic rates of 122 s to 500 ms

• End of update cycle notification

The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. In addition to providing time of day, the RTC provides a 100 year calendar with alarm features and battery backed operation. The time of day function includes fourteen control registers.

NOTEThe leap year determination for adding a 29th day to February does not take into account the end-of-the-century exceptions.

Table 6-1 Interval Timer FunctionsInterval Timer Function Description

Function Counter 0 (System Timer)

Gate Always on

Clock In 1.193 MHz (OSC/12)

Out IRQ0 (INT1)

Function Counter 1 (Refresh Request)

Gate Always on


Out Refresh Request

Function Counter 2 (Speaker Tone)

Gate Programmable via Port $061


Out Speaker


6.11 UEFI Firmware - Backup UEFI Firmware

The XVR16 provides two 8 MByte SPI flash devices for the UEFI Firmware code and Management Engine firmware. The two devices consist of primary and a backup code. Integrated logic switches between the primary UEFI Firmware and the backup UEFI Firmware device. The primary UEFI Firmware can be programmed by the user only. The backup UEFI Firmware chip is read-only and can be updated at the factory only. This feature prevents the customer from hang-ups at primary UEFI Firmware updates.

Switching between primary and backup UEFI is controlled by header P8. When there is no jumper on P8, then the primary UEFI is used. When a jumper is installed on P8, then the backup UEFI is used. See Figure 5-1 on page 35 for location of P8 header.

UEFI Firmware with Backup UEFI Firmware - Easy updating, in-system programmable Flash ROM, automatic system configuration, write protected backup UEFI Firmware with automatic swap.

• Integrated VGA, and Ethernet PXE ROM BIOS

• USB mass storage support, password protection, headless support

• Remote console via serial port

6.12 BMC

A Baseboard Management Controller (BMC) is implemented on the XVR16, interfacing between the host processor and the system management network. This controller can also function as a Peripheral Management (PM) Controller. The BMC is mapped into the local CPU’s I/O address space.

If the power of the XVR16 is off, the Intelligent Platform Management Interface (IPMI) controller may be supplied by the +5VSTDBY power pin.

For information about the System Management in VME systems, please refer to

the VITA 38 and PICMG® 2.9 System Management Specification. More information about IPMI can be found at the Intel website.

LINKwww.intel.com/content/www/us/en/servers/ipmi/ipmi-home.html.

6.12.1 IPMBThe Intelligent Platform Management Bus (IPMB) is an I2C based bus that provides a standardized interconnection between different VME boards within a chassis. The standardized connection to the backplane is shown below.

Table 6-2 IPMB Backplane Pin AssignmentsP1 Name Description

B21 IPMB_SCL Serial Clock

B22 IPMB_SDA Serial Data

B31 +5 VSTDBY Power Supply for all IPMI-devices

http://www.intel.com/content/www/us/en/servers/ipmi/ipmi-home.html


6.12.2 SMBusThe SMBus is an I2C-based bus that provides a standardized interconnection

between the BMC and other I2C devices on the chassis. The standardized connection to the backplane is shown below:

6.13 Elapsed Time Indicator

A Dallas DS1682 Elapsed Time Indicator (ETI) logs the amount of time the XVR16 has been powered and the number of power cycles. Power up time is only recorded when the platform is fully powered and not in State S3, S4 or S5. Power cycle events are only recorded when the backplane VS3 (+5V) power rail transitions from on to off.

The ETI is intended only to be used by Abaco software drivers. See the relevant software manual for details.

LINKFor more details on the ETI device, see www.maxim-ic.com.

6.14 Keyboard and Mouse

The communication between the PC and the keyboard and mouse is managed by a USB connection. A legacy 8042 interface is available via emulation for USB unaware OS.

6.15 SATA Interface

The XVR16 offers up to six SATA Gen1 and Gen2 channels that can transfer up to 300 MByte/s.

SATA Ports:

• SATA0 to onboard hard drive option

• SATA1 to optional eSATA GEN3 Front Panel Port

• SATA2 to Rear P0*

• SATA3 to Rear P0*

• SATA4 to SSD2

• SATA5 to SSD1

NOTE*SATA signals at the rear are shared with PMC1 I/O signals. Rear SATA is not available in the Full PMC1 I/O configuration. Ensure that the PMC1 I/O pins on the PMC module do not conflict with the SATA signals.

Table 6-3 SMBus Backplane Pin AssignmentsP1 Name Description

D19 SMB_SCL Serial Clock

D21 SMB_SDA Serial Data

D23 \SMB_ALERT SMBus Alert signal to IPMI controller

http://www.maxim-ic.com/


The XVR16 UEFI Firmware automatically detects connected SATA Drives or flash disks and enters the corresponding drive parameters into the UEFI Firmware setup.

Using SATA and SCSI devices: The PC allows the simultaneous use of SATA and SCSI hard disks (for example: SCSI PMC). UEFI Firmware setup allows reordering drives to boot from either SCSI or SATA drives.

6.16 Gigabit Ethernet Interface

Four Ethernet interfaces are available on the XVR16 depending on the configuration. The ports are high performance 1000BASE-T (backward compatible with 10BASE-T/100BASE-TX).

Use of PCH Internal Gbit MAC, combined with I217 Clarksville Gbit PHY, provides VPRO capability. All four ports provide IEEE-1588 capability. Each network interface is assigned a unique MAC address which resides in an Ethernet address ROM on the XVR16. All GbE interfaces are equipped with LEDs indicating Link and Activity.

• Two GbE interfaces available at the front panel

– ETH1 Intel Springville, standard port

– ETH2 Intel Springville, optionally provided when the PMC/XMC optionis not chosen (H=1,2 or 3).

• Two GbEs at the rear are routed to P0 (ANSI/VITA 31.1-2003 compliant)

– ETH3 Intel Springville

– ETH4 Intel Clarksville

Remote booting is supported on all four ports with Intel PXE Boot Firmware.

6.17 Additional Devices

6.17.1 XVR16 Field Programmable Gate Array DevicesThe XVR16 has a Field Programmable Gate Array (FPGA) that controls the power sequence and reset sources. The FPGA also contains additional devices: Serial Interfaces, Watchdog Timer, MRAM, Timers, GPIO and Board Configuration registers. See section 8.1 FPGA Control and Status Registers on page 83 for details.

• Serial Interface

• Watchdog Timer

• MRAM

• Timers

• GPIO

• Board Configuration


Serial Interfaces The serial interfaces are provided by the Lattice FPGA. The XVR16ʹs serial ports are fully compatible with the 16550D UART. Each serial interface provides a 16 byte FIFO, offering higher performance than earlier used standard serial interfaces. The UARTs have programmable baud rate generators capable of up to 115200 baud. There are four address locations defined for serial interfaces on standard PCs. The serial interfaces are I/O mapped and can occupy four address ranges.

• COM1 and COM2 are available out the rear P2

• COM3 is RS232 only interface located on the Front Panel

• COM4 is a transistor-transistor logic (TTL) serial port supportingcommunication with the BMC

Watchdog Timer The XVR16 provides a Watchdog timer (WDT) in the onboard FPGA. This timer can be loaded with 8 different count values ranging from 2 ms up to 67 s. Once loaded and enabled, the WDT will count until the load value is reached, or the count is reset by accessing the WDT Keep Alive Register. If the Keep Alive Register is not accessed before the count is reached, the WDT will reset the XVR16. See Table 8-5 , Watchdog Timer (WDT) Refresh (0x60D), on page 86.

MRAM The MRAM is a 512 KByte Non-volatile memory residing at location 0xFC000000 memory space. The total 512 KByte space is addressed with eight 64 KByte memory pages. Memory page selection is controlled by the MRAM register located at IO Space 0x68A. See Table 8-15 for additional details on MRAM Page Registers.

Timers The XVR16 FPGA provides two 32-bit timers with load, continuous and one-shot modes, and interrupt capability. See Table 8-16, Table 8-17, Table 8-23 and Table 8-24.

GPIO (0-11) The GPIO is sourced from the FPGA. Twelve GPIO pins are available on the VME connector P2 (P7302). These pins can be used for I/O functions with output 3.3 V signals as well as GPIOs are 3.3 V only and are not 5 V tolerant inputs. GPIO (0..9) can be used only when the DVI1 is not installed. GPIO (0..9) and DVI1 are mutually exclusive ordering options. GPIO (10..11) are always available. Refer to Table 8-30 to Table 8-47 for more GPIO details.

Board Configuration

The XVR16 FPGA provides registers dedicated to providing information regarding the unit options for items such as Front panel presence, number and type of video displays, Ethernet ports, SATA ports, USB ports, etc.

Refer to Table 8-60 to Table 8-61 for more register descriptions that include board configuration registers.

6.17.2 Temperature SensorsTemperature sensors are integrated in the CPU die, PCH die, and the sensor of the FPGA that displays the local onboard temperature of the XVR16 and is located beneath the CPU heat sink.

The BMC or FPGA sensor provides an integrated over-temperature output that can be used to take actions such as reducing the CPU speed.

The die sensors of the CPU and PCH may be programmed to take actions to protect the devices from overheating. The CPU temperature sensor has a


catastrophic protection which shuts down the CPU core voltage if the die temperature reaches above 125 °C.

6.17.3 Geographic AddressingIf the backplane supports geographic addressing (GA), the XVR16 can detect the unique address in a VME System with the GA [5...0] pins on the VME connector P1.

6.17.4 LEDsThe XVR16 has a set of status LEDs for indicating power/startup and BIT status (see your Sales Representative for BIT availability). Five LEDs plus two user programmable LEDS are available at the front panel. Two status lines for LEDs are connected to the rear. See Section 5.1 Front Panel Interface on page 36.

Front I/O LEDs

• 1x Front Power Good Green LED

• 1x Front Aux_Power_Good Red LED

• 1x Front Reset Status Red LED

• 1x Front BITFail Red LED

• 2x Front Yellow user programmable LEDs

• 1x Front BITPass Green LED

Rear I/O LEDs

• 1x Rear BITFail LED signal

• 1x Rear Boot Status LED signal

The rear status LED signals provide the board status for external LEDs. The signal already implements serial resistors on the XVR16.

Table 6-4 Front BIT Status LEDStatus LED

BITFail Red on

BITStatus 1, 0 Yellow

BIT PASSED Green


6.17.5 Power ButtonThere is a Power (PWR) Button onboard. An external Power Button may be connected between the appropriate I/O connector at the back side and ground (GND).

Figure 6-3 Power Button

With a short pressing at the PWR Button, the operating system tries to shut down the XVR16 to State S5. If the operating system does not react, a long pressing (>5 s) will shut down the XVR16 to State S5 without operating system support.

State S5 switches off the CPU core power and holds the XVR16 in reset. The state S5 is indicated at the S-State LED. At this state it is possible to reactivate the XVR16 with a short press at the PWR Button. The CPU core voltage is switched on and the board restarts. This power off and power on cycle can be used to reset the XVR16.

6.17.6 HD AudioHigh Definition (HD) Audio is supported on the rear I/O through the P0 VME connector. The HD Audio controller is in the QM87 Express Chipset, with an external Audio Codec. These Audio signals can be accessed through a connector on the transition module. No Audio AMP is required onboard.


7 • System Resources, Memory Mapping, and Registers

This chapter describes system resources, such as memory mapping, register settings, and default interrupt request assignments.

7.1 Memory Mapping

The table below shows the memory address area used by the XVR16.

Table 7-1 Memory MappingAddress Size Used by

$0 - $9_FFFF 640 KByte System RAM

$A_0000 - $B_FFFF 128 KByte Video RAM (if enabled)

$C_0000 - $D_FFFF 128 KByte Used by PCI ROMs, Add-on cards

$E_0000 - $F_FFFF 128 KByte UEFI Firmware

$10_0000 - $EFFF_FFFF Depends on available DRAM Extended RAM

$4000_0000 - $FFBF_FFFF Depends on available DRAM Dynamically used by PCI devices

$FF80_0000 - $FFFF_FFFF 8 MByte SPI ROM (UEFI Firmware and descriptors)

Publication No. 500-9300007876-000 Rev. C.0 System Resources, Memory Mapping, and Registers 79

7.2 Register Settings

The following section provides an overview of the registers located in the I/O address area of the XVR16.

NOTEThe address locations of the PCI devices, such as Ethernet, are not described in the following tables. This is because the UEFI Firmware automatically configures all PCI devices.

7.2.1 Standard Register SettingsThe standard register settings are equal to all standard PC/AT systems. The table below provides an overview of the address ranges occupied by these registers.

Table 7-2 Standard Register SettingsI/O Address Range (Hex) Function

$00H - $0FH DMA Controller

$20H - $21H Interrupt Controller

$40H - 43H Counter / Timer

60H Keyboard Controller

$61H NMI Status and Control

$64H Keyboard Controller

$70H - $71H RTC, NMI Mask

$80H - $8FH DMA Page Register

$A0H - $A1H Interrupt Controller

$B2H - $B3H Power Management

$C0H - $DEH DMA Controller

$F0H - $F1H Coprocessor

$170H - $177H Secondary SATA

$1F0H - $1F7H Primary SATA

$2E8H - $2EFH COM port a

$2F8H - $2FFH COM port a

$3E8H - $3EFH COM port a

$3F8H-$3FFH COM port a

$600H - $6FFH XVR16 specificb a Via setup four address ranges can be defined for the serial interfaces.

b Used for onboard programmable options.


7.2.2 InterruptsThe interrupt routing for standard components such as COM1/2 is in compliance with standard PC/AT systems. Unused interrupts can be used for add-on cards or other board specific PCI devices such as SCSI and Ethernet.

Table 7-3 Interrupt AssignmentsHardware IRQ IRQ Source

INTC1

IRQ00 System Timer

IRQ01 Keyboard a

IRQ02 Cascade from INTC2

IRQ03 COM2b

IRQ04 COM1b

IRQ05 GPIO0-11

IRQ06 Timers 1 and 2

IRQ07 COM3b

IRQ08 Real Time Clock

IRQ09 Power Management Control

IRQ10 COM4b

IRQ11 PnP/PCIb

IRQ12 PS/2 Mouse a

IRQ13 Numeric Coprocessor

IRQ14 External IDE c

IRQ15 Onboard IDE d

NMI Parity Error,ECC Error System Error

a Emulated interrupt from USB keyboard/mouse.

b Interrupts are available for Plug and Play PCI devices

c This interrupt is available for other devices when the primary IDE is disabled in SETUP or when IDE is configured to native PCI-mode.

d This interrupt is available when the secondary IDE is disabled in SETUP or when IDE is configured to native PCI mode.

Publication No. 500-9300007876-000 Rev. C.0 System Resources, Memory Mapping, and Registers 81

7.3 Advanced Programmable Interrupt Controller

The XVR16 supports APIC. This handling of the APIC interrupt services must be supported by the operating system. The I/O APIC handles interrupts differently than the standard interrupt controller. These differences are:

• Method of Interrupt Transmission: The I/O APIC transmits interruptsthrough processor FSB, and interrupts are handled without the need for theprocessor to run an interrupt acknowledge cycle.

• Interrupt Priority: The priority of interrupts in the I/O APIC is independentof the interrupt number. For example, interrupt 10 may be given a higherpriority than interrupt 3.

• More Interrupts: The three I/O APICs in the XVR16 support a total oftwenty-four independent interrupt sources.

7.4 Message Signaled Interrupts

The XVR16 supports Message Signaled Interrupts (MSI) on all of its PCIe links for transporting interrupts from PCIe devices towards the CPU.


8 • FPGA Registers

The FPGA is a device that provides the following:

• Onboard registers

• Watchdog Timer for synchronizing and controlling multiple events

• Software controlled general purpose timers

• GPIO signals sourcing

• Write protection control

The XVR16 provides bootable NAND Flash and 512 KByte of nonvolatile random access memory (NVRAM).

The block diagram for the FPGA is shown in the figure below.

Figure 8-1 Block Diagram for FPGA

RTLPC

Interface

LFRAME#

LAD[3..0 ]

PCI CL KRESET#

IO addr: 0x600+

32-bit Timer

32-bit Timer

WDT

Board ID

BMM Ctrl. Reg.

Serial Ctrl. Reg.

GPIO

NVRAM

Publication No. 500-9300007876-000 Rev. C.0 FPGA Registers 83

8.1 FPGA Control and Status Registers

The XVR16 FPGA contains an LPC interface for access to real-time user functions such as Watchdog timer, 32-bit Timers, and GPIO. There are also control and status registers for other board functions such as BIT, Board/Front Panel Options, NVRAM Page control, and COM Port Configuration. The FPGA registers are mapped in I/O space staring at address 0x600.

See Table 8-1 for the list of XVR16 FPGA Registers.

Table 8-1 XVR16 FPGA Register Definitions LPC I/O Port (Hex) Description Access

600 Board ID Read

601 Board Revision Read

602-060A Reserved NA

60B FPGA Revision Read

60C Reserved NA

60D Watchdog Timers (WDT) Refresh Read/Write

60E Watchdog Timer CSR (LSB) Read/Write

60F Watchdog Timer CSR (MSB) Read/Write

610 to 61A Board ID String Read

61B Reset Cause Register 1 Read

61C Reset Cause Register 2 Read

61D-61F Reserved NA

620 BMM/BMC Control Read/Write

621 Reserved NA

622 LED Control Read/Write

623 Reserved NA

624 Reserved NA

625 BIOS/SPI Control Read/Write

626-628 Reserved NA

629 BIT Control/Status Register Read/Write

62A-62D Reserved NA

62E-631 Reserved NA

632-634 Reserved NA

635 NVRAM Memory Space Page Register Read/write

636-647 Reserved NA

648-64F Reserved NA

650 Timer 0 CSR1 Read/Write


652 Timer 0 IRQ Clear Write to Clear

653 Reserved NA

654 Timer 0 Byte 0 (LSB) Read/Write

655 Timer 0 Byte 1 Read/Write

656 Timer 0 Byte 2 Read/Write

657 Timer 0 Byte 3 (MSB) Read/Write




65A Timer 1 IRQ Clear Write to Clear

65B Reserved NA

65C Timer 1 Byte 0 (LSB) Read/Write

65D Timer 1 Byte 1 Read/Write

65E Timer 1 Byte 2 Read/Write

65F Timer 1 Byte 3 (MSB) Read/Write

660-66F Reserved NA

670 GPIO 7-0 Out Read/Write

671 GPIO 7-0 In Read

672 GPIO 7-0 Direction Read/Write

673 GPIO 7-0 Interrupt Enable Read/Write

674 GPIO 7-0 Interrupt Level/Edge Read/Write

675 GPIO 7-0 Interrupt Active High/Low Read/Write

676 GPIO 7-0 Both Edges Read/Write

677 GPIO 7-0 Interrupt Status Read/Write to Clear

678 GPIO 7-0 Available Read

679-67B Reserved NA

67C GPIO 15-8 Out Read/Write

67D GPIO 15-8 In Read

67E GPIO 15-8 Direction Read/Write

67F GPIO 15-8 Interrupt Enable Read/Write

680 GPIO 15-8 Level/Edge Read/Write

681 GPIO 15-8 Active Low/High Read/Write

682 GPIO 15-8 Both Edges Read/Write

683 GPIO 15-8 Interrupt Status Read/Write to Clear

684 GPIO 15-8 Available Read

685-687 Reserved NA

688-696 Reserved NA

697-69F Reserved NA

6A0 Ethernet Port Availability Read

6A1 COM Port Availability Read

6A2 COM Port Wire Configuration Read

6A3 COM Port Full Modem Line Configuration Read

6A4 SATA Port Availability Read

6A5 USB 2.0 Port 7:0 Available Read




6A9 Display Availability Read

6AA Display Type VGA Read

Table 8-1 XVR16 FPGA Register Definitions (Continued)LPC I/O Port (Hex) Description Access


6AB Display Type DVI/HDMI Read

6AC Display Type DisplayPort Read

6AD Ancillary/Audio Configuration Read

6AE Front Panel Configuration Read

6AF PMC/XMC1 I/O Configuration Read

6B0 PMC/XMC2 I/O Configuration Read

6B1 SSD Availability Register Read

6B2 SSD Hardware Secure Erase Availability Read

6B3-6B7 Reserved NA

6B8 UART Enable Read/Write

6B9-6BA Reserved NA

6BB COM Port Transceiver Enables Read/Write

6BC COM Port RS232/RS422 Selections Read/Write

6BD COM Port RS485 Auto Direction Control Read/Write

6BE COM Port Loop-back Enables Read/Write

6BF SSD Erase Control Register Read/Write

6C0 SSD Cache Flush Control Register Read/Write

6C1 Reserved NA

6C2 VME Backplane Control Read/Write

6C3 Reserved NA

6C4-6C5 Reserved NA

6C6 Scratch Pad Register

6C7 Test Register (Reserved for Factory Test Only) Read/Write

6C8 PMC/XMC1 Status NA

6C9 PMC/XMC2 Status Read

6CA VME Backplane Status Read

6CB SSD Status Read

6CC Write Protection Status Read

6CD Board Jumper/Link Status Read

6CE Boot Location Status Read

6CF Reserved NA

6D0 Thermal Status Read

6D1 Alarm Status Read

6D2-6FF Reserved NA

Table 8-2 Board ID Register (0x600)Bit R/W Description Default

7:0 R When read, this register returns the Value 0x6E to identify the XVR16

0x6E

Table 8-1 XVR16 FPGA Register Definitions (Continued)LPC I/O Port (Hex) Description Access


Table 8-3 Board Revision Register (0x601)Bit R/W Description Default

7:4 R Major assembly revision (artwork)

0x1=Rev 1, 0x2=Rev 2

NA

3:0 R Minor revision (Hardware build state revision)

0x0 = Rev A, 0x1 = Rev B

NA

Table 8-4 FPGA Revision Register (0x60B)Bit R/W Description Default

7:0 R Revision of FPGA code N/A

Table 8-5 Watchdog Timer (WDT) Refresh (0x60D)Bit R/W Description Default

7:0 R/W Any Write access to this register will re-load the Watchdog Timer. This must be done periodically after the WDT is enabled, to keep the WDT from causing a Board Reset.

0x00

Table 8-6 Watchdog Timer Control/Status Register (CSR) LSB (0x60E)Bit R/W Description Default

7:1 R Reserved 0

0 R/W Watchdog Timer Count Enable (1 = WDT enabled, 0 = WDT disabled)

0

Table 8-7 Watchdog Timer Control/Status Register (CSR) MSB (0x60F)Bit R/W Description Default

7:3 R Reserved 0

2:0 R/W Watchdog Timer Timeout Selection111= WDT Timeout = 2mS110= WDT Timeout = 32mS101= WDT Timeout = 131mS100= WDT Timeout = 262mS011= WDT Timeout = 524mS010= WDT Timeout = 2.1S001= WDT Timeout = 33S000= WDT Timeout = 66S

111

Table 8-8 Board ID String Registers (0x610 - 0x61A)Bit R/W Description Default

7:0 R These bytes read back ASCII values for "XVR 16"0x610=0x58 ("X")0x611=0x56 ("V")0x612=0x52 ("R")0x613=0x20 (" ")0x614=0x31 ("1") 0x615=0x36 ("6")

0X580x560x520x200x310x36


Table 8-9 Reset Cause Register 1 (0x616)Bit R/W Description Default

7-3 R Reserved 0

2 R Reserved for Front Panel Reset 0

1 R Reserved 0

0 R VME Reset 0

Table 8-10 Reset Cause Register 2 (0x617)Bit R/W Description Default

7-4 R Reserved 0

3 R Reserved for BMC reset 0

2-1 R Reserved 0

0 R Watchdog Reset 0

Table 8-11 BMM/BMC Control Register (0x620)Bit R/W Description Default

7-6 R Reserved for BMM (Not Required for BMC) 0

5 R/W BMC Interrupt Enable 1 = Enable 0 = Disable

0

4:0 R Reserved for BMM (Not Required for BMC) 0


Table 8-12 LED Control Register (0x622) Bit R/W Description Default

7 R/W BIT PASS LED1 = LED ON 0 = LED OFF

0 (sticky on BIT reset)

6 R/W BIT Fail LED1 = LED ON0 = LED OFF

Note: This output is ORed with the BMC BIT FAIL output before driving the LED and also the BIT_FAIL pin on the backplane.

0

5 R/W BIT Status 1 LED1 = LED ON0 = LED OFF

0

4 R/W BIT Status 0 LED1 = LED lit0 = LED not lit

0

3 R Reserved for Standby Power LED 0

2 R/W Board Power Status LED 1 = LED ON0 = LED OFF

0

1 R/W Reset Status LED1 = LED ON0 = LED OFF

0

0 R/W SATA Status LED)1 = LED ON0 = LED OFF

0

Table 8-13 BIOS/SPI Control Register (0x625)Bit R/W Description Default

7 R/W Select Other boot device1 = Opposite boot device from which the board was booted is selected (i.e. if booted from recovery, main device is selected)

0 = Boot device from which the board was booted is selected

0

6-0 R Reserved 0


Table 8-14 BIT Control/Status Register (0x629)Bit R/W Description Default

7 R/W HRESET1 = Board reset requested0 = Board reset not requested

0

6-5 R/W Bit Run Status00 = BIT not previously run01 = Fast BIT performed10 = Full BIT performed11 = Fast Start Performed

0 (sticky when reset using HRESET req)

4 R/W Pass/Fail1 = Failed0 = Passed


3 R/W FAST BIT enable1 = Fast BIT enabled (via BIOS setting)0 = Fast BIT disabled

0

2 R/W FAST Start enable1 = Fast Start enabled (Via BIOS setting)0 = Fast Start Disabled

0

1 R FAST Start Input (GPIO0) 1

0 R/W BIT Run1 = BIT has been run0 = BIT not been run


Table 8-15 NVRAM Memory Space Page Register (0x635)Bit R/W Description Reserved

7-3 R Reserved 0

2:0 R/W 64K Byte page select NVRAM address 18:16Driven onto NVRAM bus when NVRAM is accessed

0

Table 8-16 Timer 0 Control and Status Register 1 (CSR1) (0x650)Bit R/W Description Reserved

7 R Timer IRQ status1 = Pending0 = No Interrupt

NA


6 R Reserved 0

5:4 R/W Clock Source Select:00 = Use 2 MHz FPGA Clock (default)01 = Reserved10 = Reserved11 = Reserved

0

3 R/W Timer Read Selection 1 = Read Timer Load Value0 = Read Current Time Value

0

2:1 R/W Clock Divider (Value when 2 MHz Clock used)00 = 1:1 (2 MHz)01 = 1:2 (1 MHz)10 = 1:4 (500 KHz)11 = 1:8 (250 KHz)

0

0 R/W Enable Timer IRQ1 = IRQ Enabled 0= IRQ Masked

0

Table 8-17 Timer 0 Control and Status Register 2 (CSR2) (0x651)Bit R/W Description Default

7:5 R Reserved NA

4 R/W Timer Read Latch Select 1 = Latch All Timers on read of Timer 0 LSB, 0 = Latch Individual Timers on the read of individual Timer LSBNote: Setting this bit in any timer CSR2 register will have the same effect of latching ALL timers on read of timer 0 LSB.

0

3:2 R Reserved NA

1 R/W Timer One-Shot Enable1 = Timer will count down once and stop0 = Timer will count down and reload at terminal count

0

0 R/W 1 = Timer Enabled0 = Timer Disabled

0

Table 8-18 Timer 0 IRQ Clear Register (0x652)Bit R/W Description Default

7:0 W Any Write to this register will clear the Timer IRQ N/A



Table 8-19 Timer 0 Data Byte 0 (LSB) (0x654)Bit R/W Description Default

7:0 R/W Read value depends on value of CSR1(3).

If '0' - Contains Bits 7-0 of the Timer current counter valueIf '1' - Contains Bits 7-0 of the Timer load value

Reading this register latches the upper bits of the count value to prevent rollover. Write always updates Timer load value.

0x00

Table 8-20 Timer 0 Data Byte 1 (0x655)Bit R/W Description Default




0x00

Table 8-21 Timer 0 Data Byte 2 (0x656)Bit R/W Description Default




0x00

Table 8-22 Timer 0 Data Byte 3 (MSB) (0x657)Bit R/W Description Default




0x00



7 R Timer IRQ status

1 = Pending 0 = No Interrupt

NA

6 R Reserved 0

5:4 R/W Clock source select:

00 = Use 2 MHz FPGA Clock (default) 01 = Reserved10 = Reserved11 = Reserved

0

3 R/W Timer Read selection

1 = Read Timer Load value 0 = Read Current Time value

0

2:1 R/W Clock divider (Value when 2 MHz Clock Used)

00 = 1:1 (2 MHz)01 = 1:2 (1 MHz)10 = 1:4 (500 KHz)11 = 1:8 (250 KHz)

0

0 R/W Enable Timer IRQ

1 = IRQ Enabled 0= IRQ Masked

0

Table 8-24 Timer 1 Control and Status Register 2 (CSR2) (0x659)Bit R/W Description Default

7:5 R Reserved 0

4 R/W Timer Read Latch Select

1 = Latch All Timers on read of Timer 0 LSB0 = Latch Individual Timers on the read of individual Timer LSB

Note: Setting this bit in any timer CSR2 register will have the same effect of latching ALL timers on read of timer 0 LSB

0

3:2 R Reserved 0

1 R/W Timer On-Shot Enable

1 = Timer will count down once and stop0 = Timer will count down and reload at terminal count

0

0 R/W Timer Enable

1 = Timer enabled0 = Timer disabled

0


Table 8-25 Timer 1 IRQ Clear Register (0x65A)Bit R/W Description Default

7:0 R/W Any write to this register will clear the Timer IRQ N/A

Table 8-26 Timer 1 Data Byte 0 (LSB) (0x65C)Bit R/W Description Default

7:0 R/W Read value depends on CSR1(3)



0x00

Table 8-27 Timer 1 Data Byte 1 (0x65D)Bit R/W Description Default




0x00

Table 8-28 Timer 1 Data Byte 2 (0x65E)Bit R/W Description Default




0x00


The value of this register is driven onto the GPIO pins when the direction mode is set to output.

This register returns the status of the GPIO pins, regardless of the direction mode.

Table 8-29 Timer 1 Data Byte 3 (MSB) (0x65F)Bit R/W Description Default

7:0 R/W Read value depends on CSR1(3).



0x00

Table 8-30 GPIO 7-0 OUT Register (0x670)Bit R/W Description Default

7:0 R/W GPIO7:GPIO0 0x00

Table 8-31 GPIO 7-0 IN Register (0x671)Bit R/W Description Default


Table 8-32 GPIO 7-0 Direction Register (0x672)Bit R/W Description Default

7:0 R/W GPIO7:GPIO0

1 = Output0 = Input

0x00

Table 8-33 GPIO 7-0 Interrupt Enable Register (0x673)Bit R/W Description Default

7:0 R/W GPIO7:GPIO0

1 = Interrupt enabled0 = Interrupt masked

0x00


This interrupt sets the interrupt detection sensitivity of each interrupt pin (level or edge mode).

This interrupt sets the interrupt detection sensitivity of each interrupt pin (active high/low or rising/falling edge depending on sensitivity mode).

When enabled, both-edge mode causes interrupts to be generated on both rising and falling edges.

Table 8-34 GPIO 7-0 Interrupt Level/Edge Register (0x674)Bit R/W Description Default

7:0 R/W GPIO7:GPIO0

1 = Edge0 = Level

0x00

Table 8-35 GPIO 7-0 Interrupt Active High/Low Register (0x675)Bit R/W Description Default

7:0 R/W GPIO7:GPIO0

1 = Active high / rising edge 0 = Active low / falling edge

Note: Function depends on whether the bit is in level or edge mode.

0x00

Table 8-36 GPIO 7-0 Both-Edge Register (0x676)Bit R/W Description Default

7:0 R/W GPIO7:GPIO0

1 = Both-edge mode enabled 0 = Both-edge mode disabled

Note: The GPIO bit must be in edge mode for both-edge mode to work.

0x00

Table 8-37 GPIO 7-0 Interrupt Status Register (0x677) Bit R/W Description Default

7:0 R/W1C GPIO7:GPIO0 (Write 1 to Clear)

1 = Interrupt pending0 = No interrupt

0x00


This register allows software to easily determine which GPIO 7-0 signals are available on the board. All GPIO signals use shared backplane pins and are only available when the board is configured with the appropriate build option.

The value of this register is driven onto the GPIO pins when the direction mode is set to output.

This register returns the status of the GPIO pins, regardless of the direction mode.

Table 8-38 GPIO 7-0 Availability Register (0x678)Bit R/W Description Default

7 R GPIO7 Availability1 = GPIO7 Available0 = GPIO7 Not Available

NA


NA


NA


NA


NA


NA


NA


NA

Table 8-39 GPIO 15-8 OUT Register (0x67C)Bit R/W Description Default


Table 8-40 GPIO 15-8 IN Register (0x67D)Bit R/W Description Default

7:0 R GPIO15:GPIO8 0x00


This interrupt sets the interrupt detection sensitivity of each interrupt pin (level or edge mode).

This interrupt sets the interrupt detection sensitivity of each interrupt pin (active high/low or rising/falling edge depending on sensitivity mode).

When enabled, both-edge mode causes interrupts to be generated on both rising and falling edges.

Table 8-41 GPIO 15-8 Direction Register (0x67E)Bit R/W Description Default

7:0 R/W GPIO15:GPIO8

1 = Output0 = Input

0x00

Table 8-42 GPIO 15-8 Interrupt Enable Register (0x67F)Bit R/W Description Default


1 = Interrupt enabled 0 = Interrupt masked

0x00

Table 8-43 GPIO 15-8 Interrupt Level/Edge Register (0x680)Bit R/W Description Default


1 = Edge 0 = Level

0x00

Table 8-44 GPIO 15-8 Interrupt High/Low Register (0x681)Bit R/W Description Default


1 = Active high / rising edge0 = Active low / falling edge

Note: Function depends on whether the bit is in level or edge mode.

0x00

Table 8-45 GPIO 15-8 Both-Edge Register (0x682)Bit R/W Description Default


1 = Both-edge mode enabled0 = Both-edge mode disabled

Note: The GPIO bit must be in edge mode for both-edge mode to work.

0x00


This register allows software to easily determine which GPIO 7-0 signals are available on the board. All GPIO signals use shared backplane pins and are only available when the board is configured with the appropriate build option.

NOTEEven when a port is not available due to a build option, the port may still be visible to software. Availability of these ports is build option dependent.

Table 8-46 GPIO 15-8 Interrupt Status Register (0x683)Bit R/W Description Default

7:0 R/W GPIO15:GPIO8 (Write 1 to Clear)

1 = Interrupt pending0 = No interrupt

0x00

Table 8-47 GPIO 15-8 Availability Register (0x684)Bit R/W Description Default


NA


NA


NA


NA


NA


NA


NA


NA

Table 8-48 Ethernet Port Availability Register (0x6A0)Bit R/W Description Default

7:0 R Ethernet ports 7:0 availability0 = Ethernet port is not available1 = Ethernet port is available

NA


Table 8-49 COM Port Availability Register (0x6A1)Bit R/W Description Default

7:0 R COM 8:1 Availability

0 = COM8:1 is not available1 = COM8:1 port is available

NA

Table 8-50 COM Port Wire Configuration Register (0x6A2)Bit R/W Description Default

7:0 R COM Port 8:1 4 Wire Configuration

0 = COM Port is available in 2-wire (TX/RX) mode only1 = COM Port is available in 4-wire (RS232 or RS422) mode

NA

Table 8-51 COM Port Full Modem Line Configuration Register (0x6A3)Bit R/W Description Default

7:0 R COM Port 8:1 Modem Configuration

1 = Full modem line support is available0 = Full modem line support is not available

NA

Table 8-52 SATA Port Availability Register (0x6A4)Bit R/W Description Default

7:0 R SATA Ports 7:0 availability

1 = SATA ports are available0 = SATA ports are not available

NA

Table 8-53 USB 2.0 Port 7-0 Availability Register (0x6A5)Bit R/W Description Default

7:0 R USB2.0 ports 7:0 availability

1 = USB2.0 ports are available0 = USB2.0 ports are not available

NA




NA





NA




NA

Table 8-57 Display Availability Register (0x6A9)Bit R/W Description Default

7:0 R Display 7:0 availability

1 = Display is available0 = Display is not available

NA

Table 8-58 VGA Display Availability Register (0x6AA)Bit R/W Description Default

7:0 R Display 7:0 VGA availability

1 = Display is VGA type0 = Display is not VGA type

NA

Table 8-59 DisplayPort Availability Register (0x6AC)Bit R/W Description Default

7:0 R Display 7:0 DisplayPort availability

1 = Display is DisplayPort type0 = Display is not DisplayPort type

NA


Table 8-60 Ancillary/Audio Availability Register (0x6AD)Bit R/W Description Default

7 R Front Panel I/O available1 = Front Panel I/O 0 = No Front Panel I/O

NA

6-5 R Reserved NA

4 R COM Port 4 present on front panel1 = COM Port 4 present0 = COM Port 4 not present

NA


NA


NA


NA

0 R Audio available1 = Audio is available0 = Audio is not available

NA

Table 8-61 Front Panel Configuration Register (0x6AE)Bit R/W Description Default

7 R Ethernet port 1 present on front panel1 = Ethernet Port1 present0 = Ethernet Port1 not present

NA

6 R SATA port 1 present on front panel1 = SATA Port1 present0 = SATA Port1 not present

NA

5 R USB 2.0 port 1 present on front panel1 = USB2.0 Port1 present0 = USB2.0 Port1 not present

NA

4 R Video port 1 present on front panel1 = Video Port1 present0 = Video Port1 not present

NA

3 R Ethernet port 0 present on front panel1 = Ethernet Port0 present0 = Ethernet Port0 not present

NA

2 R SATA port 0 present on front panel1 = SATA Port0 present0 = SATA Port0 not present

NA

1 R USB2.0 port 0 present on front panel1 = USB2.0 Port0 present0 = USB2.0 Port0 not present

NA

0 R Video port 0 present on front panel1 = Video Port0 present0 = Video Port0 not present

NA


Table 8-62 XMC/PMC1 I/O Configuration Register (0x6AF)Bit R/W Description Default

7 R P64s compliant configuration1 = I/O is P64 compliant0 = I/O is not P64 compliant

NA

6 R Reduced P64s configuration1 = I/O is a subset of P640 = I/O is not a subset of P64

NA

5:4 R Reserved NA

3 R XMC X12d configuration1 = I/O is X12d compliant0 = I/O is not X12d compliant

NA


NA

1 R XMC X24s configuration1 = I/O is X24s compliant0 = I/O is not X24s compliant

NA


NA

Table 8-63 XMC/PMC2 I/O Configuration Register (0x6B0)Bit R/W Description Default

7 R P64s compliant configuration1 = I/O is P64 compliant0 = I/O is not P64 compliant

NA

6 R Reduced P64s configuration1 = I/O is a subset of P640 = I/O is not a subset of P64

NA

5:4 R Reserved NA


NA


NA


NA


NA


Table 8-64 SSD Availability Register (0x6B1)Bit R/W Description Default

7:0 R SSD7:SSD0 availability1 = SSD available0 = SSD not available

NA

Table 8-65 SSD Hardware Secure Erase Availability (0X6B2)Bit RW Description Default

7:0 R SSD7:0 Secure Erase capability0 = Hardware Secure Erase not available1 = Hardware Secure Erase available

When available, indicates that triggering a hardware erase function will result in a secure erase algorithm being executed.

(Hardware Secure Erase not currently available, but maybe in the future)

0x00

Table 8-66 UART Enable Register (0x6B8)Bit R/W Description Default

7:0 R/W COM8:1 UART Enable1 = UART is enabled0 = UART is disabled and will not respond to reads or writes.

NA

Table 8-67 COM Port Transceiver Enable Register (0x6BB)Bit R/W Description Default

7:0 R/W COM8:1 Enable1 = COM Port transceivers enabled0 = COM Port transceivers disabled

Software should set this bit to a ‘1’ after the desired COM port mode (i.e. RS232/RS422) is set.

NA

Table 8-68 COM Port Mode Register (0x6BC)Bit R/W Description Default

7-4 R/W COM8:1 mode1 = COM Port transceiver in RS422 mode0 = COM Port transceiver in RS232 mode

NA


NOTETo trigger a fast erase, enable bit must be written with a '1','0','1' pattern on consecutive write cycles to this register. This is to protect against "accidental" erase functions. The value read from this register represents the state of the output and not the last value written.

Table 8-69 COM Port RS485 Auto Direction Control Enable Register (0x6BD)Bit R/W Description Default

7:0 R/W COM8:1 RS485 Auto Direction Control mode1 = COM Port RS485 Auto Direction Control enabled. When enabled, this mode causes the RTS signal to assert and enable the transceiver whenever there is data ready to be transmitted on the port. Otherwise, the transceiver is tri-stated.

0 = COM Port RS485 Auto Direction Control disabled.

Note: This bit can only be set to a ‘1’ when the corresponding bit in the COM port Mode register (0x6BC) is set to “RS422 mode”.

0x00

Table 8-70 COM Port Loopback Enable Register (0x6BE)Bit R/W Description Default

7:0 R/W COM8:1 Loopback Enable1 = COM Port transceiver loopback mode enabled0 = COM Port transceiver loopback mode disabled (normal operation)

Loopback mode can be used by test software to test the basic functionality of the transceiver.

0x00

Table 8-71 SSD Erase Control Register (0x6BF)Bit R/W Description Default

7:0 R/W SSD7:0 Hardware erase1 = Hardware Erase pin active0 = Hardware Erase pin negated

0x00

Table 8-72 SSD Cache Flush Control Register (0x6C0)Bit R/W Description Default

7:0 R/W SSD7:0 Cache Flush1 = Cache Flush pin active0 = Cache Flush pin negated

This bit directly controls the cache flush pin of the SSD device.

0x00


Table 8-73 Scratch Pad Register (0x6C6)Bit R/W Description Default

7:0 R/W SCRATCH_PAD7:SCRATCH_PAD0 0x00

Table 8-74 PMC1/XMC1 Status Register (0x6C8)Bit R/W Description Default

7 R XMC1 Presence1 = XMC1 is fitted0 = XMC1 is not fitted

NA

6 R XMC1 VPWR voltage 0 = XMC1 VPWR rail is 5 V1 = XMC1 VPWR rail is 12 V

NA

5 R XMC1 BIST status1 = XMC1 BIST is active0 = XMC1 BIST is not active

NA

4:3 R Reserved NA

2 R PMC1 enumeration-ready status1 = PMC1 ERDY pin is active (OK to enumerate)0 = PMC1 ERDY pin is not active

NA

1 R PMC1 VIO voltage1 = PMC1 VIO voltage = 5 V0 = PMC1 VIO voltage = 3.3 V

NA

0 R PMC1 Presence1 = PMC1 is fitted0 = PMC1 is not fitted

NA


Table 8-75 PMC2/XMC2 Status Register (0x6C9)Bit R/W Description Default

7 R XMC2 presence1 = XMC2 is fitted0 = XMC2 is not fitted

NA

6 R XMC2 VPWR voltage 0 = XMC2 VPWR rail is 5 V1 = XMC2 VPWR rail is 12 V

NA

5 R XMC2 BIST status1 = XMC2 BIST is active0 = XMC2 BIST is not active

NA

4:3 R Reserved NA

2 R PMC2 enumeration-ready status1 = PMC2 ERDY pin is active (OK to enumerate)0 = PMC2 ERDY pin is not active

NA

1 R PMC2 VIO Voltage1 = PMC2 VIO voltage = 5 V0 = PMC2 VIO voltage = 3.3 V

NA

0 R PMC2 Presence1 = PMC2 is fitted0 = PMC2 is not fitted

NA

Table 8-76 SSD Status Register (0x6CB)Bit R/W Description Default

7:0 R SSD7:0 Write Protect Status1 = SSD is write protected 0 = SSD is not write protected

NA


Table 8-77 Write Protection Status Register (0x6CC)Bit R/W Description Default

7 R PCIe to PCI-X Bridge EEPROM status1 = Write protected0 = Not Write protected

0

6 R Ethernet SPI status1 = Write protected0 = Not Write protected

0

5 R SPD EEPROM status1 = Write protected0 = Not Write protected

0

4 R Reserved 0

3 R Boot SPI status1 = Write protected0 = Not Write protected

0

2 R Recover Boot SPI status1 = Write protected0 = Not Write protected

0

1 R NVRAM status1 = Write protected0 = Not Write protected

0

0 R Reserved 0

Table 8-78 Board Jumper/Link Status Register (0x6CD)Bit R/W Description Default

7 R NVRAM Link status1 = Link is installed 0 = Link is not installed

0

6 R Recovery boot link status1 = Link is installed0 = Link is not installed

0

5 R Write protect link status1 = Link is installed0 = Link is not installed

0

4:0 R Reserved 0


Table 8-79 Board Location Status Register (0x6CE)Bit R/W Description Default

7 R Reserved for Auto swap fail over 0

6:5 R Active Boot ROM location 1x = Active boot ROM is located on the test card (FACTORY ONLY)00 = Active boot ROM is the Main onboard ROM01 = Active boot ROM is the Recovery onboard ROM

0

4 R SPD Location1 = Board booted using SPD EEPROMs located on test card0 = Board booted using SPD EEPROMs located onboardDetermined by the state of the TAC SPD jumper link on the test card

0

3 R Ethernet configuration ROM location1 = Board booted using ethernet configuration ROM on test card0 = Board booted using ethernet configuration ROM onboard.

0

2:0 R Reserved 0

Table 8-80 Thermal Status Register (0x6D0)Bit R/W Description Default

7 R Reserved 0

6 R Ambient board temperature thermal alarm1 = Thermal alarm active0 = Thermal alarm NOT active

0

5 R Ambient board temperature alert alarm1 = Alert alarm active0 = Alert alarm NOT active

0

4:0 R Reserved 0

Table 8-81 Thermal Alarm Status Register (0x6D1)Bit R/W Description Default

7:4 R Reserved 0

3 R Processor Thermal Alarm Active1 = Thermal active0 =Thermal NOT active

0

2:0 R Reserved 0

Publication No. 500-9300007876-000 Rev. C.0 Specifications 109

9 • Specifications

Single slot 6U VME Single Board Computer

PCB

FR4 Multilayer

Size

• Total board size: 6U, 4 HP (XVR16)

Dimensions

• PCB: 233.35 mm x 178 mm x 20 mm (XVR16 single slot)

Weight

< 2.0 lb. Level 5

* If applicable, add weight of mounted Hard Disk Drive(s) or Solid State Drive(s).

RoHS compliance

XVR16 is RoHS compliant.

Conformal coating - Optional

MTBF - Calculations are available in accordance with MIL-HDBK-217

Levels

TIPRefer to Appendix D Processor Speed and Temperature for more information on High Temperature.

WARNINGThe ambient high temperature is dependent on the CPU that is used, the air flow, and other conditions. See Section 9.4 Environmental Conditions on page 113 for more details.

Table 9-1 Levels AvailableXVR16 Level 1 Level 2 Level 3 Level 4 Level 5

Low temperature

0 °C -20 °C -40 °C -40 °C -40 °C

High temperature

(See WARNING below regarding high temperatures.)

Front panel YES YES YES

Stiffener YES

Conformal coating

YES YES YES YES

Conduction cooling

YES YES

Lithium battery

YES YES


9.1 Power Consumption

The following table displays the power consumption of the XVR16.

For measurement purposes, the XVR16 board is mounted on a VME backplane. During measurement, the power consumption of the backplane, keyboard, and the hard disk drive are deducted from the results. The values measured are typical.

The i7 mobile processor is available in the following CPU option version:

• Quad Core (i7-4700EQ) 6 MByte Cache, up to 2.4 GHz

• When using onboard PMC modules, add power of the enabled PMC bridgesand the PMC module power consumption

• With an onboard hard disk drive, add the following values to the +5 V current:

– During power up, 0.9 A max.

– In an idle condition, 0.13 A typical

– During read/write access, 0.42 A typical

NOTEValues derived from the Fujitsu MHT 2060 AT data sheet

• For keyboard, mouse, etc., add 0.1 A (typical) to the +5 V current

• USB connector P1680 provides fused VCC voltage (+5 V). The total currentdrawn from this source may not exceed 1.0 A.

Table 9-2 CPU Power ConsumptionProcessor Memory Peak Power (3.3 V) Peak Power (5 V)

i7-4700EQIdleTest

16 GByte16 GByte

1.8 A3.5 A

6.8 A9.2 A

Note: Test conditions: T=25 °C, BIOS - defaults, Operating System = Windows 7 64-bit SP1 with Power Management - default, Test Software = Burn-In Pro V 7.1 running 2D video (70%), 3D video (70%), memory (70%), Disk (70%),

Ethernet (70%) and CPU (100%).

For every enabled PMC bridge (when adding PMC cards), add 0.45 A in addition to the PMC current requirement.


9.2 Onboard Lithium Battery

An onboard battery (BV1632_G) (130 mAh) supplies the XVR16 RTC. The estimated battery life time depends on temperature and power status. See the table below for battery life at non-operating mode (XVR16 power off, RTC supplied by battery) and operating mode (XVR16 power on, RTC supplied by power rail). The XVR16 RTC has a current consumption of 6A (board non-operating).

NOTEBatteries are installed in convection cooled version boards Levels 1 and 2. Levels 3, 4 and 5 do not have batteries installed.

9.2.1 Battery LifetimeThe battery lifetime varies with the temperature range.

Table 9-3 Battery LifetimeMode Temperature Range Lifetime in Years

Non-operating +10 °C to +85 °C 3.5

Non-operating -10 °C to +10 °C 2.5

Non-operating < -10 °C 2.0

Operating -20 °C to +65 °C 10.0


9.2.2 Battery in Vertical Holder; Removal/Replacement• Switch off power to unit

• Locate the battery on the computer

Figure 9-1 Battery Removal/Replacement

Removal

1. Apply pressure to the bottom of the battery on the solder side of the board.This pushes the battery up allowing more of it to be exposed on thecomponent side of the board.

2. The battery can then be grasped at the top and removed from the socket.

Replacement

A new battery can be installed by sliding it into the holder. Make sure to observe correct polarity.

1. Observe the proper polarity (+) (-).

2. Push the new battery down into the socket until the battery protrudesslightly through the board and the top retaining clips snap into place.


9.3 External Battery Input (+5VSTDBY)

Pin +5VSTDBY located at the VME connector P1 pin B31 can optionally supply current to the RTC and the IPMI controller while the XVR16 is in non-operating mode.

Without battery and without this +5VSTDBY supply voltage, the Real Time Clock oscillator must be started at each power up. The duration increases when operating at lower temperatures and can be up to around 30 seconds (at -40 °C). This delay is below one second at normal ambient temperatures.

When ordering a battery-less XVR16, the setup information is stored automatically within an onboard EEPROM and is updated via the standard UEFI Firmware Setup function. It is recommended to use an external supply voltage to this battery input to avoid the power-on oscillator start time and to preserve the date and time information.

The optional +5VSTDBY also supplies the IPMI controller while the XVR16 is in non-operating mode. See the following Table for +5VSTDBY current consumption.

9.4 Environmental Conditions

Ambient temperatures and humidity values for the XVR16.

NOTERefer to Appendix D Processor Speed and Temperature for more information on Maximum Operating Temperature.

* 3 dB/octave roll-off from 5 to 20 Hz and 6 dB/octave roll-off from 1000 to 2000 Hz

** No roll-off

Table 9-4 +5VSTDBY Current Consumption+5VSTDBY RTC IPMI

XVR16 operating mode 0 mA 0 mA

XVR16 non-operating mode 2 mA 85 mA

Table 9-5 Environmental ConditionsLevel 1 Level 2 Level 3 Level 4 Level 5

Cooling Method Convection Convection Convection Conduction Conduction

Conformal Coating Optional Standard Standard Standard Standard

High/Low TemperatureOperational

0 Cto55 C -20 Cto65 C -40 Cto75 C -40 CtoC -40 Cto85 C

Storage Temperature -40 Cto85 Ca -50 Cto100 C -50 Cto100 C -50 Cto100 C -50 °C to +100 C

Operational 300 ft/min airflow 300 ft/min airflow 600 ft/min airflow at cold wall at cold wall

Random Vibration 0.002g2/Hz* 0.002g2/Hz* 0.04g2/Hz** 0.1g2/Hz** 0.1g2/Hz**

Shock 20g*** 20g*** 20g*** 40g*** 40g***

Humidity Up to 95% RH Up to 95%RH***

a Limited to -40 Cto85C if the product includes a battery.* 20 to 1000 Hz, 6dB/Octave roll-off from 1000 to 2000 Hz** Random from 10 to 1000 Hz*** Peak sawtooth 11 ms duration


NOTEValues for shock and vibration are only valid for products without a hard disk drive (HDD) installed. For values of shock and vibration of HDDs, please see the specifications of the HDD manufacturer. For further information, please consult the Abaco technical support team.

Maximum Altitude Usage for the XVR16 is specified in the table below.

Level 4 and Level 5 boards are the only builds capable for use in a true vacuum environment. Level 3 boards may be operated in conditions that exclude a battery, but will still require forced air cooling. All other board levels contain batteries and do not have the possibility to cool without airflow.

9.5 Electrical CharacteristicsThe XVR16 requires supply voltages of +5 V and 3.3 V. +12 and -12 V are only required if needed on the PMC slot. The table below shows voltages with maximum current restrictions due to layout restrictions or fusing:

9.5.1 Supply Voltage RangeThe following ranges are defined by the VME64 specification ANSI/VITA 1-1994 for VME64 and ANSI/VITA 1.1-1997 for VME64 Extensions. The voltages must be measured at the backplane.

Table 9-6 Maximum Altitude UsageMaximum Altitude Level 1, 2, 3 Level 4, 5

Operating 4.5 km Vacuum

Storage 12 km Vacuum

Table 9-7 Supply VoltagesName Voltage Imax Description Fuse

+12 V +12 V 0.5 A Supply for PMC-Module

-12 V -12 V 0.2 A Supply for PMC-Module

USB_VCC 5 V 2.0 A Supply for front panel USB F1681 b

VTM+3.3 V 3.3 V 0.5 A Supply for transition module logic

b TPS2034D (Texas Instruments)

Table 9-8 Supply Voltage RangeSupply Voltage and Tolerance

+5 V 5.0 V +0.250 V / -0.125 V

+5 V STDBY 5.0 V +0.250 V / -0.125 V

+3.3 V 3.3 V +0.150 V / -0.050 V

+12 V 12.0 V +0.60 V / -0.36 V


9.5.2 GPIO 0...11The general purpose I/O pins can be used as inputs, with the following signal levels:

When used as outputs (open drain), the following signal levels are supplied:

9.5.3 IsolationIsolation of the Ethernet outputs, either front or rear, is limited to 500 V peak against GND and any other supply voltage. By itself, the onboard digital ground GND and the front panel/chassis frame ground FGND are isolated on the XVR16 with a layout distance of more than 0.3 mm in all PCB layers. However, most standard devices (keyboard, mouse, and monitor) except Ethernet, connects FGND and GND directly in the device. Also, standard racks connect both grounds at the power supply for safety reasons.

Table 9-9 GPIO IN Signal LevelsLevel Voltage

Low -0.3 V ... +0.8 V

High +2.0 V ... +3.75 V (Absolute Max Rating)

Table 9-10 GPIO OUT Signal LevelsLevel Voltage

Low +0.4 V at 6 mA sinking

High 10K Ohm Pull-up


A • Transition Modules

A.1 VTM26 Transition ModuleThis section describes the VTM26 Transition Module, compatible with the XVR16 and used for easy connection of I/O signals to standard connectors. Please refer to Figure A-1 for the location of available interfaces.

Figure A-1 VTM26 Transition Module

A.1.1 VGA InterfacesVGA1 Interface

(P4100) The analog signals of VGA1 are available in any XVR16 board version. The VTM26 provides these signals at a 15-pin SUB-D connector. The connector is available only if a hard-disk is not mounted. The RGB signals are terminated with 75 Ohm resistors at the transition module.

(P4100)VGA1

VGA2

COM2

COM1

DVI1/2

PWR

P2

P0

USB

USB0

USB1

eSATA1

SATA3

SATA4ETH3

ETH4

11

1

1

1

1

11

1

1A 1B 1C 1D1Z

1

77

CC

AA

SATA5

Onboard HD

SPDIFAudioOut

J2000

(P7201)

(P2200)

(P1751)

(P1720) (P1731)

(P5300)

(P5400)

(P1601)

(P7101)

(P2201)

(P2002)GPIO

(P2000)

COM2

PMC1 PMC2

MISC

(GPIO/HW_WP#)

SATA2

U1 Audio signalling

11

Connectors highlighted in Green are notloaded when the Hard Drive is loaded

Line inLine outCD in

(P4000)

(S2000)

(P2100)

(P2901)

(P4300)

(P1750)

(P1740)

(U1)

Publication No. 500-9300007876-000 Rev. C.0 Transition Modules 117

Figure A-2 VGA Interface (P4100)

VGA2 Interface (P4300)

The VGA2 interface is available at a 14-pin header connector (P4300). The RGB signals are terminated with 75 Ohm resistors at the transition module.

The signals are shared with PMC2 I/O signals. For availability, the correct version of XVR16 and VTM26 must be selected.

Table A-1 VGA1 Interface (P4100) P4100 Name

1 VGA1_RED

2 VGA1_GREEN

3 VGA1_BLUE

4 NC

9 +5 V

11 NC

12 VGA1_DDCData

13 VGA1_HSYNC

14 VGA1_VSYNC

15 VGA1_DDCClock

5, 6, 7, 8, 10 GND

VTM26

Table A-2 VTM26 VGA2 (P4300)P4300 Name

2 VGA2_RED

4 VGA2_GREEN

6 VGA2_BLUE

8 VGA2_HSYNC

10 VGA2_VSYNC2

12 VGA2_DDCData

13 VGA2_DDCClock

14 NC

1, 3, 5, 7, 9,11 GND


A.1.2 Serial Interfaces COM1 (P2100) and COM2 (P2200,P2201)

Figure A-3 Serial Interfaces COM1 and COM2

COM1 and COM2 ports are accessible via the transition module. COM1 is via a 10-pin har-Link® connector. Use adapter cable YLB-CR12-01 for the interface tothe 9-pin SUB-D connector.

COM2 is either at 10 pole headers or 9-pin SUB-D connectors. The SUB-D for COM2 is available only if a hard-disk is not mounted at the transition module.

The ports are software selectable for RS232 or RS422/485 operation. The RS485 output drivers can be enabled or disabled with the DTR signal. An active DTR means the drivers are always enabled. When using the RS422 setting, the output drivers are always enabled and the DTR signal is not used.

NOTE2100 is har-Link, P2200 is pin header.

* +5 V is fused with 2 A, however, for normal operation do not exceed 1 A at thispin.

Table A-3 VTM26 COM1 (P2100) P2100 har-Link Name RS232 Name RS422/485

1 DCD TXD-

2 DSR TXD+

3 RXD RTS-

4 RTS RTS+

5 TXD CTS+

6 CTS CTS-

7 DTR RXD+

8 RI RXD-

9 GND

10 +5 V*

VTM26VTM26


NOTEP2100 is har-Link, P2200 is pin header.

* +5 V is fused with 2 A, however, for normal operation do not exceed 1 A at thispin.

A.1.3 Ethernet Interface 10/100/1000BASE-T (P5300, P5400)Figure A-4 Ethernet Interface 10/100/1000BASE-T

The Ethernet interfaces for rear I/O requires usage of CAT 5 cable for proper operation with 100/1000BASE-T.

Table A-4 VTM26 COM2 (P2200, P2201)P2200 P2201 Name RS232 Name RS422/RS485

1 1 DCD TXD-

6 2 DSR TXD+

2 3 RXD RTS-

7 4 RTS RTS+

3 5 TXD CTS+

8 6 CTS CTS

4 7 DTR RXD+

9 8 RI RXD-

5 9 GND

10 +5 V*

Table A-5 VTM26 Ethernet Connectors (P5300, P5400)Ethernet 3, 4 10/100BASE 1000BASE

1 TxD+ DA+

2 TxD- DA

3 RxD+ DB+

4 NC DC+

5 NC DC

6 RxD- DB

7 NC DD+

8 NC DD


Two LEDs (green and yellow) are integrated into each of the RJ45 connectors. These LEDs indicate the link status and activity of the interface.

A.1.4 USB Connectors (P1600, P1601)Two channels are available at the standard USB connectors. FUSE_VCC is fused with 2 A, however, for normal operation, do not exceed 1 A at this pin.

Figure A-5 USB Connectors (P1600, P1601)

Table A-6 VTM26 LEDsLED Function

Right green LED

On Link is active

Off No link

Left yellow LED

On, blink Tx/Rx activity

Off No activity

Table A-7 VTM26 USB0 (P1600)Name P1600

FUSE_VCC* 1

USB0- 2

USB0+ 3

GND 4

Table A-8 VTM26 USB1 (P1601)Name P1601

FUSE_VCC* 1

USB1- 2

USB1+ 3

GND 4

VTM26


A.1.5 SATA ConnectorsAll SATA interfaces have redrivers for improved signal quality.

There are provisions for four SATA interfaces. In normal configuration, two SATA interfaces (SATA port 4 and port 5) are available at the VTM26.

SATA4 has only a cable connector P1740. SATA5 has either an eSATA connector (P1751) or a connector for direct mounting (P1750) a hard disk at the transition module. In this case, the front connector for COM2 and VGA1, are not available.

Figure A-6 eSATA5 Connector

Table A-9 SATAxx/eSATAPin Name

2 SATATXx+

3 SATATXx-

5 SATARXx-

6 SATARXx+

1, 4, 7 GND

Table A-10 SATA5 HD DirectSignal section Name

2 SATATX5

3 \SATATX5

5 \SATARX5

6 SATARX5

1, 4, 7 GND

Power section Name

1, 2, 3, 7, 8, 9 VCC3

4, 5, 6, 10, 11, 12 GND

13, 14, 15, NC

VTM26


A.1.6 Digital Video Connector DVI 1/2 (P4000)

Figure A-7 DMS59 Connector (P4000)

The VTM26 provides two DVI ports at the connector labeled DVI 1/2 on the VTM26 front panel. Use a split cable to connect to compliant DVI connectors. Due to layout reasons, the VTM26 physical DVI1 port is connected with split cable DVI connector with number ʺ2ʺ and the physical DVI2 port is connected with the split cable DVI connector with the number ʺ1ʺ.

Since DVI1 signals are shared with GPIO(0...9) and DVI2 signals are shared with PMC2 I/O, the correct XVR16 version must be selected for availability.

Figure A-8 DMS59 Connector Layout

VTM26 DMS59 Connector Digital Pin Assignments Table A-11 VTM26 DMS59 Connector Digital Pin Assignments DVI1 and DVI2

Pin Signal name Pin Signal name

1 GND 31 DVI2_TXC+

2 NC 32 DVI2_TXC-

3 NC 33 GND (DVI2_Data0 Shield)

4 GND 34 GND (DVI2_Data1 Shield)

5 +5 V* 35 GND (DVI2_Data2 Shield)

6 DVI2_SCL 36 DVI2_HTPLG

7 DVI2_SDA 37 NC

8 GND 38 GND

9 DVI1_SDA 39 NC

10 DVI1_SCL 40 DVI1_HTPLG

11 +5 V* 41 GND (DVI1_Data2 Shield)

12 GND 42 GND (DVI1_Data1 Shield)

13 NC 43 GND (DVI1_Data0 Shield)

14 NC 44 DVI1_TXC-

15 GND 45 DVI1_TXC+


*+5 V is fused with 2 A, however, for normal operation, do not exceed 1 A at this pin.

A.1.7 GPIO Connector (P2002)

* +5 V is fused with 2 A, however, for normal operation, do not exceed 1 A at this pin.

This connector shares the functions TMDS and GPIO. Only one function is available at the same time and is board specific.

16 DVI1_TX0+ 46 GND

17 DVI1_TX0- 47 NC

18 DVI1_TX1+ 48 NC

19 DVI1_TX1- 49 GND (DVI1_Clock Shield)

20 DVI1_TX2+ 50 NC

21 DVI1_TX2- 51 NC

22 GND 52 GND

23 NC 53 NC

24 GND 54 GND

25 DVI2_TX2+ 55 NC

26 DVI2_TX2- 56 NC

27 DVI2_TX1+ 57 GND (DVI2_Clock Shield)

28 DVI2_TX1- Key -

29 DVI2_TX0+ 58 NC

30 DVI2_TX0- 59 GND

Table A-12 GPIO Connector (P2002) P2002 Name

3 GPIO0

5 GPIO1

7 GPIO2

9 GPIO3

11 GPIO4

13 GPIO5

15 GPIO6

17 GPIO7

19 GPIO8

21 GPIO9

23 GPIO10

25 GPIO11

26* +5 V

10,12,14,16,18,20,22 GND

1, 2, 4, 6, 8,24 NC

Table A-11 VTM26 DMS59 Connector Digital Pin Assignments DVI1 and DVI2 (Continued)Pin Signal name Pin Signal name


A.1.8 Miscellaneous Connector (P2000)

* +5 V is fused with 2 A, however, for normal operation, do not exceed 1 A at this pin.

A.1.9 Audio PinoutsThe VTM26 provides audio connectors U1 for the audio signals and P2901 for SPDIFOUT.

Figure A-9 VTM26 Audio Pinouts

Table A-13 VTM26 Miscellaneous Connector (P2000)Name P2000 P2000 Name

NC 1 2 NC

\HW_WP 3 4 \STATLED

\BITFAILR 5 6 GND

\PWRBUT 7 8 GND

\SPEAKER 9 10 +5 V*

Table A-14 U1 and P2901 PinoutsPin Number Name

U1

1 LINE_OUT_L

2 LINE_OUT_R

3 GND

4 LINE_IN_L

5 LINE_IN_R

6 GND

7 CD_L

8 CD_COM

9 CD_COM

10 CD_R


A.1.10 PMC I/O ConnectorsThe PMC I/O signals of both the PMC slots are on a 64-pin male header (P7101/ P7201). Many signals of PMC2 I/O are shared with other interfaces. For availability, the correct version of XVR16 and VTM26 must be selected.

The following table lists the pin assignments of the PMC I/O signals on the 64-pin header.

Table A-15 PMC I/O ConnectorsP7101/P7201 Pin Pin P7101/P7201

PMCxIO_01 1 2 PMCxIO_02

































A.1.11 Write Protection (J2000)The VTM26 provides a Write Protection Jumper. If the jumper is off J2000, all programmable devices of the XVR16 are hardwired write protected. If the jumper is on J2000, all programmable devices of the XVR16 are NOT hardwired write protected. See the note at the end of section E.2 Non-Volatile Memory, on page 150 for additional information.

A.1.12 LEDThe rear status LED signals provide the board status at the VTM26. The signal already implemented the serial resistors on the XVR16.

A.2 VTM28 Transition ModuleThis section describes the VTM28 Transition Module. This transition module would be used with the XVR16 in the special case that the XVR16 ordering configuration has H = 0 and G = 1 or 4, in order to provide support for PMC I/O through two MEZZIO connectors for all of the XVR16 PMC I/O sites. If other signals are needed rather than PMC I/O, then it is recommended to purchase a VTM26 transition module or contact Sales for custom ordering options. Please refer to Figure A-10 for the location of available interfaces.

Table A-16 Rear BITFail Status LEDBITFAIL_LED Status LED (1k Ohm serial resistor at XVR16)

Built In Test Fail Red (1k Ohm serial resistor)

Table A-17 Rear Status LEDSTAT_LED Status LED (330Ohm serial resistor at XVR16)

UEFI Firmware started Green blinking

Loading OS Green steady on


Figure A-10 VTM28 Transition Module

DVI(J27)

COM1(J100)

USB0

USB1

LAN B

LAN A

(J30)

(J29)

(J24)

(J23)

COM2(P10)

(J31)VGA1

P2

P0

MEZZIO(J21)

WP(J14)

MEZZIO(J22)


A.2.1 VGA1 Interface (J31)The analog signals of VGA1 are available in any XVR16 board version. The VTM28 provides these signals at a 15-pin SUB-D connector. The RGB signals are terminated with 75 Ohm resistors at the transition module.

Figure A-11 VGA1 Interface (J31)

A.2.2 Serial Interfaces COM1 (J100) and COM2 (P10)Figure A-12 Serial Interfaces COM1 and COM2

COM1 and COM2 ports are accessible via the transition module. COM1 is via a 10-pin har-Link connector. Use adapter cable YLB-CR12-01 for the interface to the9-pin SUB-D connector. COM2 is via a 9-pin SUB-D connector.

The ports are software selectable for RS232 or RS422/RS485 operation. The RS485 output drivers can be enabled or disabled with the DTR signal. An active DTR means the drivers are always enabled. When using the RS422 setting, the output drivers are always enabled and the DTR signal is not used.

VTM28

VGA1StatusBITFailLAN BLAN AUSB1USB0COM1DVI 1/2RST

COM2

Table A-18 VGA1 Interface (J31) J31 Name

1 VGA1_RED

2 VGA1_GREEN

3 VGA1_BLUE

4 NC

9 +5 V

11 NC

12 VGA1_SDA

13 VGA1_HSYNC

14 VGA1_VSYNC

15 VGA1_SCL

5, 6, 7, 8, 10 GND


* +5 V is fused with 2 A, however, for normal operation do not exceed 1 A at this pin.

A.2.3 Ethernet Interface 10/100/1000BASE-T (J29, J30)

Figure A-13 Ethernet Interface 10/100/1000BASE-T

Table A-19 VTM28 COM1 (J100) J100 har-Link Name RS232 Name RS422/RS485

1 DCD TXD-

2 DSR TXD+

3 RXD RTS-

4 RTS RTS+

5 TXD CTS+

6 CTS CTS-

7 DTR RXD+

8 RI RXD-

9 GND

10 +5 V*

Table A-20 VTM28 COM2 (P10)P10 Name RS232 Name RS422/RS485

1 DCD TXD-

6 DSR TXD+

2 RXD RTS-

7 RTS RTS+

3 TXD CTS+

8 CTS CTS

4 DTR RXD+

9 RI RXD-

5 GND


The Ethernet interfaces for rear I/O requires usage of CAT 5 cable for proper operation with 100/1000BASE-T.

A.2.4 USB Connectors (J23, J24)Two channels are available at the standard USB connectors. FUSE_VCC is fused with 2 A, however, for normal operation, do not exceed 1 A at this pin.

Figure A-14 USB Connectors (J23, J24)

Table A-21 VTM28 Ethernet Connectors (J29, J30)LAN A, LAN B 10/100BASE 1000BASE

1 TxD+ DA+

2 TxD- DA-

3 RxD+ DB+

4 NC DC+

5 NC DC-

6 RxD- DB-

7 NC DD+

8 NC DD-

Table A-22 VTM28 USB0 (J23)Name J23

FUSE_VCC* 1

USB0- 2

USB0+ 3

GND 4

Table A-23 VTM28 USB1 (J24)Name J24

FUSE_VCC* 1

USB1- 2

USB1+ 3

GND 4


A.2.5 Digital Video Connector DVI 1/2 (J27)

Figure A-15 DMS59 Connector (J27)

The VTM28 provides one DVI port (DVI1) at the connector labeled DVI 1/2 on the front panel (the DVI2 signals are not available on the VTM28 transition module). The use of a split cable is required in order to connect to a compliant DVI connector. Due to layout reasons, the VTM28 physical DVI1 port is connected with split cable DVI connector with number ʺ2ʺ.

DVI1 signals are shared with GPIO(0...9).

Figure A-16 DMS59 Connector Layout

VTM28 DMS59 Connector Digital Pin Assignments Table A-24 VTM28 DMS59 Connector Digital Pin Assignments for DVI

Pin Signal name Pin Signal name

1 GND 31 NC

2 NC 32 NC

3 NC 33 GND

4 GND 34 GND

5 +5 V* 35 GND

6 NC 36 NC

7 NC 37 NC

8 GND 38 GND

9 DVI1_SDA/GPIO9 39 NC

10 DVI1_SCL/GPIO8 40 DVI1HOTPLUG

11 +5 V* 41 GND

12 GND 42 GND

13 NC 43 GND

14 NC 44 DVI1TXC-/GPIO1

15 GND 45 DVI1TXC+/GPIO0


*+5 V is fused with 2 A, however, for normal operation, do not exceed 1 A at this pin.

16 DVI1TX0+/GPIO2 46 GND

17 DVI1TX0-/GPIO3 47 NC

18 DVI1TX1+/GPIO4 48 NC

19 DVI1TX1-/GPIO5 49 GND

20 DVI1TX2+/GPIO6 50 NC

21 DVI1TX2-/GPIO7 51 NC

22 GND 52 GND

23 NC 53 NC

24 GND 54 GND

25 NC 55 NC

26 NC 56 NC

27 NC 57 GND

28 NC Key -

29 NC 58 NC

30 NC 59 GND

Table A-24 VTM28 DMS59 Connector Digital Pin Assignments for DVI (Continued)Pin Signal name Pin Signal name


A.2.6 PMC I/O Connectors (J21/J22)The PMC I/O signals of both the PMC slots are on a 64-pin male header (J21/J22). Many signals of PMC2 I/O are shared with other interfaces. For availability, the correct version of XVR16 and VTM28 must be selected.

Table A-25 and Table A-26 list the pin assignments of the PMC I/O signals on the 64-pin header. These tables represent two separate connectors (J21/J22) on theVTM28. One for PMC1/XMC1 I/O and one for PMC2/XMC2 I/O where nrepresents mezzanine site 1 or 2.

Table A-25 Mezzio Connector Rows A-J (J21/J22) Pin Row A Row B Row C Row D Row E Row F Row G Row H Row J

1 GND NC GND NC GND NC GND NC GND




5 GND XMCn_PMCn_07 GND XMCn_PMCn_03 GND XMCn_PMCn_08 GND XMCn_PMCn_04 GND






11 GND GND GND GND GND GND GND GND GND
















Table A-26 Mezzio Connector Rows K-T (J21/J22) Pin Row K Row L Row M Row N Row P Row Q Row R Row S Row T

1 GND SYSRESET~ GND 3V3_AUX GND +5V GND +5V GND
























25 GND GND GND GND GND NC GND NC GND


A.2.7 Write Protection (J14)The VTM28 provides a Write Protection Jumper. If the jumper is off J14, all programmable devices of the XVR16 are hardwired write protected. If the jumper is on J14, all programmable devices of the XVR16 are NOT hardwired write protected. See the note at the end of section E.2 Non-Volatile Memory, on page 150 for additional information.

A.2.8 LEDThe rear status LED signals provide the board status at the VTM28. The signal already implemented the serial resistors on the XVR16.

Table A-27 Rear BITFail Status LEDBITFAIL_LED Status LED (1k Ohm serial resistor at XVR16)

Built In Test Fail Red (1k Ohm serial resistor)

Table A-28 Rear Status LEDSTAT_LED Status LED (330Ohm serial resistor at XVR16)

UEFI Firmware started Green blinking

Loading OS Green steady on


B • BIOS Setup Utility

This appendix gives a brief description of the setup options in the system BIOS firmware. Due to the custom nature of Abaco’s SBCs, your BIOS firmware options may vary from the options discussed in this appendix.

To Access the First Boot setup screen, press the F7 key at the beginning of boot.

To access the setup screens, press the F2 or DEL key at the beginning of boot.

B.1 First Boot MenuThe XVR16 has a First Boot menu enabling the user to, on a one time basis, select a drive device to boot from. This feature is useful when installing from a bootable disk. For example, when installing an operating system from a CD, enter the First Boot menu and use the arrows keys to highlight ATAPI CD-ROM Drive. Press ENTER to continue with system boot.

This feature is accessed by pressing the F7 key at the very beginning of the boot cycle. The selection made from this screen applies to the current boot only, and will not be used during the next boot-up of the system.

If you have trouble accessing this feature, disable the QuickBoot Mode in the Main BIOS firmware, setup screen. Exit, saving changes and retry accessing the First Boot menu.

Table B-1 BIOS Firmware, First Boot Menu

Please select boot device:

SanDisk U3 Cruzer Micro 2.18

Enter Setup

and to move selection

ENTER to select boot device

ESC to boot using defaults

Publication No. 500-9300007876-000 Rev. C.0 BIOS Setup Utility 137

B.2 Main MenuThe Main next-generation BIOS firmware, setup menu screen has two main areas. The left frame displays the options that can be configured. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white and a text message in the right frame gives a brief description of the option.

The Main menu reports the BIOS firmware revision and allows the user to set the system’s clock and calendar. Use the left and right arrow keys to select other screens.

NOTEBelow is a sample of the Main screen. The information displayed on your screen will reflect your actual system.

Table B-2 BIOS Main Menu


B.3 Advanced Setup MenuThe Advanced BIOS firmware, Setup menu allows the user to configure some CPU settings, the IDE bus, SCSI devices and other external devices and internal drives.

Select the Advanced tab from the setup screen to enter the Advanced BIOS firmware, Setup screen. You can select the items in the left frame of the screen, such as Super I/O Configuration, to go to the sub menu for that item. You can display an Advanced BIOS firmware, Setup option by highlighting it using the <Arrow> keys. A sample of the Advanced BIOS firmware, Setup screen is shown below.

NOTEChanges in this screen can cause the system to malfunction. If problems are noted after changes have been made, reboot the system and access the BIOS firmware. From the Exit menu select ‘Load FailsafeDefaults’ and reboot the system. If the system failure prevents access to the BIOS firmware screens, refer to Section 4.2.1 Clear CMOS/RTC/Password on page 33 for instructions on clearing the CMOS.

Table B-3 BIOS Advanced Menu

Options shown may not be available on your system.


B.3.1 Set Processor Speed from the Advanced MenuThe processor speed can be changed as follows:

Set both items to the desired multiplier; i.e. 25 = 2.5 GHz, 20 = 2.0 GHz, etc.:

Advanced -> CPU Configuration -> Max Freq Ratio

Advanced -> CPU Configuration -> Max Boot Freq Ratio

This will set the maximum frequency allowable for the CPU. The allowable multiplier range varies depending on the processor. To restore the maximum frequency range to the original range, choose ̋ F3: Optimized Defaultsʺ and reboot the SBC.

B.3.2 Enabling/Disabling the GbE Boot-from-LAN BIOSFirmware

The Gigabit Ethernet boot-from-LAN BIOS firmware provides support for booting over the network.

NOTEIn order to boot from the network, some operating systems require that the network driver be set to “boot” within the Control Panel.

The Gigabit Ethernet boot-from-LAN BIOS firmware defaults to Enabled in the BIOS firmware, Setup Utility. The Advanced Menu of the BIOS firmware, Setup Utility, allows the boot-from-LAN BIOS firmware to be Enabled or Disabled. Table B-3 shows the Advanced Menu. Use the arrow keys to highlight the Onboard Device Configuration. Select ʹGigE Option ROMʹ in the submenu’s list and enter <+> until the option is set to Enabled or Disabled. Press F4 to Save and Exit the BIOS firmware, Setup Utility.


B.4 Chipset Setup MenuSelect the various options for chipsets located in the system (for example, the CPU configuration and configurations for the North and South Bridge). The settings for the chipsets are processor dependent and care must be used when changing settings from the defaults set at the factory.

Below is a sample of the Chipset Setup screen; the actual options on your system may vary.

NOTEChanges in this screen can cause the system to malfunction. If problems are noted after changes have been made, reboot the system and access the BIOS firmware. From the Exit menu select ‘Load FailsafeDefaults’ and reboot the system. If the system failure prevents access to the BIOS firmware screens, refer to Section 4.2.1 Clear CMOS/RTC/Password on page 33 for instructions on clearing the CMOS.

Table B-4 BIOS Chipset Menu


B.5 Server Management MenuThe Server Management Menu provides configuration options for watchdog timers and BIOS coordination and communication with the BMC. The menu reports the status of communication with the BMC as may be used to display data collected from the BMC: Self test information, Event logs, FRU data.

Table B-5 Server Mgmt Menu


B.6 Boot Setup MenuUse the Boot Setup menu to set the priority of the boot devices, including booting from a remote network. The devices shown in this menu are the bootable devices detected during POST. If a drive is installed that does not appear, verify the hardware installation. Also available in this screen are “Boot Settings” which allow the user to set how the basic system will act.

Table B-6 BIOS Boot Menu


B.7 Security Setup MenuThe Security setup provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first.

The system can be configured so that all users must enter a password every time the system boots or when setup is executed, using either the Supervisor password or User password.

Table B-7 BIOS Security Menu

To reset the security in the case of a forgotten password, you must clear the NVRAM and reconfigure. Refer to Section 4.2.1 Clear CMOS/RTC/Password on page 33 for instructions on clearing the CMOS.


B.8 Save & Exit MenuSelect the Save & Exit tab from the setup screen to enter the Save & Exit BIOS firmware, Setup screen. You can display the Save & Exit BIOS firmware, Setup option by highlighting it using the <Arrow> keys. The Save & Exit BIOS firmware, Setup screen is shown below.

Table B-8 BIOS Save & Exit Menu

If changes have previously been made in the BIOS firmware, and the system malfunctions, reboot the system and access this screen. Select ‘Restore Defaults’ and continue the reboot.

Publication No. 500-9300007876-000 Rev. C.0 Mezzanine Sites 145

C • Mezzanine Sites

C.1 PMC/XMC SlotThe PCI Mezzanine Card (PMC/XMC) interface is an additional slot for parallel mounted add-on cards. The interface is compliant to the IEEE 1386.1 specification and is based on the electrical and logical layer of the PCI specification. PMC slots are 66/100/133 MHz PCI-X capable.

• Both PMCs have a 3.3 V key mounted, for 3.3 V compatible PMC cards.

C.1.1 Electrical Characteristics

C.1.2 Mounting of PMC or XMC ModuleTo mount a PMC or an XMC board to the XVR16, follow these steps:

1. Remove XVR16 from system housing.

2. Remove the front panel cover of the PMC/XMC slot.

3. Take the PMC/XMC from inside through the front panel and then pressconnectors together.

4. Verify correct installation of the EMC gasket.

5. Affix the PMC/XMC onto the host boards with four screws. Screws must belocked with Loctite 243.

Table C-1 Electrical CharacteristicsParameter Comment Value

5 V Max. current on 5 V Pins 1.5 A c

3.3 V Max. current on 3.3 V Pins 2.3 A c

+12 V Max. current on +12 V Pin 0.1 A

-12 V a Max. current on -12 V Pin 0.1 A

V(I/O) b Voltage for PCI I/O 3 V or 5 V

P Max. power consumption total

7.5 W

a -12 V must be connected to the backplane.

b The appropriate key has to be mounted.

c Total power dissipation on 3.3 V and 5 V rail is 7.5 W.


Figure C-1 Mounting PMC/XMC Module onto XVR16

C.1.3 Secondary Thermal InterfaceOn conduction-cooled versions of boards and mezzanines, the PMC modules may be equipped with optional Secondary Thermal Interfaces. If the PMCs do not fit into their sockets on the XVR16 base board, you can remove them. Use a matching TORX screw driver to remove the Secondary Thermal Interfaces. For mounting, use a torque of 0.3 Nm to fix the screws or use minimum force to tighten the screws. Add only a short turn (~1/16th) when the screw starts to tighten.

PMC EMC Gasket

Front panel

Connectors

Standoff 10 mm long

Keying pin 5V

Host board Cover

Cross recessed pan head DIN7985 M2, 5x6 A2

Publication No. 500-9300007876-000 Rev. C.0 Mezzanine Sites 147

Figure C-2 Mounting of Secondary Thermal Interface on PMC Module

Screw M2 (03 Nm)

Secondary Thermal Interface


C.2 Installing HD-ADAP8 SATA Module

Figure C-3 Installing HD-ADAP8 SATA Module

HD-ADAP8 SATA Module

Publication No. 500-9300007876-000 Rev. C.0 Processor Speed and Temperature 149

D • Processor Speed and Temperature

The processor speed and the temperature are inter-dependent. This means that for a given temperature, a maximum processor speed is achievable before throttling, and conversely for a given processor speed before throttling, a maximum temperature is achievable. This is further affected by the build level, which dictates the maximum ambient temperature at which the board can operate (See >Chapter 9 • Specifications).

The processor speed can be set from the BIOS via the Advanced Tab on the Main Menu. Appendix B BIOS Setup Utility.

D.1 Quad Core (i7-4700EQ) 47 W, 2.4 GHz Processor OptionTable D-1 Maximum Operating Frequency versus Max Temperature for Quad Processor

NOTEThe thermal data from the table above was taken while the units were running multi-threaded test software used to stress the CPU, memory and I/O functions simultaneously. This test load is generally heavier than a standard embedded application. There may be some variance in the user’s thermal results based on the end application. Please contact Abaco Sales or Technical Support for any further thermal details or discussions relating to your specific application.

Maximum Operating 5 V DCA 3.3 V DCA

CPU Power Build Level Frequency Temperature Min Avg Max Min Avg Max Dissipation

Method

1 2.4 GHz 54°C 6.2 6.9 7.8 2.4 2.7 3.0

300LFM2.2 GHz 55°C 5.4 6.2 7.4 2.4 2.6 2.9

2 2.4 GHz 54°C 6.2 6.9 7.8 2.4 2.7 3.0

1.4 GHz 65°C 4.6 5.0 5.6 2.4 2.6 2.9

47W 3 2.4 GHz 69°C 5.9 6.8 8.0 2.4 2.7 2.9600LFM1.8 GHz 75°C 5.4 5.9 6.8 2.4 2.7 2.9

4 2.4 GHz 75°C 6.9 7.6 8.7 1.5 1.7 1.9Card Edge5 2.4 GHz 79°C 6.7 7.6 8.9 1.5 1.7 2.0

1.8 GHz 85°C 5.3 6.0 7.0 1.5 1.7 2.0Bold values indicate the maximum DC current.


E • Statement of Volatility

E.1 Volatile MemoryThis product contains volatile memory, i.e. memory in which the contents are lost when power is removed.

E.2 Non-Volatile MemoryThis product contains non-volatile memory, i.e. memory in which the contents are retained when power is removed.

Table E-2 Non-Volatile Memory

NOTEIn normal operation, all non-volatile memory except the FRAM (NVRAM U192) and optional SATA NAND (U190, U191) are write protected. In order to allow writes to these devices, or to change the write status of the NVRAM/NAND in the BIOS/UEFI setup, a jumper must be installed on header P6. See Figure 5-1, XVR16 Top View Interface of Levels 1, 2, 3 Version, on page 35 for location of header P6.

Table E-1 Volatile Memory

Type of Memory Size User Modifiable

User Data Access Function Process to Clear

SDRAM - 1.35 V 8, 16 GByte Yes Yes Contains run-time data Cleared upon power- off

Type of Memory Size User Modifiable

User DataAccess Function Process to Clear

U192 - NVRAM FRAM 55nS 3.3 V FRAM (MRAM) Ferroelectric Nonvolatile RAM

512 KByte Yes Yes Storage of user specific information

This memory space can be cleared by any utility capable of writing IO Space

U139,U140,U141 - SPI Flash 3.3 V

16 MByte Yes Yes Contains BIOS code, ME Firmware and BIOS settings

This memory space can be cleared by any utility capable of writing to the PCH SPI bus

U190, U191 - (Optional) SATA NAND Drive, 3.3 V, 1.2 V

8/32 GByte Yes Yes Solid State Flash Drive Any hard drive formatting utility

U144 - FPGA 3.3 V N/A No No Power up / reset logic, glue logic, LPC registers, Timers, Watchdog, NVRAM Access

JTAG via rear connector

U197 - I2C EEPROM 3.3 V 8 Kbit Yes Yes SPD information for DDR3 Memory

This memory space can be cleared by any utility capable of writing to the PCH I2C bus

U5 - EEPROM 3.3 V 32 kB Yes Yes User EEPROM This EEPROM can be cleared by any utility that can access the I2C/SMBus

U166-169 - (Optional) SPI Flash 3.3 V

2 kB Yes Yes Storage of Intel WGI210IT Ethernet Configuration

This memory space can be cleared by any utility capable of writing to the LAN SPI bus.

© 2016 Abaco Systems, Inc.All rights reserved.

* indicates a trademark of Abaco Systems,Inc. and/or its affiliates. All othertrademarks are the property of their respective owners.

Confidential Information - This document contains Confidential/Proprietary Information of Abaco Systems, Inc. and/or its suppliers or vendors. Distribution or reproduction prohibited without permission.

THIS DOCUMENT AND ITS CONTENTS ARE PROVIDED "AS IS", WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. ALL OTHER LIABILITY ARISING FROM RELIANCE ON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED.

Abaco SystemsInformation Centers

Americas:1-866-652-2226 (866-OK-ABACO)or 1-256-880-0444 (International)

Europe, Middle East and Africa:+44 (0) 1327 359444

Additional Resources

For more information, please visit theAbaco Systems website at:

www.abaco.com

Publication No. 500-9300007876-000 Rev. C.0

https://www.abaco.com/