Gate oxide damage: Testing approaches and methodologies

Gate oxide damage: Testing approaches and methodologiesCalvin T. Gabriel Citation: Journal of Vacuum Science & Technology A 17, 1494 (1999); doi: 10.1116/1.581842 View online: http://dx.doi.org/10.1116/1.581842 View Table of Contents: http://scitation.aip.org/content/avs/journal/jvsta/17/4?ver=pdfcov Published by the AVS: Science & Technology of Materials, Interfaces, and Processing Articles you may be interested in Plasma damage effects on low- k porous organosilicate glass J. Appl. Phys. 108, 094110 (2010); 10.1063/1.3506523 Development and instrumentation of an integrated three–dimensional optical testing system for application inintegrated circuit packaging Rev. Sci. Instrum. 76, 093109 (2005); 10.1063/1.2042647 High resolution sampling electrostatic force microscopy using pulse width modulation technique J. Vac. Sci. Technol. B 18, 626 (2000); 10.1116/1.591250 Designing test interconnect structures for micro-scale stress measurement: An analytical guidance J. Vac. Sci. Technol. B 17, 448 (1999); 10.1116/1.590574 Filter design methodology for defect detection in wafer inspection J. Vac. Sci. Technol. B 15, 2718 (1997); 10.1116/1.589714

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Gate oxide damage: Testing approaches and methodologiesCalvin T. Gabriela)

VLSI Technology, Incorporated, 1109 McKay Drive MS02, San Jose, California 95131

~Received 20 October 1998; accepted 8 March 1999!

The main types of gate oxide damage measurement techniques are examined and compared, leadingto a selection of ‘‘application-specific’’ damage measurement techniques. Each technique hasstrengths and weaknesses, so no single measurement can completely characterize damage. Instead,a combination of measurement approaches is needed, each one targeted to provide a piece of thedamage puzzle. It is helpful to understand the different damage mechanisms when selecting ameasurement technique, so a survey of mechanisms is given. Damage proceeds by either directexposure of the gate oxide~through ion bombardment or ultraviolet radiation! or by indirectexposure~by charging from a nonuniform plasma or from the presence of high aspect ratiostructures on the wafer!. The relative importance of each mechanism depends on process technologyand other factors. The most useful combination of damage measurement techniques includes surfacepotential measurement, electrically erasable read-only memory transistors, direct measurement ofcharging, antenna transistors, and passive voltage contrast. Damage measurements should becalibrated to device performance parameters such as yield or reliability. ©1999 AmericanVacuum Society.@S0734-2101~99!13404-3#

I. INTRODUCTION

Plasma processing of complementary metal–oxide–semiconductor~CMOS! devices has the potential to inducedamaging current flow through thin gate oxides. Many stud-ies have been undertaken to measure this damage, using avariety of measurement techniques.1 In response to the con-fusing array of measurement options available, it is natural toseek a single, simple technique for measuring damage, pref-erably one that requires no expertise or prior knowledge ofdamage mechanisms. However, to study gate oxide damage,a variety of complementary techniques and an understandingof damage mechanisms are needed, as will be shown here.

II. GATE OXIDE DAMAGE MECHANISMS

Mechanisms for damaging gate oxide during plasma pro-cessing must be understood to some extent before damagecan be measured intelligently. Fortunately, the understandingof damage mechanisms has matured in recent years. Themain mechanisms can be divided into those that indirectlyaffect gate oxide by charging conductors connected to thegate oxide and those that directly affect gate oxide by plasmaexposure.

Charging—the indirect method of damage—occursthrough both the nonuniform plasma mechanism and by to-pography dependent charging, also known as electric shad-ing. In a nonuniform plasma, a local imbalance between ionand electron current from the plasma leads to a localized netcurrent flux to the wafer.2 A conductor exposed to the plasmacan collect this current and, if connected to a gate electrode,cause it to pass through and damage the gate oxide. Thedamage occurs as electrons pass through and release theirenergy within the gate oxide, breaking Si–O bonds and cre-ating traps. The extent of damage caused by this Fowler–

Nordheim tunneling current depends on the amount ofcharge~current3time! that passes through the oxide. Charg-ing can also occur in a uniform plasma by topography de-pendent charging, which is essentially an interaction betweenthe plasma and structures on the wafer caused by the differ-ence in isotropy of electrons and ions crossing the plasmasheath to the wafer surface.3 In high aspect ratio spaces,isotropic electrons are hindered from reaching the bottom ofthe space, whereas anisotropic~and positively charged! ionsare not. Because insulating masks such as photoresist or ox-ide are commonly used when etching conductors, the under-lying film can acquire a positive charge by the topographydependent charging mechanism.

Damage from direct plasma exposure occurs from bothion bombardment of gate oxide exposed to the plasma andfrom ultraviolet ~UV! radiation that reaches the gate oxide.Ion bombardment causes localized structural damage andcontamination due to direct exposure of gate oxide to theplasma environment.4 In submicron processes, this occursbetween the end of gate etching and the beginning of thesubsequent spacer deposition—the only steps when gateedges are actually exposed to the plasma. UV radiation alsocauses damage by directly interacting with the gate oxide atgate edges. Typical dielectric films used in intermetal oxidestacks are mostly transparent to UV, however, so UV-induced damage can occur long after the gate edges havebeen covered by dielectric films.5

The relative importance of these damage mechanisms var-ies with process generation because of the evolution of gateoxide quality, plasma equipment design, process integration,and circuit design techniques. The trend in importance ofeach mechanism is shown graphically in Fig. 1. For 5mmmetal–oxide–semiconductor~MOS! process technologies,gate oxides were thick and damage was low, dictated bydirect exposure to the plasma through ion bombardment anda!Electronic mail: [email protected]

1494 1494J. Vac. Sci. Technol. A 17 „4…, Jul/Aug 1999 0734-2101/99/17 „4…/1494/7/$15.00 ©1999 American Vacuum Society


UV radiation because masked threshold voltage implantswere done over actual gate oxide. By the time 1.5mm pro-cess technologies arrived, however, this practice had ended.Today, direct exposure damage can only occur at the edgesof the gates in typical CMOS processes.

As gate oxides grew thinner and more sensitive to damagefor submicron technologies, charging from nonuniform plas-mas increased dramatically in importance. But within years,understanding of the problems caused by nonuniform plas-mas spread through the semiconductor equipment and inte-grated circuit ~IC! manufacturing industries, resulting inmore uniform plasmas because of improved plasma tools andprocesses. One study found that improving plasma nonuni-formity to 20% or better~an easily achieved value! preventedsignificant charging from occurring.6 However, topographydependent charging surged in importance as dimensionsshrank into the deep submicron range, causing an increase inaspect ratios and thus an enhanced susceptibility to topogra-phy dependent charging. High density plasma tools came tothe forefront at about this same time, adding to topographydependent charging because of their tendency to producehigher temperature electrons than conventional low densityplasmas.3 The contribution from topography dependentcharging exceeded charging from nonuniform plasmas nearthe 0.25mm process node.

As CMOS technology progresses below 0.25mm and gateoxide thickness descends below 5.0 nm, trends appear to bechanging significantly. Both forms of charging damage willdiminish in importance as the direct tunneling mechanismallows current to pass harmlessly through these extremelythin gate oxides.7 For a given plasma condition, currentsforced through gate oxide will certainly increase as the gateoxide is thinned. However, for oxides below about 40 Å, theenergy released by the current within the gate oxide willdecrease as electrons tunnel directly through the barrier. Butthe contributions of the direct exposure techniques will likelyincrease, with the role of UV radiation increasing most be-cause of the prevalence of high density plasmas and theircorrespondingly higher levels of UV radiation.5 Figure 2

shows an instance when the damaging effect of UV radiationexceeded that of charging.

This evolution in importance of gate oxide damagemechanisms suggests that there needs to be a correspondingevolution in damage measurement techniques. For instance,when studying damage from a typical 0.25mm process, ameasurement technique which is sensitive to UV radiationbut not to topography dependent charging would give littlerelevant information, yet this same technique could be veryuseful when studying damage from a 0.1mm process.

III. STUDYING THE DAMAGING POTENTIAL OF THEPLASMA

Damage measurement techniques can also be divided be-tween those that measure thesource of the damage~theplasma! and those that measure theeffectof the damage~onthe gate oxide!. To study the damaging potential of theplasma itself, the most useful measurement devices includeelectrically erasable read-only memory~EEPROM! transis-tors, surface potential measurement, also known as contact

FIG. 3. Current density–voltage (J–V) characteristic of two plasma pro-cesses and the Fowler–Nordeim oxide tunneling characteristic.Jox1 is thecurrent the oxide will experience in process 1, andJox2 is the current theoxide will experience in process 2. Figure courtesy of Wafer ChargingMonitors.

FIG. 1. Trend in relative contributions to gate oxide damage from majorsources. Process technology is referenced to the minimum physical gatelength.

FIG. 2. Effect of plasma exposure on threshold voltage shift, with and with-out UV radiation shield, for antennas with small~8000:1! and large~90,000:1! antenna area ratios. From Ref. 5.

1495 Calvin T. Gabriel: Gate oxide damage: Testing approaches and methodologies 1495

JVST A - Vacuum, Surfaces, and Films


potential difference or plasma damage monitoring, and directmeasurement techniques such as the Stanford plasma on-wafer real time~SPORT! probe.

EEPROM transistors are capable of ‘‘remembering’’ thepotentials and, using current-sensing resistors, the currentsthey experienced in the plasma.8 These structures can act asa passive plasma probe, allowing measurement of the currentdensity–voltage~J–V) characteristic of the plasma on thesurface of the wafer—each of multiple charge-flux sensorsprovides one point on theJ–V plot. Armed with theJ–Vplot and the gate oxide Fowler–Nordheim current–voltage(I –V) plot, the damaging effect of the plasma on a particulargate oxide can be predicted. An example result is shown inFig. 3, which compares the damaging effect of two plasmaprocesses. The current density and potential that will be ex-perienced by the oxide is dictated by the intersection of theplasma and oxide characteristics. Process 1 will be more

damaging than process 2 becauseJox1.Jox2. The maximumpotential is lower for process 1 than for process 2 (V1

,V2), but this does not translate into reduced damage be-cause current is too low at the maximum potential to damagethe gate oxide.

Design modifications can make EEPROM transistors sen-sitive to UV radiation. Topography dependent charging canbe studied as well by adding a high aspect ratio mask to thecharge-collecting electrode attached to the EEPROM transis-tor. This enables the test structure to more closely resembledevice structures that will be encountered on real wafers.Having realistic test structures can be crucial for studyingprocesses such as via etching—vias do not at all resemble alarge, unpatterned electrode. As shown in Fig. 4, a traditionalunpatterned charge-collecting electrode did not register highpotentials when placed in a via etching plasma, but highpotentials and very high current densities~not shown here!were detected when the charge-collecting electrode was pat-terned with via holes. The test structure must match reality todraw the correct conclusions.

A test structure that yields results similar to the EEPROMtransistor is the SPORT probe, which enables the real-timedirect measurement of currents and surface potentials.9 Anarrangement of conductive pads is built on a wafer and con-nected to wires leading from the wafer to outside of theplasma chamber, where voltages and currents can be inducedor monitored. The major drawback: The plasma tool willlikely need modification to accommodate these wires extend-ing from the wafer through the chamber walls.

The simple SPORT probe can be used to study topogra-phy dependent charging by adding a resist pattern to it, asshown in Fig. 5. For this case, the presence of the 0.5mmlines and spaces transformed what appeared to be a ratherbenign plasma into one quite capable of causing gate oxidedamage by increasing potential and current density in highaspect ratio spaces.10 Like a Langmuir probe, the SPORTprobe can also measure electron temperature and plasma po-tential ~Table I!, allowing a more detailed characterizationand minimization of the topography dependent chargingdamaging potential of the plasma. After establishing the ini-tial setup, this work can be done rapidly because of the real-time nature of the measurement technique.

FIG. 4. Peak positive potentials registered by EEPROM transistors in a viaetch plasma.~a! No photoresist pattern.~b! Charge collecting electrodespatterned with a via photoresist mask. Figures courtesy of Wafer ChargingMonitors.

FIG. 5. SPORT probeJ–V results with 0.5mm lines/spaces~‘‘shaded’’! andwithout ~‘‘bare pad’’!. From Ref. 10.


J. Vac. Sci. Technol. A, Vol. 17, No. 4, Jul/Aug 1999


Perhaps the simplest damage measurement technique issurface potential measurement. The test structure in this caseis merely an oxidized blank test wafer. Charge deposited bythe plasma is expected to reside on the relatively thick~e.g.,100 m! oxide until it can be measured with a noncontactsurface-potential sensor.11 Information is not collected re-garding topography dependent charging unless realistic teststructures are on the wafer, but this technique yields rapidresults for detecting certain charging conditions. An exampleis the power-lift process, an oxygen plasma used to neutral-ize residual charge in an oxide film and enable a wafer to beremoved from the electrode following plasma-enhanced ox-ide deposition. Surface potential measurement detected large

surface potentials on a wafer exposed to a power-lift process,while a control wafer experienced very low potentials~Fig.6!, in agreement with results from other damage testingtechniques.12

As with any damage measuring technique, surface poten-tial measurement can give misleading information in somecircumstances. It may reflect only the plasma charging be-havior at the instant before plasma is turned off in the finalplasma step. For example, when studying a magnetically en-hanced reactive ion etch plasma, the potentials left by thelaser position of the rotating magnetic field when the plasmawas extinguished were frozen in place on the wafer~Fig. 7!.In reality, the entire wafer would experience these variationsin surface potential as the magnetic field rotates during waferprocessing. UV-induced photoconduction may dissipate thecharge deposited on the oxide surface while the wafer is stillin the plasma, so results must be interpreted carefully.

IV. STUDYING THE EFFECT OF THE PLASMA ONGATE OXIDE

The techniques just described are used to study the dam-aging potential of the plasma. To study the effect that plasmadamage has on gate oxide, electrical parameters are mea-

FIG. 6. Surface potential measurement maps.~a! With the power-liftprocess.~b! Control wafer—no exposure to the power-lift process. FromRef. 12.

FIG. 7. Surface potential measurement map of a wafer exposed to magneti-cally enhanced reactive ion etch plasma. Figure courtesy of SemiconductorDiagnostics, Inc.

FIG. 8. Damage from via-intensive metal-1 antennas having an area ratio of70 200:1 as measured by threshold voltage shift following a Fowler–Nordheim stress (DVt), charge-to-breakdown (Qbd), and gate leakage (I g).From Ref. 13.

TABLE I. Comparison of SPORT and Langmuir probe measurements ofelectron temperature and plasma potential. From Ref. 10.

Pressure~mT!

SPORT probe Langmuir probe

Te~eV! Vp ~V! Te ~eV! Vp~V!

4 7.5 15.3 ••• •••5 7.9 14.5 7.4 15

10 6.1 12.7 6.5 13.420 4.7 10.7 5.9 1340 4.2 9.8 ••• •••60 3.9 9.3 ••• •••




sured appropriate for capacitors and transistors, typicallyconnected to large, conductive ‘‘antennas’’ over thick fieldoxide. Significant processing is required to build these teststructures, so feedback is slow and test wafer cost is highunless the same wafers are used for other purposes.

The transistors stressed from charge collected by the an-tenna can be characterized using a variety of techniques.Among the most popular device parameters to measure arethreshold voltage shift induced by a postprocess Fowler–Nordheim stress (DVt), charge-to-breakdown (Qbd), andgate leakage (I g). A comparison of the sensitivity of thesetechniques is given in Fig. 8. All three techniques registereddamage for a sufficiently large number of vias attached to afixed-size antenna, butQbd and DVt detected the onset ofdamage even earlier than didI g for this 6.5 nm gate oxide.13

When using large antenna structures like these, however,measuringI g is adequately sensitive for detecting damage.

When antenna area ratio is varied and failures are de-tected by a gate leakage measurement increase, charging isoccurring in the plasma. Figure 9~a! shows a case wherecharging was clearly detected through poly antennas but notthrough metal-1 antennas. More work would be required toisolate and optimize the exact plasma process causing thecharging. Antennas are well suited to studying topographydependent charging—if the antenna is designed as a comb-like or finger structure, then the spacing between lines—and

hence aspect ratio, defined as total film thickness divided byspace width—can be varied to determine its impact on dam-age. When failures increase for higher aspect ratios, as inFig. 9~b!, it is likely that the antennas have experienced to-pography dependent charging. In this case, gate stack thick-ness was 2750 Å, resist mask thickness was 4600 Å, andspace widths varied from 0.5 to 4.5mm.

Ion bombardment at the gate edges will affect the antennatransistor~not only the charge collector! just as it affectsnormal transistors. However, damage induced from chargecollected by the antenna may greatly exceed damage fromdirect ion bombardment of the gate oxide, so the antennatransistor dimensions must be varied if sensitivity to ionbombardment is desired. Antennas can also be designed withand without UV shields to study the role of UV radiation.5

Because antenna transistor structures are exposed to manyplasmas during complete wafer processing, it can be difficultto determine which step or steps cause damage. Short-loopexperiments may be required to isolate the offending pro-cess. A relatively new technique, borrowed from the failureanalysis world, may be more suitable than antenna transistorsfor this application. Passive voltage contrast, a scanningelectron microscope~SEM! technique for observing that ox-ide has been damaged, can be used for rapid feedback ondamage experienced by real wafers.14

When a wafer being processed through a fab is placed ina low-voltage SEM, any floating conductor present on thewafer surface will be charged by exposure to the electronbeam. If the conductor is connected to gate oxide that hasbeen sufficiently damaged, the electron beam current willflow to the substrate and the structure will appear brighterthan undamaged structures, which can still hold a charge.Thus, a simple, low-voltage SEM inspection can be used todetect charging damage in near real time during wafer pro-cessing. The technique is nondestructive, so the same wafercan be examined after several different steps to isolate adamage source. In one case, passive voltage contrast wasused to isolate charging to the Ti sputter deposition step.14

Reducing power during this step actually increased the inci-dence of failures observed by passive voltage contrast from13% to 20%. Reducing the rate of ramping the power on,however, resulted in no observed failures at high power.

Passive voltage contrast is especially useful for engineersattempting to solve a significant charging problem in an op-erating fab, where device wafers and a low-voltage in-lineSEM are readily available. The main drawback of thismethod is that it may not be sufficiently sensitive to detectvery low levels of charging—gate oxide must leak enough tocause a voltage contrast in a SEM. However, for dealingwith real charging in a real fab, passive voltage contrast is auniquely useful technique.

The various damage measurement techniques are summa-rized in Table II. The techniques for measuring the chargingsource ~EEPROM, SPORT, and surface charge measure-ment! tend to be fast, not dependent on gate oxide quality,and most useful for isolating the source of the charging to asingle step. However, the topography and structures present

FIG. 9. Gate leakage failures~defined as gate leakage>1 nA! for ~a! polyand metal-1 area-intensive antennas and~b! edge-intensive poly antennaswith 8000:1 area ratio having different aspect ratios~defined as total filmthickness divided by space width between the poly fingers!. Aspect ratiosare calculated including or excluding the mask thickness in the total filmthickness.




on the wafer may not match real devices, and these tech-niques study isolated steps rather than the integrated process.Still, they are useful for focusing on individual steps—developing and characterizing plasma tools and optimizingprocesses. The techniques for measuring the effects of dam-age to gate oxide~passive voltage contrast and device param-eter degradation of antenna capacitors and transistors! benefitfrom being based on fully integrated processing of real to-pography and device structures, but they tend to be slow anddependent on gate oxide quality. It may be difficult to useantenna structures to precisely isolate the charging source;passive voltage contrast does not suffer much from this limi-tation. These techniques are most useful for process integra-tion and to gain an overview of damage sources and trendsfor a particular process technology.

V. JUDGING THE SERIOUSNESS OF DAMAGE

Every plasma process damages gate oxide to some extent,and given a sufficiently sensitive damage measurement tech-nique, that damage can be detected. Resources for dealingwith damage are generally limited, however, so damage thatdegrades device performance must be distinguished fromtrivial—albeit detectable—levels of damage. There are nouniversal guidelines for making this distinction: each gateoxide, each integrated process, and each circuit design has adifferent sensitivity to damage.

Ideally, a large number of device wafers would be pro-cessed while also making damage measurements, allowing acorrelation between device performance and damage to bedetermined. In a recent study, thousands of wafers contain-ing both yielding devices and scribe-line antenna transistorswere processed.15 The damage detected by the antenna tran-sistor gauge was obviously significant in this case—ICs onwafers with damaged antenna transistors yielded 1%–7%lower than ICs on wafers with undamaged ones. An examplefrom this comparison is shown in Fig. 10. Carrying out asimilar ~if less ambitious! study is helpful when beginning adamage study, to enable the proper priority and attention tobe given to the results and to ‘‘calibrate’’ the various damagemeasurement techniques that will be used.

VI. SUMMARY

There is no single ideal gate oxide damage measurementtechnique—most approaches have some useful applications.Each has advantages and disadvantages, so the choice oftechniques is application specific. To understand, minimize,and then monitor damage, a variety of techniques must beavailable in one’s damage measurement ‘‘toolbox’’ or somesources of damage may be overlooked or overemphasized.

An understanding of damage mechanisms is helpful todetermine the most relevant measurement techniques. Gateoxide can be damaged indirectly by charging during plasmaprocessing, which arises from two main sources: plasmanonuniformity and topography dependent charging. Damagecan also occur directly to the gate oxide when it is exposedto ion bombardment or UV radiation. The relative contribu-tion from each damage source changes with process technol-ogy, with charging sources generally diminishing in impor-tance and direct exposure techniques increasing inimportance as the industry draws closer to 0.1mm processes.

To study the damaging potential of the plasma, surfacepotential measurement provides a rapid and simple techniquewhile EEPROM transistors and SPORT are more detailed

TABLE II. Comparison of major damage measurement techniques.

Technique Measure damage source Measure damage effect

Examples EEPROM, SPORT, surface charge Passive voltage contrast, devicemeasurement parameter degradation of antenna

capacitors/transistorsStrengths Fast Real topography and structures

Independent of gate oxide Processes are fully integratedquality

Isolates damage sourceWeaknesses Wafer topography and structures May be slow

may not match real devices Dependent on gate oxide qualityLooks at isolated, not integrated, May be difficult to precisely

processes isolate damage sourceUses Plasma tool development and Process integration

characterization Overview of damage sourcesProcess optimization and trends

FIG. 10. Effect on product yield distribution for wafers that experiencedcharging ~defined as a 25 mV threshold voltage for a particular antennatransistor structure located in the scribe line!. From Ref. 15.




and capable of predicting the damage level expected fromboth nonuniform plasma charging and topography dependentcharging. To study the effect that plasma damage has on gateoxide, antenna transistors remain the most sensitive andcomprehensive, but passive voltage contrast provides an al-ternative that is simpler and closer to real time. All of thesetechniques are sensitive to charging, but only those with thepossibility of high aspect ratio structures on the surface willbe sensitive to topography dependent charging. Sensitivity todirect damage from ion bombardment and UV radiation var-ies with the technique and the test structures chosen for thattechnique.

When a combination of these methods is used to studydamage, a more complete picture emerges, enabling rapiddetection and elimination of a variety of significant damagesources while minimizing the risk of overlooking majorsources or exaggerating minor ones.

1C. T. Gabriel, Semicond. Int.20, 151 ~1997!.2C. T. Gabriel and J. P. McVittie, Solid State Technol.35, 81 ~1992!.3K. Hashimoto, Jpn. J. Appl. Phys., Part 132, 6109~1993!.4X.-Y. Li, T. Brozek, P. Aum, D. David, and C. R. Viswanathan, 1995IEEE International Rel. Physics Proceedings, Las Vegas, Nevada, 1995,p. 260.

5G. Bersuker, J. Werking, S. Anderson, and D. Chan, Proceedings of the1998 Third International Symposium on Plasma Process-Induced Dam-age, Honolulu, HI, 1998, p. 231.

6R. Patrick, P. Jones, and W. En, Proceedings of the 1997 Second Inter-national Syposium on Plasma Process-Induced Damage, Monterey, CA,1997, p. 255.

7M. Alavi, S. Jacobs, S. Ahmed, C.-H. Chern, and P. McGregor, Proceed-ings of the 1997 Second International Symposium on Plasma Process-Induced Damage, Monterey, CA, 1997, p. 7.

8W. Lukaszek, International Wafer Level Rel. Workshop, Lake Tahoe,CA, October, Part 1, 1992, p. 101.

9S. Murakawa and J. McVittie, Jpn. J. Appl. Phys., Part 133, 4446~1994!.10S. Siu and R. Patrick, Proceedings of the 1998 Third International Sym-

posium Plasma Process-Induced Damage, Honolulu, HI, 1998, p. 136.11A. M. Hoff, T. Esry, and K. Nauka, Solid State Technol.39, 139 ~1996!.12K. P. Cheunget al., Proceedings of the 1998 Third International Sympo-

sium Plasma Process-Induced Damage, Honolulu, HI, 1998, p. 18.13C. T. Gabriel and J. L. Educato, Proceedings of the 1997 Second Inter-

national Symposium on Plasma Process-Induced Damage, Monterey, CA,1997, p. 91.

14V. Liang, S. Bothra, H. Sur, and S. Sengupta, Proceedings of the 1998Third International Symposium on Plasma Process-Induced Damage, Ho-nolulu, HI, 1998, p. 148.

15J. R. Luchies, P. Simon, F. Kuper, and W. Maly, Proceedings of the 1998Third International Symposium on Plasma Process-Induced Damage, Ho-nolulu, HI, 1998, p. 7.




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Gate oxide damage: Testing approaches and methodologies