Full Custom Design Flow

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Outlineintroduction

Pre-Layout Simulation ( Hpsice )

Layout ( Laker )

Verification ( Calibre )

Post-Layout Simulation ( Hspice )

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interduction

CIC18

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Pre-Layout Simulation* HspiceInputxxx.lishspice job concluded

Pre-Layout Simulation*sp

Pre-Layout Simulationsp*

Pre-Layout SimulationspEx*

Pre-Layout Simulation*

Pre-Layout SimulationHspiceC D E,F,G,H I : J JFETK Mutual inductorL M MOSFETQ BJTO,T,U V : X *

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Pre-Layout SimulationHspiceZero (0) is always GroundGround may be 0, GND, GND

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Pre-Layout SimulationHspiceAnalysis type. tran()Ex : .tran 0.01n 100n

Output parameter. optionEx: option post *Graph file. Probe *(awaves)

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Pre-Layout SimulationHspiceTransient source statementsTypes of independent source functionPulse (pulse function) clock

Sinusoidal (sin function)

Exponential (exp function)

Piecewise linear (pwl function)

Single-frequency FM (sffm function)

Single-frequency AM (am function)

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Pre-Layout SimulationHspicePulse function : pluse syntax: pulse(v1 v2 )

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Pre-Layout SimulationHspice ExVin 1 0 PULSE ( 0V 5V 10ns 10ns 10ns 40ns 100ns )

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Pre-Layout SimulationHspicePiecewise linear function : pwl: pwl( )

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Pre-Layout SimulationExvAin Ain 0 PWL(0n 0v 9.9ns 0v 10ns vsupply 19.9ns vsupply 20ns 0v 24.9ns 0v 25ns vsupply 29.9ns vsupply r 0)ExvBin Bin 0 PWL(0n 0v 4.9ns 0v 5ns vsupply 14.9ns vsupply 15ns 0v 24.9ns 0v 25ns vsupply 29.9ns vsupply r 0)

*ainbin

Pre-Layout SimulationHspiceC.subcktEx.subckt name n1 .ends

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Pre-Layout SimulationMOSFET :MOSM Exmp0 out ain vdd vdd p_18 w=1.5u l=0.18u

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Pre-Layout SimulationMOSFET : Exmn0 out ain gnd gnd n_18 w=0.5u l=0.18u

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Pre-Layout Simulation*

Nand

Pre-Layout SimulationHspicedelay Syntax.MEASURE DC|AC|TRAN result_var TRIG ... TARG ... Ex .meas tran delay_1 trig v(ain) val='meas_val' rise=1 + targ v(out) val='meas_val' rise=3

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Pre-Layout SimulationHspicePower Syntax.MEASURE DC|AC|TRAN result FUNC out_var + Ex.meas tran Power avg p(xnand2) from'1*t_cycle' to '10*t_cycle'

Pre-Layout SimulationHspicePower-Delay Product(PDP) Ex.meas tran sum_PDP_1 param='delay_1*Power'

Pre-Layout SimulationdelaypowerRC*

Pre-Layout SimulationCosmosScopeScope

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Pre-Layout SimulationPlotfilesHspice*

Pre-Layout Simulation*

Pre-Layout Simulationnandainbin10

*ainbinout

Layout ( Laker )layoutspring_softlakerlakercalibre(DRC)(LVS)RC *

Layout ( Laker )library

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Layout ( Laker )Library nameTechnology file*

Layout ( Laker )

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Layout ( Laker )cell

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Layout ( Laker )library

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Layout ( Laker )tool*

Layout ( Laker )toolContactMetalPolyDiffussionNwellPIMPNIMP

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Layout ( Laker )rkcCtrl+mmosoCtrl or shitf+z

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Layout ( Laker )(n-well)

Layout ( Laker )nandlayout

Layout ( Laker )layoutDRC

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Verification ( Calibre )RuleRun DRC

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Verification ( Calibre )

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Verification ( Calibre )Rule

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Verification ( Calibre )LVS(Layout Versus Schematic)

Verification ( Calibre )Rule

Verification ( Calibre )InputsNetlist

Verification ( Calibre )Run LVS

Verification ( Calibre )

Verification ( Calibre )LVS Report

Verification ( Calibre )debug

Post-Layout Simulation ( Hspice )PEX

Post-Layout Simulation ( Hspice )

Post-Layout Simulation ( Hspice )InputNetlis

Post-Layout Simulation ( Hspice )Output

Post-Layout Simulation ( Hspice )RuleInputsOutputsRunPEX

Post-Layout Simulation ( Hspice )(scope)

Post-Layout Simulation ( Hspice )ainbinout

Post-Layout Simulation ( Hspice )RCdelaypower

Post-Layout Simulation ( Hspice )layout(Pre-sim)(Post-sim)

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