1..FLIP & FLOP A traditional flip-flop circuit based on bipolar junction transistors

In electronics, a flip-flop is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. A circuit incorporating flip-flops has the attribute of state; its output depends not only on its current input, but also on its previous inputs. Such a circuit is described as sequential logic. Where a single input is provided, the circuit changes state every time a pulse appears on the input signal. Since the flip-flop retains the state after the signal pulses are removed, one type of flip-flop circuit is also called a "latch". Other types of flip-flops may have inputs that set a particular state, set the opposite state, or change states, depending on which input is pulsed.

Flip-flops are used as data storage elements, for counting of pulses, and for synchronizing randomly-timed input signals to some reference timing signal. Flip-flops are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

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TYPES OF FLIP & FLOP

D flip-flop

D flip-flop symbol

The D flip-flop is the most common flip-flop in use today. It is better known as data or delay flip-flop (as its output Q looks like a delay of input D).

The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low).[23] It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.

Truth table:

Clock D Q Qprev

Rising edge 0 0 X

Rising edge 1 1 XNon-Rising X Qprev

T FLIP AND FLOP

T flip-flop

A circuit symbol for a T-type flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:

(expanding the XOR operator)

and can be described in a truth table:

T flip-flop operation[25]

Characteristic table Excitation table

T Q Qnext Comment Q Qnext T Comment

0 0 0 hold state (no clk) 0 0 0 No change0 1 1 hold state (no clk) 1 1 0 No change1 0 1 toggle 0 1 1 Complement1 1 0 toggle 1 0 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be

2 MHz. This "divide by" feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Qprevious is connected to the D input through an XOR gate). A T flip-flop can also be built using an edge-triggered D flip-flop with its D input fed from its own inverted output.

JK FLIP & FLOPJK flip-flop

A circuit symbol for a positive-edge-triggered JK flip-flop

JK flip-flop timing diagram

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

NOTE: The flip-flop is positive-edge triggered (rising clock pulse) as seen in the timing diagram.

The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

JK Flip Flop operation[25]

Characteristic table Excitation tableJ K Qnext Comment Q Qnext J K Comment0 0 Q hold state 0 0 0 X No change0 1 0 reset 0 1 1 X Set1 0 1 set 1 0 X 1 Reset1 1 Q toggle 1 1 X 0 No change

Rs flip and flop

) SR flip-flop - (Or "RS flip-flop") A "set/reset" flip-flop in which activating the "S" input will switch it to one stable state and activating the "R" input will switch it to the other state.

The outputs of a basic SR flip-flop change whenever its R or S inputs change appropriately. A clocked SR flip-flop has an extra clock input which enables or disables the other two inputs. When they are disabled the outputs remain constant.

If we connect two clocked SR flip-flops so that the Q and /Q outputs of the first, "master" flip-flop drive the S and R inputs of the second, "slave" flip-flop, and we drive the slave's clock input with an inverted version of the master's clock, then we have an edge-triggered RS flip-flop. The external R and S inputs of this device are latched on one edge (transition) of the clock (e.g. the falling edge) and the outputs will only change on the next opposite (rising) edge.

If both R and S inputs are active (when enabled), a race condition occurs and the outputs will be in an indeterminate state. A JK flip-flop avoids this possibility.

2..Counter In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal

Types.

Up/down counter

A counter that can change state in either direction, under the control of an up/down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.

4..Digital logic design

Combinational And Sequential Circuit Analysis And Design, Digital Circuit Design Optimization Methods Using Random Logic Gates, Multiplexers, Decoders, Registers, Counters, And Programmable Logic Arrays. Computer Aided Tools In The Design, Simulation, And Testing Of Digital Circuits.

Importance of digital logic design

New, due to popular request! I have received a number of questions regarding the internal structure and operation of logic gates. This is not as simple as it may seem, because there are many different ways to implement logical functions electronically. Therefore, I am now adding some new pages on the major logic families and their internal operation.

I've also had some requests regarding building and demonstrating actual circuits to perform logical functions. If you'd like to get some hands-on experience, I've set up a series of pages on breadboarding logic circuits to demonstrate their operation. If these prove as popular as I expect, I will add to the list soon.

Digital or binary logic has fascinated many people over the years. The very idea that a two-valued number system can possibly be the basis for the most powerful and sophisticated computers seems astounding, to say the least. Nevertheless, it is so, and the how and the why of this requires some explanation.

Everything in the digital world is based on the binary number system. Numerically, this involves only two symbols: 0 and 1. Logically, we can use these symbols or we can equate them with others according to the needs of the moment. Thus, when dealing with digital logic, we can specify that:

0 = false = no 1 = true  = yes

 

Using this two-valued logic system, every statement or condition must be either "true" or "false;" it cannot be partly true and partly false. While this approach may seem limited, it actually works quite nicely, and can be expanded to express very complex relationships and interactions among any number of individual conditions.

One essential reason for basing logical operations on the binary number system is that it is easy to design simple, stable electronic circuits that can switch back and forth between two clearly-defined states, with no ambiguity attached. It is also readily possible to design and build circuits that will remain indefinitely in one state unless and until they are deliberately switched to the other state. This makes it possible to construct a machine (the computer) which can remember sequences of events and adjust its behavior accordingly.

Applications

Digital electronicsFrom Wikipedia, the free encyclopediaJump to: navigation, search

Digital electronics represent signals by discrete bands of analog levels, rather than by a continuous range. All levels within a band represent the same signal state. Relatively small changes to the analog signal levels due to manufacturing tolerance, signal

attenuation or parasitic noise do not leave the discrete envelope, and as a result are ignored by signal state sensing circuitry.

In most cases the number of these states is two, and they are represented by two voltage bands: one near a reference value (typically termed as "ground" or zero volts) and a value near the supply voltage, corresponding to the "false" ("0") and "true" ("1") values of the boolean domain respectively.

An industrial digital controller

Intel 80486DX2 microprocessor

Digital techniques are useful because it is easier to get an electronic device to switch into one of a number of known states than to accurately reproduce a continuous range of values.

Digital electronic circuits are usually made from large assemblies of logic gates, simple electronic representations of Boolean logic functions.[1]

Advantages

One advantage of digital circuits when compared to analog circuits is [2] that signals represented digitally can be transmitted without degradation due to noise. For example, a continuous audio signal, transmitted as a sequence of 1s and 0s, can be reconstructed without error provided the noise picked up in transmission is not enough to prevent identification of the 1s and 0s. An hour of music can be stored on a compact disc as about 6 billion binary digits.

In a digital system, a more precise representation of a signal can be obtained by using more binary digits to represent it. While this requires more digital circuits to process the signals, each digit is handled by the same kind of hardware. In an analog system,

additional resolution requires fundamental improvements in the linearity and noise characteristics of each step of the signal chain.

Disadvantages

Disadvantages

In some cases, digital circuits use more energy than analog circuits to accomplish the same tasks, thus producing more heat which increases the complexity of the circuits such as the inclusion of heat sinks. In portable or battery-powered systems this can limit use of digital systems.

For example, battery-powered cellular telephones often use a low-power analog front-end to amplify and tune in the radio signals from the base station. However, a base station has grid power and can use power-hungry, but very flexible software radios. Such base stations can be easily reprogrammed to process the signals used in new cellular standards.

Digital circuits are sometimes more expensive, especially in small quantities.

Most useful digital systems must translate from continuous analog signals to discrete digital signals. This causes quantization errors. Quantization error can be reduced if the system stores enough digital data to represent the signal to the desired degree of fidelity. The Nyquist-Shannon sampling theorem provides an important guideline as to how much digital data is needed to accurately portray a given analog signal.

Analog issues in digital circuits

Digital circuits are made from analog components. The design must assure that the analog nature of the components doesn't dominate the desired digital behavior. Digital systems must manage noise and timing margins, parasitic inductances and capacitances, and filter power connections.

Bad designs have intermittent problems such as "glitches", vanishingly-fast pulses that may trigger some logic but not others, "runt pulses" that do not reach valid "threshold" voltages, or unexpected ("undecoded") combinations of logic states.

Additionally, where clocked digital systems interface to analogue systems or systems that are driven from a different clock, the digital system can be subject to metastability where a change to the input violates the set-up time for a digital input latch. This situation will self-resolve, but will take a random time, and while it persists can result in invalid signals being propagated within the digital system for a short time.

Since digital circuits are made from analog components, digital circuits calculate more slowly than low-precision analog circuits that use a similar amount of space and power. However, the digital circuit will calculate more repeatably, because of its high noise immunity. On the other hand, in the high-precision domain (for example, where 14 or more bits of precision are needed), analog circuits require much more power and area than digital equivalents.

Structure of digital systems

Engineers use many methods to minimize logic functions, in order to reduce the circuit's complexity. When the complexity is less, the circuit also has fewer errors and less electronics, and is therefore less expensive.

The most widely used simplification is a minimization algorithm like the Espresso heuristic logic minimizer within a CAD system, although historically, binary decision diagrams, an automated Quine–McCluskey algorithm, truth tables, Karnaugh Maps, and Boolean algebra have been used.

Representations are crucial to an engineer's design of digital circuits. Some analysis methods only work with particular representations.

The classical way to represent a digital circuit is with an equivalent set of logic gates. Another way, often with the least electronics, is to construct an equivalent system of electronic switches (usually transistors). One of the easiest ways is to simply have a memory containing a truth table. The inputs are fed into the address of the memory, and the data outputs of the memory become the outputs.

For automated analysis, these representations have digital file formats that can be processed by computer programs. Most digital engineers are very careful to select computer programs ("tools") with compatible file formats.

To choose representations, engineers consider types of digital systems. Most digital systems divide into "combinational systems" and "sequential systems." A combinational system always presents the same output when given the same inputs. It is basically a representation of a set of logic functions, as already discussed.

Automated design tools

To save costly engineering effort, much of the effort of designing large logic machines has been automated. The computer programs are called "electronic design automation tools" or just "EDA."

Simple truth table-style descriptions of logic are often optimized with EDA that automatically produces reduced systems of logic gates or smaller lookup tables that still produce the desired outputs. The most common example of this kind of software is the Espresso heuristic logic minimizer.

Most practical algorithms for optimizing large logic systems use algebraic manipulations or binary decision diagrams, and there are promising experiments with genetic algorithms and annealing optimizations.

To automate costly engineering processes, some EDA can take state tables that describe state machines and automatically produce a truth table or a function table for the combinational logic of a state machine. The state table is a piece of text that lists each state, together with the conditions controlling the transitions between them and the belonging output signals.

It is common for the function tables of such computer-generated state-machines to be optimized with logic-minimization software such as Minilog.

Often, real logic systems are designed as a series of sub-projects, which are combined using a "tool flow." The tool flow is usually a "script," a simplified computer language that can invoke the software design tools in the right order.

Tool flows for large logic systems such as microprocessors can be thousands of commands long, and combine the work of hundreds of engineers.

Writing and debugging tool flows is an established engineering specialty in companies that produce digital designs. The tool flow usually terminates in a detailed computer file or set of files that describe how to physically construct the logic. Often it consists of instructions to draw the transistors and wires on an integrated circuit or a printed circuit board.

Trade-offs

Several numbers determine the practicality of a system of digital logic. Engineers explored numerous electronic devices to get an ideal combination of fanout, speed, low cost and reliability.

The cost of a logic gate is crucial. In the 1930s, the earliest digital logic systems were constructed from telephone relays because these were inexpensive and relatively reliable. After that, engineers always used the cheapest available electronic switches that could still fulfill the requirements.

The earliest integrated circuits were a happy accident. They were constructed not to save money, but to save weight, and permit the Apollo Guidance Computer to control an inertial guidance system for a spacecraft. The first integrated circuit logic gates cost nearly $50 (in 1960 dollars, when an engineer earned $10,000/year). To everyone's surprise, by the time the circuits were mass-produced, they had become the least-expensive method of constructing digital logic. Improvements in this technology have driven all subsequent improvements in cost.

With the rise of integrated circuits, reducing the absolute number of chips used represented another way to save costs. The goal of a designer is not just to make the simplest circuit, but to keep the component count down. Sometimes this results in slightly more complicated designs with respect to the underlying digital logic but nevertheless reduces the number of components, board size, and even power consumption.

For example, in some logic families, NAND gates are the simplest digital gate to build. All other logical operations can be implemented by NAND gates. If a circuit already required a single NAND gate, and a single chip normally carried four NAND gates, then the remaining gates could be used to implement other logical operations like logical and. This could eliminate the need for a separate chip containing those different types of gates.

The "reliability" of a logic gate describes its mean time between failure (MTBF). Digital machines often have millions of logic gates. Also, most digital machines are "optimized" to reduce their cost. The result is that often, the failure of a single logic gate will cause a digital machine to stop working.

Digital machines first became useful when the MTBF for a switch got above a few hundred hours. Even so, many of these machines had complex, well-rehearsed repair procedures, and would be nonfunctional for hours because a tube burned-out, or a moth got stuck in a relay. Modern transistorized integrated circuit logic gates have MTBFs greater than 82 billion hours (8.2×1010) hours,[5] and need them because they have so many logic gates.

3..Explain memories in term of digital logic design?

DECODING LARGE MEMORIES

Large memories such as the 16 KB memory have row and column decoders that split the input address into a row address and a column address and activate a row and column select lines respectively. The row and column select lines select a location in the memory array. The memory is arranged in a two-dimensional manner instead of the linear address method discussed earlier. The reason for adopting a row and column decoder to independently but simultaneously select a location by its unique row and column number is to speed up the decoding process. As the memories get larger the decoders that decode and select a unique memory location also become very large with large number of gates. Due to the increased level of gates of the decoding circuitry the delay in decoding the input address increases, thereby slowing the memory access. A large address split into row and column addresses and separately decoded by row and column decoders requires comparatively smaller decoders with fewer number of gates resulting in fast decoding times and thereby faster memory access. The block diagram of a memory using row and column decoders is shown. Figure 40.1.

Detail circuitry of the Input/Output Buffer is shown which manages the control of the Data In and Data Out lines. Figure 40.2. When the W, write signal is active and the memory chip is selected CS, the top AND gate is selected and the bottom AND gate is

disabled. The data applied at the Data In/Out bi-directional lines is stored in the selected latches. When the W signal is inactive and the CS and OE signals are active the bottom AND gate is selected which enables the tri-state buffers connected at the end of the data out lines leading from the latch outputs. This allows data from the selected latches to be available on the Data In/Out lines.

The Reading and Writing of data is done by activating the various memory signals in a proper sequence. The Memory Read Cycle controls the memory for reading of data and a Memory Write Cycle controls the memory for writing of data.

Memory Read Cycle

The timing diagram of the read cycle is shown. Figure 40.3. To read data from the memory, the Read Cycle is initiated by applying the address signals. The valid address needs to be maintained stable for a specified duration tRC the read cycle time. Next, the CS and

theOEsignals are activated, after a delay of tGQ, the output enable access time measured with

respect to the high-to-low transition of the OE signal, valid data appears on the data lines. The tAQ, address access time is measured from the beginning of the valid address that appears on the address lines to the appearance of valid data on the data lines. The time tEQ measures the chip enable access time which is the time for the valid data to appear after the

high-to-low transition of the chip select signalCS.

Memory Write Cycle

The timing diagram of the write cycle is shown. Figure 40.4. To write data to the memory, the Write Cycle is initiated by applying the address signals. The valid address needs

to be maintained stable for a specified duration tWC the write cycle time. Next, theCSand

the WE signals are activated. The write enable signal WE is activated after a minimum time of ts(A) the address setup time which is measured from the beginning of the valid address. The

time for which the WE signal remains active is known as the write pulse width. After the WE signal becomes active the data that is to be written in the memory at the addressed location is applied at the data lines. The WE signal must remain valid after data is applied at

the data input lines and must remain valid for a minimum time duration tWD. The data must

remain valid for a time th(D), hold time after the WE signal is deactivated.

Figure 40.4 Timing diagram of a Write Cycle

Synchronous Burst SRAM

RAM chips are subdivided into Asynchronous RAM (ASRAM) and Synchronous Burst RAM (SB SRAM).The Static memory described is an Asynchronous SRAM, the operation of which does not depend upon the clock signal. The read and write operations are carried out asynchronously. Synchronous SRAM uses a clock signal which is used by the microprocessor to synchronize its activities to synchronize the read and write operations for faster operation. The block diagram of a Synchronous Burst SRAM is shown. Figure 40.5.

BURST

I/O0-I/O7 8 8 Data Input/Output

Synchronous RAM is very similar to the Asynchronous RAM, in terms of the memory array, the address decoders, read/write and enable inputs. In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. In the diagram, the external address,

the WE and the CS external signals are latched in on a positive clock transition simultaneously. The data that is to be written into the memory is also latched into the Data Input Register at the same positive clock transition. For a read operation the data is latched in the Data Output register on the positive clock transition. There are two variations of the Synchronous SRAM, the Flow-through and the Pipelined SRAM. In the Flow-through SRAM there is no Data Output Register so the data is asynchronously available on the data lines during a read operation. In the Pipelined version there is a Data Output Register which latches in the data read from the memory array.

The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to read or write up to four locations using a single address. When an external address is latched in by the Address register, the lower two bits of the address are connected to the Burst logic circuitry which internally increments the addresses at each clock transition producing four different addresses 00, 01, 10 and 11. For example, if an external base address of 37A0 H is stored in the Address Register, the Burst Logic circuitry produces addresses 37A0, 37A1, 37A2 and 37A3. The detailed Burst Logic circuit is shown. Figure 40.6.

Dynamic RAM

A static RAM uses a latch to store a single bit of information. Four gates are used to implement a latch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. A single memory cell is thus implemented using a single transistor and a capacitor which occupy lesser space as compared to the six transistors which are used to implement a single Static RAM cell. Thus the density of the capacitor based memory is significantly increased. The capacitor based memory is known

as a Dynamic RAM (DRAM). The drawback of DRAM is the discharging of the capacitor over a period of time. Unless the capacitor is periodically recharged all the information stored in terms of binary bits in a capacitor based memory array is lost. The extra circuitry required to refresh the capacitor complicates the operation of the DRAM.

The circuit diagram of a single DRAM capacitor based memory cell is shown. Fig 40.7a. The capacitor is connected through a MOSFET which connects or disconnects the column line at B to the capacitor at D. If the row is set at logic high the MOSFET connects the column line to the capacitor. If the row line is set to logic low the MOSFET disconnects the column line form the capacitor.

Refresh Column

Refresh

Row

Capacitor

DOUT

R/W

DIN

Figure 40.7a Writing a 1 or 0 into the DRAM cell

A write operation allows a logic 1 or 0 to be stored in a DRAM cell (capacitor). The appropriate cell is selected by specifying the address of the memory location which is decoded and the row connecting the desired cell is activated. The R / W signal is set to logic low indicating a write operation which enables the tri-state Input Buffer. The logic 1 which is to be stored in the memory cell is applied at the DIN data line which is available at A on the column line. The row line is selected (set to logic high) which allows the MOSFET to connect column B to capacitor D. The capacitor is charged to logic 1 voltage level via ABD. Figure 40.7a. A Write operation to store logic 0 in a DRAM cell is similar. The appropriate row is selected by

specifying the storage location address. The R / W signal is set to logic low which enables the Input Buffer. The logic 0 to be stored in the DRAM cell is applied at the DIN which is stored on the capacitor via ABD. Figure 40.7a. The thick line in the diagram indicates the data path from DIN to the storage capacitor.

The read operation is accomplished by specifying the address of the location from

which data is to be read. The DRAM address decoder activates the appropriate row. The R / W signal is set to logic high which enables the output buffer. The logic 1 or 0 stored on the capacitor is available at DOUT through path DBA. Figure 40.7b.

The capacitor can not retain the charge, therefore it has to be periodically charged through a refresh cycle. The Refresh Buffer is enabled by setting the Refresh signal to high. The input of the Refresh Buffer is connected to the output buffer/sense amplifier. The R / W signal is set to logic high during the Refresh cycle allowing the information stored on the capacitor to be available at the output of the Output Buffer/Sense amplifier. The information is feed back to the capacitor through the Refresh Buffer via path CBD. Figure 40.7c.

Input Buffer

Figure 40.7b Reading a 0 or 1 from the DRAM cell

Figure 40.7c Refreshing a DRAM cell

Address Multiplexing

DRAM chips use address multiplexing to reduce the number of address lines by half. The address required to select a memory location is split into row and column addresses. To access a DRAM location for reading or writing of information the row address is first applied at the address lines. The row address is latched by the Row Address Latch of the

DRAM memory chip. The column address is applied next at the same address lines. The column

address is latched by the Column Address Latch. Two signals RAS and CAS are used as strobe signals to control the Row Address and Column Address latches respectively. The external address lines are multiplexed as the same set of address lines are used to apply the row address and the column address at different time instances. The outputs of the Row Address Latch and the Column Address Latch are connected to the Row and Column Decoders which select a single row and column line selecting the storage cell to be accessed. Figure 40.8

Refresh Control and Timing

Decoder

DOUT

DIN

Figure 40.8 Circuit Diagram of a 1M x 1 DRAM

The R / W signal controls the Reading and Writing of data through the DOUT and DIN lines. The E signal enables the DRAM chip. The refresh cycle is controlled by the Refresh Control and Timing circuit which configures the Data Selector to select row addresses

generated by the refresh counter. During the refresh cycle all memory cells connected to the selected row are refreshed simultaneously. Therefore, a 1M bit DRAM arranged as 1024 rows and 1024 columns is refreshed by selecting all the 1024 rows in a sequence.