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BySHUVRA SAHA

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Contents Why Flash Memory?

Differences Between EPROM,EEPROM and Flash Memory Cell.

Usage of Flash memory cell in todays market.

Principles of Floating Gate Device.

Charge Injection Mechanism.

Hot Electron Injection.

Fowler-Nordheim Tunneling.

Industry-Standard Flash Cells

Basic Operationsa. Read.

b. Program.

c. Erase.

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Reliability

a) Programming Disturb.

b) Retention.

c) Endurance.

d) Erase Distribution.

Scaling Issues.

Flash Array Architectures.

Nor and Nand.

Parallel and Serial.

Block Diagram of Flash Memory Cell along with peripheralcircuitry.

Conclusion.

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Two type of CMOS Memory:

1)RAM: Information is lost once the power supply is

switched off. They are therefore volatile.a)SRAM

b)DRAM

2)ROM: They are non-volatile i.e. they keep information

stored also when the power supply is switched off.

a)EPROM: Electrically Programmable Read OnlyMemory.

b)EEPROM: Electrically Erasable and ProgrammableRead Only Memory.

c)Flash Memory.

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Comparative Study Of NVMs

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Why Flash?

EPROM EEPROM Flash Cell

ElectricallyProgrammable buterasable via exposure to

UV.

Both electricallyprogrammable anderasable.

Both electricallyprogrammable anderasable.

Single transistor cell.Density is more.

Two transistor cell.Density is less andoccupies more area.

Single transistor cell.Density is more.

Programmed by CHEinjection but erased byUV light.

Both programmed anderased by FN tunneling.

Mostly programmed CHEinjection but erased byFN tunneling.

Single bit programmablebut erase on the wholearray.

They allow bytealterability.

Single bit programmableand erase consist of largeno. of cellstogether(sector or block).

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Usage of Flash

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Floating Gate Device

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Charge Injection Mechanism

HOT ELECTRON INJECTION(mostly used forprogramming operation).

FOWLER-NORDHEIM TUNNELING(mostly used forerasing operation).

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Hot Electron Injection

Fowler-Nordheim Tunneling

An optimum thickness(10nm) is

chosen to trade off between

performance and reliability.

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Industry Standard Flash

Cell(ETOX)

EPROM TUNNEL OXIDE

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The Cell isasymmetrical

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Basic Operation On Flash Memory Cell

Operation Source Control Gate Drain

READ GND Vcc Vread

PROGRAM GND Vpp VddERASE(DV) Vpp GND FLOAT

ERASE(SV) Vcc Vneg FLOAT

12Vcc=5v,Vpp=12v,Vdd=5-7v,Vread=1v,Vneg=-8v

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Source breakdown is one of the major limiting factors to erase timereduction

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R i i it

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Re ia i ity

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Oxide Defects and Ionic Contamination

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Scaling

Reduction in Leff.

Reduction in operating voltages.

Limitation on tunnel oxide thickness to 7-8nm andinterpoly dielectric to be around 12-13nm.

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NOR architecture

NAND architecture

l h f l h

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General Architecture of Flash Memory System

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Fl h Chi

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Flash Chip

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To be continued

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THANK YOU

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