Flash Access Specification EPSON Flash Access Specification (Rev. 1.00) 4. Flash Access Create voice data to be written to the S1V3S344 internal flash memory using the Epson …

Rev.1.00

Flash Access Specification

S1V3S344 S1V3G340

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. The flash memory technology incorporated in this product is used under technical license from Silicon Storage Technology, Inc.

©SEIKO EPSON CORPORATION 2009, All rights reserved.

Contents

1. Introduction................................................................................................................................... 1

1.1 Scope ......................................................................................................................................... 1

1.2 Document structure .................................................................................................................... 1

1.3 Terminology ................................................................................................................................ 1

2. Overview ....................................................................................................................................... 2

3. Flash Access Mode Setup ........................................................................................................... 3

3.1 ISC_SPISW_IND........................................................................................................................ 4

3.2 Resetting from Flash Access mode ............................................................................................ 5

4. Flash Access................................................................................................................................. 6

4.1 S1V3S344 write processing........................................................................................................ 6

4.1.1 S1V3S344 erasing ............................................................................................................ 7

4.1.2 S1V3S344 writing.............................................................................................................. 7

4.2 S1V3S344 read processing ........................................................................................................ 8

4.3 S1V3G340 external SPI flash memory access ........................................................................... 9

5. Specifications for Flash Memory Writer Sample Program...................................................... 11

5.1 Overview................................................................................................................................... 11

5.2 Obtaining the sample program ................................................................................................. 11

5.3 Details of files ........................................................................................................................... 11

5.3.1 main_flashwrite.c............................................................................................................. 11

5.3.2 Message file .................................................................................................................... 11

5.3.3 ROMImage.h ................................................................................................................... 12

5.4 Specifications for main programs.............................................................................................. 13

5.4.1 main_flashwrite.c............................................................................................................. 13

5.5 Specifications for S1V3S344 flash memory access control APIs.............................................. 16

5.5.1 SPI_Initialize.................................................................................................................... 16

5.5.2 SPI_SendReceiveByte .................................................................................................... 17

5.5.3 SPI_SendByte ................................................................................................................. 18

5.5.4 SPI_SendMessage.......................................................................................................... 19

5.5.5 SPI_ReceiveMessage ..................................................................................................... 20

5.5.6 SPI_SetFlashAccessMode.............................................................................................. 21

5.5.7 SPI_EraseFlashData ....................................................................................................... 22

5.5.8 SPI_WriteFlashData ........................................................................................................ 23

Flash Access Specification EPSON i (Rev. 1.00)

ii EPSON Flash Access Specification

(Rev. 1.00)

5.5.9 SPI_VerifyFlashData ....................................................................................................... 24

5.5.10 GPIO_ControlChipSelect................................................................................................. 25

5.5.11 GPIO_ControlChipReset ................................................................................................. 26

1. Introduction

1. Introduction

1.1 Scope

This document describes various methods for accessing the internal 512-KB flash memory in the S1V3S344 and for accessing the external SPI flash memory used by the S1V3G340.

1.2 Document structure

Section 2 provides an overview of the S1V3S344 and S1V3G340.

Section 3 describes S1V3S344 and S1V3G340 Flash Access mode settings.

Section 4 describes methods for accessing the S1V3S344 and S1V3G340 flash memory.

Section 5 describes specifications for a sample program for writing data to the S1V3S344 flash memory.

1.3 Terminology

As used in these specifications, “L” and “H” correspond to the logical values “0” and “1,” respectively.

In these specifications, the term “flash voice guidance LSI” refers to both the S1V3S344 and S1V3G340.

In these specifications, the term “flash memory” refers to both the internal 512-KB flash memory in the S1V3S344 and the external SPI flash memory used by the S1V3G340.

In these specifications, the term “voice data” refers to the ROM image created using the Epson Speech IC Speech Guide Creation Tool.

In these specifications, the term “writing” refers to writing data to flash memory.

In these specifications, the term “reading” refers to reading data from flash memory.

In these specifications, the term “erasing” refers to erasing data from flash memory.

Flash Access Specification EPSON 1 (Rev. 1.00)

2. Overview

2. Overview

The flash voice guidance LSI supports sequential playback functions from flash memory. The flash memory used by the flash voice guidance LSI consists of 512-KB internal flash memory for the S1V3S344 and SPI flash memory connected externally for the S1V3G340.

In either case, the flash memory used must contain voice data created using the Epson Speech IC Speech Guide Creation Tool. For information on creating voice data, refer to the Epson Speech IC Speech Guide Creation Tool User Guide.

The flash voice guidance LSI must be set to Flash Access mode to store voice data to flash memory. When the flash voice guidance LSI is in Flash Access mode, the serial communication interface is connected directly to flash memory input and output.

In this state, voice data can be stored in flash memory by writing or erased, as described in greater detail later. Data can be read to confirm that the voice data is correctly stored on the flash memory.

The ISC_SPISW_IND message is used to set the flash voice guidance LSI to Flash Access mode.

Table 2.1 Flash voice guidance LSI specifications overview

Details Specifications

S1V3S344 S1V3G340

Flash Access mode setup method ISC_SPISW_IND message

Communication format Clock synchronous serial communications

Maximum serial clock frequency 1.024 MHz

Minimum serial clock frequency 500 kHz External SPI flash memory specifications

Erase 0xC7 External SPI flash memory specifications

(Rev. 1.00)

Write 0x02 External SPI flash memory specifications Command

Read 0x03

Erase Entire chip External SPI flash memory specifications

Write 1 byte External SPI flash memory specifications Processing unit

Read n bytes (continuous readout from specified address)

Flash memory writer sample program Yes No

Evaluation board Yes In place of S1V3S344 evaluation board

2 EPSON Flash Access Specification

3. Flash Access Mode Setup


Setting the flash voice guidance LSI to Flash Access mode connects the flash voice guidance LSI serial communication interface directly to the flash memory input and output.

The ISC_SPISW_IND message is sent to set the flash voice guidance LSI to Flash Access mode.

Figure 3.1 S1V3S344 Flash Access mode overview

Figure 3.2 S1V3G340 Flash Access mode overview



3.1 ISC_SPISW_IND

The flash voice guidance LSI switches to Flash Access mode 5 µs after the ISC_SPISW_IND message has been received. Note that the message start command, 0xAA, must be sent before ISC_SPISW_IND. (Refer to “3.2 Message Structure” in S1V3034x Series Message Protocol Specification.)

Table 3.1 ISC_SPISW_IND

Direction From host to flash voice guidance LSI

Purpose Used to set the flash voice guidance LSI to Flash Access mode

Byte Field Value

0 length(lsb)

1 length(msb) 0x0004

2 msg_id(lsb)

3 msg_id(msb) 0xFF00 – ISC_SPISW_IND

Figure 3.3 Flash Access mode setting timing chart


(Rev. 1.00)


3.2 Resetting from Flash Access mode

To return from Flash Access mode to Normal mode, perform a hardware reset by setting NRESET in the following sequence: H L H.

Figure 3.4 Flash Access mode reset timing chart


4. Flash Access

4. Flash Access

When the flash voice guidance LSI is in Flash Access mode, the serial communication interface is connected directly to the flash memory input and output.

In this state, voice data can be stored on the flash memory by writing or erasing, as described in greater detail later. Voice data stored on the flash memory can also be read.

Figures 4.1 and 4.2 show the individual pin states when in Flash Access mode.

The SIS for the S1V3S344 should be synchronized with the trailing edge of SCKS and changed using MSB first. The SIS for the S1V3S344 will be synchronized and latched with the leading edge of SCKS. The SOS for the S1V3S344 will be synchronized with the trailing edge of SCKS and changed using MSB first.

With the S1V3G340, individual pin operations must comply with the specifications for the external SPI flash memory used.

The only communication format available when using Flash Access mode is clock synchronized serial communications. Flash memory cannot be accessed directly using UART or I2C formats. For information on selecting communication formats, refer to “7.2 Serial interface” in the S1V3S344 Hardware Specification or S1V3G340 Hardware Specification.

Figure 4.1 S1V3S344 Flash Access mode pin functions

Figure 4.2 S1V3G340 Flash Access mode pin functions

4.1 S1V3S344 write processing

Before writing voice data to S1V3S344 internal flash memory, the flash memory must be initialized by erasing.


(Rev. 1.00)

4. Flash Access

Create voice data to be written to the S1V3S344 internal flash memory using the Epson Speech IC Speech Guide Creation Tool. For information on how to create voice data, refer to the Epson Speech IC Speech Guide Creation Tool User Guide.

Voice data must be written starting from address 0x000000 in the S1V3S344 internal flash memory. Sequential playback is not possible if the data write begins from any other address.

4.1.1 S1V3S344 erasing

Erasing the S1V3S344 internal flash memory cannot be made data-specific and will normally initialize all data from the chip. Initializing the S1V3S344 internal flash memory resets all bits to H.

An erase command must be issued to erase the S1V3S344 internal flash memory. The erase command is 0xC7.

The host must continue to output the clock signal to SCKS even after the erase command has been issued to complete data initialization within the S1V3S344. The time required to complete data initialization after the S1V3S344 receives the erase command is the SCKS minimum 1M cycle. This number of cycles is unrelated to the SCKS frequency and remains constant regardless of the frequency used for processing.

Figure 4.3 illustrates the timing chart for the process from issuing the erase command to completion of data initialization, together with subsequent writes. Writes should be performed in 1,024-byte blocks.

Figure 4.3 S1V3S344 erase timing chart

4.1.2 S1V3S344 writing

One data byte can be written at a time to S1V3S344 internal flash memory. To write data to the S1V3S344 internal flash memory, send data in the following sequence: Write command Write address Data to be written. The Write command is 0x02. The write address is 24 bits long.

After writing 1 byte of data, SCKS should be driven for at least 2 clock cycles before writing the next data. Writes should be repeated for at least 1,024 cycles. After the last data is written, drive SCKS for at least 128 clock cycles before proceeding to another process such as reading.


4. Flash Access

Figure 4.4 illustrates an example involving the writing of 1,024 bytes of data. Note that SCKS is driven for two cycles with NSCSS=H after the first write process has ended, before the next write process begins.

Figure 4.4 S1V3S344 write timing chart

4.2 S1V3S344 read processing

Data written to the S1V3S344 internal flash memory can be read to verify that it has been written correctly. To read out data, send data in the following sequence: Read command Read start address. Data read out is output to the SOS once the read start address has been sent. Data read out is output in sequence from the data at the read start address while NSCSS remains L. The address for data read out is incremented by 1. The Read command is 0x03. The read address is 24 bits long.

Figure 4.5 illustrates the process for erasing, writing 1,024 bytes and then continuously reading 1 byte. Figure 4.6 illustrates a 2-byte read process.

Figure 4.5 S1V3S344 read timing chart


(Rev. 1.00)

4. Flash Access

SCKS

SIS

NSCSS

SOS

NRESET

0 0 0 10 0 0 1

24-bit addressMSB LSB

Date read outLSBMSB

Date read outLSBMSB

Data at address incremented by 1

Figure 4.6 S1V3S344 read timing chart (2 bytes)

4.3 S1V3G340 external SPI flash memory access

There are two situations in which the S1V3G340 accesses external SPI flash memory.

The first is when the S1V3G340 is in Flash Access mode. In this case, the serial communication interface is connected to the SPI master interface inside the S1V3G340, as shown in Figure 4.2, creating a configuration whereby the host and external SPI flash memory are connected directly. This arrangement gives the host free access in accordance with the SPI flash memory specifications.

Create the voice data to be written to the external SPI flash memory using the Epson Speech IC Speech Guide Creation Tool. For information on creating voice data, refer to the Epson Speech IC Speech Guide Creation Tool User Guide.

Voice data must be written starting from address 0x000000 in the external SPI flash memory. Sequential playback is not possible if the data write begins from any other address.

In the second scenario, a sequential playback command is received from the host when the S1V3G340 is in Normal mode. In this case, the S1V3G340 automatically reads the specified voice data from the external SPI flash memory.

Table 4.1 shows the read specifications for S1V3G340 in Normal mode. Figure 4.7 shows the timing chart.

Table 4.1 SPI-FLASH memory specifications

Specifications Details

Read command 0x03

Address length 24 bits

Read data length n bytes read out continuously from specified address


4. Flash Access

SMSCK

SMSO

SMCS

SMSI

0 0 0 10 0 0 1

24-bit addressMSB LSB

Date read outLSBMSB

Date read outLSBMSB

Data at address incremented by 1

Figure 4.7 S1V3G340 read timing chart


(Rev. 1.00)

5. Specifications for Flash Memory Writer Sample Program


5.1 Overview

This section provides specifications for the flash memory writer sample program provided to the client using the S1V3S344. This program is a sample program designed to control access to flash memory in the S1V3S344 operating on the client host system. Given below are the specifications for the APIs contained in the sample program.

* This sample program was created for the host system used for S1V3S344 control evaluations performed by Seiko Epson. We do not guarantee the compatibility of the sample program when used in the client system.

5.2 Obtaining the sample program

You must download the sample program from the Epson Speech & Audio Evaluation Kit Download Site. Please refer to the document enclosed in the S1V3S344 evaluation kit for the Epson Speech & Audio Evaluation Kit Download Site URL.

5.3 Details of files

The sample program is stored in the following directory.

\flash Source files for the flash memory writer sample program are stored.

* When the sample program is incorporated into the client system, some source code must be modified to suit the system used.

5.3.1 main_flashwrite.c

The main_flashwrite.c file describes a series of control programs for performing flash access processing based on control from the host processor.

5.3.2 Message file

The message file defines the REQ message array table.

The message file defines data similar to the data shown in Figure 5.1. It also describes the REQ message data array, including the message header, “0x00, 0xAA.”

unsigned char aucIscResetReq[] = { 0x00, 0xAA, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00,

};

Figure 5.1 Example of message file



5.3.3 ROMImage.h

In the ROMImage.h file, specify the start address for the binary data of the ROM image file (ROMImage_YYMMDD_HHMMSS.bin) and the size of the ROM image (set 512 KB in normal use).

Table 5.1 List of source files

Filename Directory Description

main_flashwrite.c flash Main program for writing data to flash memory

Isc_msgs.c flash REQ message array table definition file for standard-version sample program

Isc_msg.h flash Header file of REQ message array table definition file for standard-version sample program

ROMImage.h flash Designation of ROM image

flash SPI control API function definition (*1) spi_api.c

flash SPI control API function declaration spi_api.h

reg.h flash SPI register map definition (*2)

*1 “spi_api.c” is a control program prepared for the SPI in the host system used by Seiko Epson for S1V3S344 control evaluations. When incorporated into the client system, it must be modified to suit the system used.

*2 “reg.h” describes the map of SPI registers in the host system used by Seiko Epson for S1V3S344 control evaluations. When incorporated into the client system, it must be modified to suit the system used. For the specifications for SPI registers in the host system used by Seiko Epson, refer to “8.1 Example of SPI register specifications.”


(Rev. 1.00)


5.4 Specifications for main programs

The sample program provides main programs for writing data to flash memory. Each main program provides control according to the procedure described below. For specifics of SPI command transmission, refer to S1V3034x Series Message Protocol Specification. For the specifications of SPI commands for accessing flash memory, refer to “4.1 S1V3S344 write processing” and “4.2 S1V3S344 read processing.”

* This sample program does not use interrupt processing. If the host system used by the client requires interrupt processing, you must make the necessary changes based on the interruption specifications of the host system used.

5.4.1 main_flashwrite.c

This is a main program used to write data to flash memory. It initializes the system and writes data to flash memory. The flowchart is shown on the next page.



Read sequence

Write sequence

Erasure sequence

Start

Initializing system

Initializing SPI I/F

CS -> L

Wait time of 120 ms

Transmission/reception of ISC_RESET_REQ/RESP

Transmitting ISC_SPISW_IND

CS -> H

Wait time of 5 s

Acquiring ROM image file size

CS -> L

Transmitting Erase command (0xC7)

CS -> H

Transmitting serial clock (1000000 x SCLK)

Acquiring 1,024 bytes of data

to be written to flash memory

CS -> L

Transmitting Write command (0x02)

CS -> H


Have 1,024 bytes been sent?


CS -> L

Transmitting Read command (0x03)

Reception of serial I/F 1 byte

Is the data correct?

Have 1,024 bytes been

Verification error

ReadSize >= FileSize?

ReadSize = ReadSize + 1,024

No

Yes

CS -> H

Yes

No

Yes

Yes

No

S1V3S344 HW Reset

No

End due to error

End

Figure 5.2 Main program flowchart


(Rev. 1.00)


(1) Initializes the system.

(2) Executes a hardware reset for the S1V3S344.

(3) Initializes the SPI I/F module.

(4) Sets the S1V3S344’s NSCSS (Chip Select) to L.

(5) Guarantees 120-ms wait time for the S1V3S344.

(6) Resets the S1V3S344. (Transmission/reception of ISC_RESET_REQ/RESP)

(7) Sets the S1V3S344 to Flash Access mode. (Transmission of ISC_SPISW_IND)

(8) Sets the S1V3S344’s NSCSS (Chip Select) to H.

(9) Guarantees 5-m wait time for the S1V3S344.

(10) Acquires the ROM image file size.


(12) Erases the contents of the S1V3S344 internal flash memory. (Transmission of 0xC7 by SPI)


(14) Continues sending the serial clock for at least “1000000 x SCKS” times while holding NSCSS in H. (To complete the S1V3S344’s flash memory erasure sequence)

(15) Obtains data to be written to flash memory. (Acquiring 1,024-byte data from the ROM image file.)


(17) Starts writing the data to flash memory. (Transmission of 0x02 by SPI, write address: 24 bits, 1-byte writing)


(19) Guarantees at least “2 x SCKS” wait time for the S1V3S344 while holding NSCSS (Chip Select) in H.

(20) Repeats (16) through (19) for 1,024 bytes.

(21) Guarantees at least “130 x SCKS” wait time for the S1V3S344 while holding NSCSS signals in H. (To complete the S1V3S344’s flash memory write sequence)


(23) Starts reading data from the S1V3S344 internal flash memory. (Transmission of 0x03 by SPI, read address: 24 bits)

(24) Reads out 1,024 bytes while comparing with the data written in (16) through (19). If the data do not match, an error will be returned.


(26) Repeats (15) through (25) a certain number of times until the space allocated for the ROM image file is full.

< End of flash memory write process >



5.5 Specifications for S1V3S344 flash memory access control APIs

Given below are the specifications for the APIs for accessing the S1V3S344’s flash memory.

* Shown below is the control program prepared for the SPI in the host system used by Seiko Epson for S1V3S344 control evaluations. When incorporated into the client system, the contents of the APIs must be modified to suit the system used.

5.5.1 SPI_Initialize

[Syntax]

void SPI_Initialize (void)

[Function]

Initializes the SPI.

[Input argument]

None

[Output argument]

None

[Return value]

None

[Function description]

This function initializes the registers of the SPI. This API function complies with the specifications of the SPI of the host processor used in Seiko Epson’s evaluation system and makes the following settings.

(1) Disables the SPI module.

(2) Sets the input/output pins.

(3) Sets the SPI clock frequency(*2).

(4) Sets the SPI clock mode (polarity and phase).

(5) Sets the SPI to Master mode.

(6) Sets the wait cycle between data transfers.

(7) Sets the bit mask for received data.

(8) Disables interrupts for the SPI module.

(9) Enables the SPI module.

(10) Disables the SD Card SPI access (because SPI I/F is shared).

*1 For specifics, refer to “8.1 Example of SPI register specifications.”

*2 The SPI’s maximum clock frequency for flash memory access is 1.024 MHz.


(Rev. 1.00)


5.5.2 SPI_SendReceiveByte

[Syntax]

unsigned char SPI_SendReceiveByte ( unsigned char ucSendData)

[Function]

Sends and receives 1-byte data.

[Input argument]

ucSendData Sets 1-byte transmission data.

[Output argument]

None

[Return value]

Returns 1-byte received data.


This function simultaneously sends and receives one-byte data to and from the S1V3S344 via the SPI.



5.5.3 SPI_SendByte

[Syntax]

void SPI_SendByte ( unsigned char ucSendData)

[Function]

Sends one-byte data.

[Input argument]

ucSendData Sets one-byte transmission data.

[Output argument]

None

[Return value]

None


This function sends one-byte data to the S1V3S344 via the SPI.


(Rev. 1.00)


5.5.4 SPI_SendMessage

[Syntax]

int SPI_SendMessage ( unsigned char *pucSendMessage, unsigned short *pusReceivedMessageID)

[Function]

Sends messages to the S1V3S344.

[Input argument]

pucSendMessage Specifies the address of the memory area in which the outbound message is stored.

pusReceivedMessageID Specifies the pointer to the variable that stores the message ID of the message received during data transmission.

[Output argument]

None

[Return value]

Returns 0 when the process is completed successfully; otherwise returns -1.


This function sends REQ messages to the S1V3S344.

It refers to the value in the length field of the target REQ message when sending data.

If a message from the S1V3S344 is received during transmission of the REQ message, the ID of that message is stored in pusReceivedMessageID.

* This is a message transmission function for the standard-version sample program.



5.5.5 SPI_ReceiveMessage

[Syntax]

int SPI_ReceiveMessage ( unsigned short *pucReceivedMessageID, )

[Function]

Receives messages from the S1V3S344.

[Input argument]

None

[Output argument]

pucReceivedMessageID Specifies the pointer to the variable that stores the message ID of the received message.

[Return value]

Returns 0 when the process is completed successfully; otherwise returns -1.


This function receives the RESP or IND message issued from the S1V3S344.

It continues receiving data from the S1V3S344 until it detects the message header (0x00, 0xAA). Thereafter, this function obtains the values in the length field and id field in the received message and continues receiving data based on the obtained length field value. The obtained id field value is stored in the output argument pucReceivedMessageID. The function also performs error processing (e.g., ID checks) for the received message.


(Rev. 1.00)


5.5.6 SPI_SetFlashAccessMode

[Syntax]

void SPI_SetFlashAccessMode (void)

[Function]

Sets the S1V3S344 to Flash Access mode.

[Input argument]

None

[Output argument]

None

[Return value]

None


This function sets the S1V3S344 to Flash Access mode(*). Described below is the detailed process flow.

* For specifics, refer to “3. Flash Access Mode Setup.”

(1) Sets NSCSS (Chip Select) to L.

(2) Sends “0x00 0xaa 0x04 0x00 0x00 0xFF” (6 bytes) in that sequence to the serial communication interface.

(3) Sets NSCSS (Chip Select) to H.

(4) Guarantees 5-s wait time to the S1V3S344.

(5) The S1V3S344 enters Flash Access mode.



5.5.7 SPI_EraseFlashData

[Syntax]

void SPI_EraseFlashData (void)

[Function]

Executes the flash memory erasure sequence in the S1V3S344.

[Input argument]

None

[Output argument]

None

[Return value]

None


This function executes the flash memory erasure sequence(*) in the S1V3S344. Described below is the detailed process flow.

* The S1V3S344 must be in Flash Access mode to execute the flash memory erasure sequence. Before calling this function, be sure to invoke the SPI_SetFlashAccessMode function to set the S1V3S344 to Flash Access mode. (For specifics, refer to “3 Flash Access Mode Setup.”)


(2) Sends 0xC7 to the serial communication interface.


(4) Operates the serial clock (sends 0x00 (dummy byte)) for a minimum duration of “1000000 x SCKS” for the serial communication interface to complete the S1V3S344’s flash memory erasure sequence.

(5) Completes the chip erasure process.


(Rev. 1.00)


5.5.8 SPI_WriteFlashData

[Syntax]

void SPI_WriteFlashData (unsigned long ulAddress, unsigned char *pucData )

[Function]

Executes the flash memory write sequence in the S1V3S344.

[Input argument]

ulAddress Flash write start address (24-bit specification)

pucData Pointer to the data to be written to flash memory

[Output argument]

None

[Return value]

None


This function executes the flash memory write sequence(*1) in the S1V3S344. It issues the Write command 1,024 times to write 1,024-byte data to flash memory. Described below is the detailed process flow.


(2) Sends 0x02 to the serial communication interface.

(3) Sends a 24-bit address and data (1 byte) to be written to the serial communication interface.


(5) Operates the serial clock (sends 0x00 (dummy byte)) for a minimum duration of “2 x SCKS”(*2) for the serial communication interface to complete the S1V3S344’s flash memory write sequence.

(6) Completes the 1-byte write process (flash memory write sequence).

(7) Repeats (1) through (6) 1,024 times.

(8) Operates the serial clock (sends 0x00 (dummy byte)) for a minimum duration of “130 x SCKS” for the serial communication interface to complete the S1V3S344’s flash memory write sequence completely.

(9) End

*1 The S1V3S344 must be in Flash Access mode to execute the flash memory write sequence. Before calling this function, be sure to invoke the SPI_SetFlashAccessMode function to set the S1V3S344 to Flash Access mode. (For specifics, refer to “3. Flash Access Mode Setup.”)

*2 The sample program operates at “8 x SCKS.”



5.5.9 SPI_VerifyFlashData

[Syntax]

int SPI_VerifyFlashData (unsigned long ulAddress, unsigned char aucCompData[])

[Function]

Executes the flash memory read sequence in the S1V3S344 and checks whether the read data is correct.

[Input argument]

ulAddress Flash read start address (24-bit specification)

aucCompData Comparison source data array

[Output argument]

None

[Return value]

Returns 0 when the process is completed successfully or returns -5 when a verification error occurs.


This function executes the flash memory read sequence (*1) in the S1V3S344 and checks whether the read data is correct.


(2) Sends 0x03 to the serial communication interface.

(3) Receives 1-byte data from the serial communication interface and checks whether it corresponds to the aucCompData array data. Returns an error and ends the process if a comparison error occurs(*2).

(4) Repeats (3) 1,024 times.


(6) End(*3)

*1 The S1V3S344 must be in Flash Access mode to execute the flash memory read sequence. Before calling this function, be sure to invoke the SPI_SetFlashAccessMode function to set the S1V3S344 to Flash Access mode. (For specifics, refer to “3. Flash Access Mode Setup.”)

*2 If a verification error occurs, enable the H/W Reset of the S1V3S344 and repeat the process from the beginning.

*3 To issue the Read command (0x03) continuously, drive the serial clock for at least “2 x SCKS” to complete the read sequence.


(Rev. 1.00)


5.5.10 GPIO_ControlChipSelect

[Syntax]

void GPIO_ControlChipSelect ( int iValue)

[Function]

Controls NSCSS (Chip Select signal) of the S1V3S344.

[Input argument]

iValue Specifies 0: L or 1: H.

[Output argument]

None

[Return value]

None


This function controls the NSCSS (Chip Select signal) of the S1V3S344. To initiate communications with the S1V3S344 by means of the serial communication interface, you must set NSCSS to L.




(Rev. 1.00)

5.5.11 GPIO_ControlChipReset

[Syntax]

void GPIO_ControlChipReset (void)

[Function]

Executes hardware reset for the S1V3S344.

[Input argument]

None

[Output argument]

None

[Return value]

None


This function executes a hardware reset for the S1V3S344. Specifically, it controls the H/WReset signal (NRESET) of the S1V3S344 and applies a hardware reset. You must invoke this function to initialize the S1V3S344 when initializing the program or when rebooting the program after a verification error.

Revision History

Revision History

Revision details Date

Rev. Page Type Details

02/12/2009 1.00 All pages New Newly established

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Documents

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