First Aid Kit TI_First Aid Kit_2011.pdf · Octal, 144 kHz, Simultaneous Sampling 24-bit Delta Sigma ADC • REF5025 Low Noise, Very Low Drift, Precision Voltage Reference • TLV431A

First Aid KitHardware Issues with FPGA’s?EBV Solutions with Texas Instruments Products

Special Edition

Distribution is today.Tomorrow is EBV!www.ebv.com

First Aid KitHardware Issues with FPGA’s?EBV Solutions with Texas Instruments Products

Special Edition

Based on TI’s Analog products, this ‘First Aid Kit’ from EBV and

TI consists of a trouble-shooting box containing a description

of various problems and the way to solve them, together with

samples and documentation to accelerate time-to-solution

implementation for R&D engineers and technicians.

TI delivers a broad portfolio of data converters, touch screen

controllers, analog front ends, audio converters and CODECs.

Featuring high-performance 12- to 18-bit SAR ADCs, 16- to 24-bit

delta-sigma ADCs, 10- to 16-bit pipeline ADCs, and 8- to 20-bit

DACs, TI has a data converter for all your analog and mixed-

signal applications.

Also, Texas Instruments’power management solutions range

from standard ICs to integrated power solutions, including plug-in

power modules, digital power, battery management and high-

performance MOSFETs. From isolated AC/DC and DC/DC power

supply controllers, and non-isolated voltage regulators, such

as switching DC/DC converters and linear regulators, to PMIC

and LED drivers and display solutions, TI power management

IC solutions can help you complete your design.

This First Aid Kit contains:

ISP #1: ADS1278

ISP #2: REF5025

ISP #3: ADS4149

ISP #4: THA4521

ISP #5: TPS62231

ISP #6: TPS60150

ISP #7: CDCE72010

ISP #8: TLK100

ISP #9: TLV431A

ISP #10: TPS3103K33

ISP #11: TPS23753A

ISP #12: TPS62067

EBV and Texas Instruments are pleased to offer you following

working samples in this ‘First Aid Kit’:

• ADS4149

14-bit 250 MspsLow Power ADC

• THS4521

Very low power rail-to-rail output fully differential amplifi er

• CDCE72010

Ten Output High Performance Clock Synchroniser,

Jitter Cleaner and Clock Distribution

• TLK100

Industrial Ethernet PHY

• TPS3103

Ultra-Low Supply Current/Supply Voltage Supervisory

Circuits

• TPS23753A

IEEE 802.3-2005 PoE Interface and Isolated Converter

Controller with Enhanced ESD Performance

• TPS6206

3 MHz, 2A Step-Down Converter in 2 x 2 SON Package

• ADS1278

Octal, 144 kHz, Simultaneous Sampling 24-bit Delta Sigma

ADC

• REF5025

Low Noise, Very Low Drift, Precision Voltage Reference

• TLV431A

Low-Voltage Adjustable Precision Shunt Regulator

• TPS60150

140 mA, 5 V Charge Pump in 2 x 2 QFN Package

• TPS62231

3 MHz Ultra Small Step-Down Converter in 1 x 1.5 SON Package

Use ESD handling precautions and you can directly test them on

your boards. You will fi nd an extract from the datasheet in the

‘First Aid Kit’. Please contact your local EBV Sales offi ce to get

more samples from this family and to answer all your questions.

For more information on additional product information,

design tools, videos, and much more please visit

www.ebv.com/fi rstaidkit!

PACKAGE INSERT


First Aid KitHardware Issues with FPGA’s? EBV Solutions with Texas Instruments Products

ProDucT: ADS1278

Key Features

• Simultaneously measure four/eight channels

• Up to 144 ksps data rate

• AC performance:

• 70 kHz bandwith

• 111 db SNR (high-resolution mode) – 108 db THD

• DC accuracy:

• 0.8 μV/°C offset drift

• 1.3 ppm/°C gain drift

• Selectable operating modes:

• High-speed: 144 ksps, 106 db SNR

• High-resolution: 52 ksps, 111 db SNR

• Low-power: 52 ksps, 31 mW/ch

• Low-speed: 10 ksps, 7 mW/ch

• Linear phase digital filter

• SPI™ or frame-sync serial interface

• Low sampling aperture error

• Modulator output option (digital filter bypass)

• Analog supply: 5 V

• Digital core: 1.8 V

• I/O supply: 1.8...3.3 V

ISP #1 – ADS1278Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters

(1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs.

ADS1274/ADS1278 Block Diagram

AVDD VREFP VREFN DVDD

Mod 1Mod 2

Mod 8

DigitalFilter 1

DigitalFilter 2

∆∑Modulator

∆∑Modulator2

∑

∑

∑

∑

∆∑Modulator4/8(1)

VREF

R

R

VCOM

+

+

–

–

+

–

+

–

AINP1

VIN4/8

VIN2

VIN1

AINN4/8(1)AINP4/8(1)

AGND

DigitalFilter 4/8(1)

ControlLogic

ModulatorOutput

SPIand

Frame-SyncInterface

DGND

AINN1

AINP2AINN2

IOVDD

DRDY/FSYNC

SCLK

DOUT[4:1]/[8:1](1)

DIN

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN[4:1]/[8:1](1)

CLKDIV

MODE[1:0]

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Special Edition

SAmPlE PAcK

EBV and Texas Instruments are pleased to offer you these working samples; use ESD handling precautions and you can directly test them on your boards. You will find an extract from the datasheet in this First Aid Kit that you have just received. Please contact your local EBV Sales office to get to know more products from this family and to answer all your questions.

Do you want to order more samples? Would you like more information? Please visit us at www.ebv.com/firstaidkit.

ISSuE

Traditionally, industrial delta-sigma ADCs offering good DC precision used digital filters with large passband droop, resulting in limited signal bandwidth mostly suited for only DC measurements. High resolution ADCs for audio applications offer larger useable bandwidths, but the DC precision (offset and drift specifications) is significantly worse (and often unspecified) than their industrial counterparts.

SoluTIon

Based on the single-channel ADS1271, the ADS1274 (quad) and ADS1278 (octal) are 24-bit, delta-sigma (∆∑) analog-to-digital converters (ADCs) with data rates up to 144 k samples of four or eight channels. The devices are offered in identical packages, permitting drop-in expandability.

Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwith and are mostly suited for dc measurements. High resolution ADCs in audio applications offer larger usable bandwiths, but the offset and drift specifications are significantly weaker than respective industrial counterparts. The ADS1274 and the ADS1278 combine these types of converters, allowing high-precision industrial measurement with excellent dc and ac specifications.


ADS1278

DRDY/FSYNC

SCLK

DOUT[8:1]

DIN

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN[8:1]

CLKDIV

MODE[1:0]

Input1

Input2

Input3

Input4

Input5

Input6

Input7

Input8

AGND

VREFP VREFN AVDD DVDD IOVDD

DGND

ΔΣ

ΔΣ

ΔΣ

ΔΣ

ΔΣ

ΔΣ

ΔΣ

ΔΣ

EightDigitalFilters

SPIand

Frame-Sync

Interface

ControlLogic

(1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs. Place the THS4521 drivers close to the ADS1278 inputs.(2) Indicates ceramic capacitors(3) Indicates COG ceramic capacitors(4) Optional. For pin test mode(5) U1: SN74LVC1G04; U2: SN74LVC2G74. These components re-clock the ADS1274/78 data output to interface to the TMS320VC5509(6) If CLK > 32.768 MHz, use the REF5020 and DVDD = 2.1 V

ADS1274 Basic Connection Drawing

THS4521(1)

IN1(+)

IN1(-)

IN4/8(+)

IN4/8(-)

2.2 nF(3)

2.2 nF(3)

AINN1

AINP1 IOVDD

ADS1274/ADS1278 TMS320VCS509

CLK

DRDY/FSYNC

DOUT1SCLK

DOUT2

DOUT3

DOUT4SYNC

PWDN1

PWDN2

PWDN3

PWDN4

CLKDIV

MODE0MODE1

FORMAT2FORMAT1

FORMAT0

BufferedVCOMOutput

100 Ω

1 µF

10 µF(2)

10 µF(2)

0.1 µF(2)

0.1 µF(2)

10 µF

+5 V

+5 V

+1.8 V+

+

+

–

(6)

OPA350

REF5025

DGND

+3.3 V

+3.3 V(High-Speed, Frame-Sync, TDM,and Fixed-Position data selected)

I/O

(5)

(4)

CLKR

DR

DVCC (I/O)

FSR

CVDD(CORE)

+1.6 V

+3.3 V

10 µF(2)

50 Ω

50 Ω

U20 Q

Q>U1

200 MHz

AGNDDINTEST1TEST0

VCOM

VREFN

VREFP

DVDD

AVDD

AINN4/8

AINP4/8



ProDucT: ADS1278

Key Features

• Simultaneously measure four/eight channels

• Up to 144 ksps data rate

• AC performance:

• 70 kHz bandwith

• 111 db SNR (high-resolution mode) – 108 db THD

• DC accuracy:

• 0.8 μV/°C offset drift

• 1.3 ppm/°C gain drift

• Selectable operating modes:

• High-speed: 144 ksps, 106 db SNR

• High-resolution: 52 ksps, 111 db SNR

• Low-power: 52 ksps, 31 mW/ch

• Low-speed: 10 ksps, 7 mW/ch

• Linear phase digital filter

• SPI™ or frame-sync serial interface

• Low sampling aperture error

• Modulator output option (digital filter bypass)

• Analog supply: 5 V

• Digital core: 1.8 V

• I/O supply: 1.8...3.3 V


(1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs.

ADS1274/ADS1278 Block Diagram

AVDD VREFP VREFN DVDD

Mod 1Mod 2

Mod 8

DigitalFilter 1

DigitalFilter 2

∆∑Modulator

∆∑Modulator2

∑

∑

∑

∑

∆∑Modulator4/8(1)

VREF

R

R

VCOM

+

+

–

–

+

–

+

–

AINP1

VIN4/8

VIN2

VIN1

AINN4/8(1)AINP4/8(1)

AGND

DigitalFilter 4/8(1)

ControlLogic

ModulatorOutput

SPIand

Frame-SyncInterface

DGND

AINN1

AINP2AINN2

IOVDD

DRDY/FSYNC

SCLK

DOUT[4:1]/[8:1](1)

DIN

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN[4:1]/[8:1](1)

CLKDIV

MODE[1:0]

VREFP VREFN AVDD DVDD

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN[8:1]

CLKDIV

Control

Logic

SPI

and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC

SCLK

DOUT[8:1]

DIN

Input2

Input1

Input4

Input3

Input6

Input5

Input8

Input7

��

��

��

��

��

��

��

��

PWDN[4:1]

ADS1278

Four

Digital

Filters

AVDD DVDD

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

CLKDIV

Control

Logic

SPI

and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC

SCLK

DOUT[4:1]

DIN

ADS1274

MODE[1:0]MODE[1:0]

Eight

Digital

Filters

VREFP VREFN

Input2

Input1

Input4

Input3

��

��

��

��

ADS1274ADS1278

www.ti.com SBAS367F –JUNE 2007–REVISED FEBRUARY 2011

Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital ConvertersCheck for Samples: ADS1274, ADS1278

1FEATURES DESCRIPTION234• Simultaneously Measure Four/Eight Channels Based on the single-channel ADS1271, the ADS1274

(quad) and ADS1278 (octal) are 24-bit, delta-sigma• Up to 144kSPS Data Rate(ΔΣ) analog-to-digital converters (ADCs) with data• AC Performance:rates up to 144k samples per second (SPS), allowing70kHz Bandwidth simultaneous sampling of four or eight channels. The111dB SNR (High-Resolution Mode) devices are offered in identical packages, permitting

–108dB THD drop-in expandability.• DC Accuracy: Traditionally, industrial delta-sigma ADCs offering0.8μV/°C Offset Drift good drift performance use digital filters with large1.3ppm/°C Gain Drift passband droop. As a result, they have limited signal• Selectable Operating Modes: bandwidth and are mostly suited for dc

High-Speed: 144kSPS, 106dB SNR measurements. High-resolution ADCs in audioapplications offer larger usable bandwidths, but theHigh-Resolution: 52kSPS, 111dB SNRoffset and drift specifications are significantly weakerLow-Power: 52kSPS, 31mW/chthan respective industrial counterparts. The ADS1274Low-Speed: 10kSPS, 7mW/chand ADS1278 combine these types of converters,• Linear Phase Digital Filter allowing high-precision industrial measurement with

• SPI™ or Frame-Sync Serial Interface excellent dc and ac specifications.• Low Sampling Aperture Error The high-order, chopper-stabilized modulator• Modulator Output Option (digital filter bypass) achieves very low drift with low in-band noise. The

onboard decimation filter suppresses modulator and• Analog Supply: 5Vsignal out-of-band noise. These ADCs provide a• Digital Core: 1.8V usable signal bandwidth up to 90% of the Nyquist

• I/O Supply: 1.8V to 3.3V rate with less than 0.005dB of ripple.Four operating modes allow for optimization of speed,APPLICATIONS resolution, and power. All operations are controlled

• Vibration/Modal Analysis directly by pins; there are no registers to program.• Multi-Channel Data Acquisition The devices are fully specified over the extended

industrial range (–40°C to +105°C) and are available• Acoustics/Dynamic Strain Gaugesin an HTQFP-64 PowerPAD™ package.• Pressure Sensors

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments, Inc.3SPI is a trademark of Motorola, Inc.4All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. © 2007–2011, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ADS1274ADS1278

SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of thisdocument, or visit the device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGSOver operating free-air temperature range unless otherwise noted(1)

ADS1274, ADS1278 UNITAVDD to AGND –0.3 to +6.0 VDVDD, IOVDD to DGND –0.3 to +3.6 VAGND to DGND –0.3 to +0.3 V

Momentary 100 mAInput current

Continuous 10 mAAnalog input to AGND –0.3 to AVDD + 0.3 VDigital input or output to DGND –0.3 to IOVDD + 0.3 VMaximum junction temperature +150 °C

ADS1274 –40 to +125 °COperating temperature range

ADS1278 –40 to +105 °CStorage temperature range –60 to +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.

2 Submit Documentation Feedback © 2007–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS1274 ADS1278



ProDucT: rEF5025

Key Features

• Low temperature drift

• High-grade: 3 ppm/°C (max.)

• Standard-grade: 8 ppm/°C (max.)

• High accuracy:

• High-grade: 0.05% (max.)

• Standard-grade: 0.1% (max.)

• Low noise: 3 μVPP/V

• Excellent long-term stability:

• 5 ppm/1000 hr/typ. (after 1000 hours)

• High output current: ±10 mA

• Temperature range: -40...+125 °C

ISP #2 – REF5025Low Noise, Very Low Drift, Precision Voltage Reference

R1R2

αT(10 μAat +25 °C

αT

R560 kΩ

R4

10 kΩ R3

1 kΩ

TRIM/NR

TEMP

GND

1.2 V

VIN

VOUT

REF50xx

+

+

–

–

REF50xx Simplified Block Diagram

DNC(1)

VINTEMP

GND

1

2

3

4

DNC(1)

VOUT

NC(2)REF50xx

TRIM/NR

8

6

7

5

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ISSuE

An analog to digital design can have tight requirements on the voltage reference. Besides stability over a temp. range and high precision, a reference should not add additional noise to the design. High accuracy analog-to-digital data capture designs have a need for stable, accurate and ‘noise-free’ references.

SoluTIon

The REF50xx is a family of low-noise, low-drift, very high precision voltage references. These references are capable of both sinking and sourcing, and are very robust with regards to line and load changes.

Excellent temperature drift (3 ppm/°C) and high accuracy (0.05%) are achieved using proprietary design techniques. These features, combined with very low noise, make the REF50xx family ideal for use in high-precision data acquisition systems.

Each reference voltage is available in both standard- and high-grade versions. They are offered in MSOP-8 and SO-8 packages, and are specified from -40...+125 °C.


+VSUPPLY

GND TRIM/NRTEMP VOUT

VIN NCDNC DNC

REF50xx

C11 µF

Noise Reduction Using the TRIM/NR Pin

Input Signal0...4 V

+5 V

R150 Ω

C11.2 nF

+5 VCBYPASS1 µF

GND

VIN VOUT

REF5040

C222 µF

-IN

+INADS8326

REF GND

VDD

+5 V

SCLKSDOCS

OPA365+

–

Basic Data Acquisition System

Special Edition

SAmPlE PAcK




ProDucT: rEF5025

Key Features

• Low temperature drift

• High-grade: 3 ppm/°C (max.)

• Standard-grade: 8 ppm/°C (max.)

• High accuracy:

• High-grade: 0.05% (max.)

• Standard-grade: 0.1% (max.)

• Low noise: 3 μVPP/V

• Excellent long-term stability:

• 5 ppm/1000 hr/typ. (after 1000 hours)

• High output current: ±10 mA

• Temperature range: -40...+125 °C


R1R2

αT(10 μAat +25 °C

αT

R560 kΩ

R4

10 kΩ R3

1 kΩ

TRIM/NR

TEMP

GND

1.2 V

VIN

VOUT

REF50xx

+

+

–

–

REF50xx Simplified Block Diagram

DNC(1)

VINTEMP

GND

1

2

3

4

DNC(1)

VOUT

NC(2)REF50xx

TRIM/NR

8

6

7

5

ADS8326

REF5040

REF

VOUT

GND

+IN

�IN

VIN+5V

OPA365

Input

Signal

0V to 4V

+5V +5V

VDD

GND

CBYPASS1 F�

R150�

C11.2nF

C222 F�

1

2

3

4

8

7

6

5

DNC(1)

NC(2)

TRIM/NR

DNC(1)

VIN

TEMP

GND

VOUT

REF50xx

SO-8, MSOP-8

(1) DNC = Do not connect.

(2) NC = No internal connection.

NOTES:

REF5010, REF5020REF5025, REF5030

REF5040, REF5045, REF5050www.ti.com SBOS410E –JUNE 2007–REVISED JUNE 2010

Low-Noise, Very Low Drift, PrecisionVOLTAGE REFERENCE

Check for Samples: REF5010, REF5020, REF5025, REF5030, REF5040, REF5045, REF5050

1FEATURES DESCRIPTION2• LOW TEMPERATURE DRIFT: The REF50xx is a family of low-noise, low-drift, very

high precision voltage references. These references– High-Grade: 3ppm/°C (max)are capable of both sinking and sourcing, and are– Standard-Grade: 8ppm/°C (max)very robust with regard to line and load changes.

• HIGH ACCURACY:Excellent temperature drift (3ppm/°C) and high– High-Grade: 0.05% (max) accuracy (0.05%) are achieved using proprietary

– Standard-Grade: 0.1% (max) design techniques. These features, combined withvery low noise, make the REF50xx family ideal for• LOW NOISE: 3mVPP/Vuse in high-precision data acquisition systems.• EXCELLENT LONG-TERM STABILITY:Each reference voltage is available in both standard-– 5ppm/1000hr (typ) after 1000 hoursand high-grade versions. They are offered in MSOP-8• HIGH OUTPUT CURRENT: ±10mA and SO-8 packages, and are specified from –40°C to

• TEMPERATURE RANGE: –40°C to +125°C +125°C.

APPLICATIONS REF50xx Family• 16-BIT DATA ACQUISITION SYSTEMS MODEL OUTPUT VOLTAGE• ATE EQUIPMENT REF5020 2.048V• INDUSTRIAL PROCESS CONTROL REF5025 2.5V

REF5030 3.0V• MEDICAL INSTRUMENTATIONREF5040 4.096V• OPTICAL CONTROL SYSTEMSREF5045 4.5V• PRECISION INSTRUMENTATIONREF5050 5.0VREF5010 10.0V

1


2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2007–2010, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

REF5010, REF5020REF5025, REF5030REF5040, REF5045, REF5050SBOS410E –JUNE 2007–REVISED JUNE 2010 www.ti.com



PACKAGE/ORDERING INFORMATION(1)PRODUCT OUTPUT VOLTAGE PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING

STANDARD GRADE (8ppm, 0.1%)

SO-8 D REF5020REF5020A 2.048V

MSOP-8 DGK R50A

SO-8 D REF5025REF5025A 2.5V

MSOP-8 DGK R50B


MSOP-8 DGK R50C

SO-8 D REF5040REF5040A 4.096V

MSOP-8 DGK R50D


MSOP-8 DGK R50E


MSOP-8 DGK R50F

SO-8 D REF5010REF5010A 10.0V

MSOP-8 DGK R50G

HIGH GRADE (3ppm, 0.05%)

SO-8 D REF5020REF5020I 2.048V

MSOP-8 DGK R50A

SO-8 D REF5025REF5025I 2.5V

MSOP-8 DGK R50B


MSOP-8 DGK R50C

SO-8 D REF5040REF5040I 4.096V

MSOP-8 DGK R50D


MSOP-8 DGK R50E


MSOP-8 DGK R50F

SO-8 D REF5010REF5010I 10.0V

MSOP-8 DGK R50G

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see thedevice product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)PARAMETER REF50xx UNIT

Input Voltage +18 V

Output Short-Circuit 30 mA

Operating Temperature Range –55 to +125 °C

Storage Temperature Range –65 to +150 °C

Junction Temperature (TJ max) +150 °C

Human Body Model (HBM) 3000 VESD Rating

Charged Device Model (CDM) 1000 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.

2 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated

Product Folder Link(s): REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050



ProDucT: ADS4149

Key Features

• Maximum sample rate: 250 Msps

• Ultra low-power with 1.8 V single supply:

• 201 mW total power at 160 Msps


• High dynamic performance:

• SNR: 80.6 dBFS at 170 MHz

• SFDR: 84 dBc at 170 MHz

• Dynamic power scaling with sample rate

• Output interface:

• Double Data Rate (DDR) LVDS with programmable swing and strength

• Standard swing: 350 mV

• Low swing: 200 mV

• Default strength: 100 Ω termination

• 2x strength: 50 Ω termination

• 1.8 V parallel CMOS interface also supported

• Programmable gain up to 6 db for SNR/SFDR trade-off

• DC offset correction

• Supports low input clock amplitude down to 200 mVPP• Package: QFN-48 (7 x 7 mm2)

ISP #3 – ADS414914-Bit 250 Msps Low Power ADC

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Would you like more information? Please visit us at www.ebv.com/firstaidkit.

ISSuE

Power consumption has an impact on your overall system design and performance. For AD Converters in particular, the power consumption should be as low as possible to reduce for example temp. drift and improve accuracy. If your AD converter input signal has a DC offset your ADC needs to be capable of handling such a signal or you will need to address such a case by the system design. If the performance

of the ADC can be fine tuned in the system for example by improving the SFDR performance it would have a direct effect on your design.

SoluTIon

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital con-verters (ADCs) with sampling rates up to 250 Msps. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8 V supply. The devices are well-suited for multi-carrier, wide bandwith communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.


AVDD AGND

CLOCKGEN

CommonDigital Functions

ControlInterface

Reference

SamplingCircuit

12-BitADC

Low-Latency Mode(Default After Reset)

DDRSerializer

CLKP

CLKM

INP

INM

VCM

ADS4129

DRVDD DRGNDDDR LVDSInterface

CLKOUTP

CLKOUTM

D0_D1_P

D0_D1_M

D2_D3_P

D2_D3_M

D4_D5_P

D4_D5_M

D6_D7_P

D6_D7_M

D8_D9_P

D8_D9_M

D10_D11_P

D10_D11_M

OVR_SDOUT

OE

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Special Edition

EBV & TI

have alloca

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‘First Aid K

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ProDucT: ADS4149

Key Features

• Maximum sample rate: 250 Msps

• Ultra low-power with 1.8 V single supply:



• High dynamic performance:

• SNR: 80.6 dBFS at 170 MHz

• SFDR: 84 dBc at 170 MHz

• Dynamic power scaling with sample rate

• Output interface:

• Double Data Rate (DDR) LVDS with programmable swing and strength

• Standard swing: 350 mV

• Low swing: 200 mV

• Default strength: 100 Ω termination

• 2x strength: 50 Ω termination

• 1.8 V parallel CMOS interface also supported

• Programmable gain up to 6 db for SNR/SFDR trade-off

• DC offset correction

• Supports low input clock amplitude down to 200 mVPP• Package: QFN-48 (7 x 7 mm2)


ADS4126, ADS4129ADS4146, ADS4149

www.ti.com SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011

12-/14-Bit, 160/250MSPS, Ultralow-Power ADCCheck for Samples: ADS4126, ADS4129, ADS4146, ADS4149

1FEATURES DESCRIPTION23• Maximum Sample Rate: 250MSPS The ADS412x/4x are a family of 12-bit/14-bit

analog-to-digital converters (ADCs) with sampling• Ultralow Power with 1.8V Single Supply:rates up to 250MSPS. These devices use innovative– 201mW Total Power at 160MSPSdesign techniques to achieve high dynamic

– 265mW Total Power at 250MSPS performance, while consuming extremely low power• High Dynamic Performance: at 1.8V supply. The devices are well-suited for

multi-carrier, wide bandwidth communications– SNR: 70.6dBFS at 170MHzapplications.– SFDR: 84dBc at 170MHzThe ADS412x/4x have fine gain options that can be• Dynamic Power Scaling with Sample Rateused to improve SFDR performance at lower

• Output Interface: full-scale input ranges, especially at high input– Double Data Rate (DDR) LVDS with frequencies. They include a dc offset correction loop

that can be used to cancel the ADC offset. At lowerProgrammable Swing and Strengthsampling rates, the ADC automatically operates at– Standard Swing: 350mV scaled down power with no loss in performance.

– Low Swing: 200mVThe ADS412x/4x are available in a compact QFN-48– Default Strength: 100Ω Termination package and are specified over the industrial

– 2x Strength: 50Ω Termination temperature range (–40°C to +85°C)– 1.8V Parallel CMOS Interface Also

Supported• Programmable Gain up to 6dB for SNR/SFDR

Trade-Off• DC Offset Correction• Supports Low Input Clock Amplitude Down To

200mVPP• Package: QFN-48 (7mm × 7mm)

ADS412x/ADS414x Family ComparisonSAMPLING RATE WITH ANALOG INPUT BUFFERS

FAMILY 65MSPS 125MSPS 160MSPS 250MSPS 200MSPS 250MSPSADS412x ADS4122 ADS4125 ADS4126 ADS4129 — ADS41B2912-bit familyADS414x ADS4142 ADS4145 ADS4146 ADS4149 — ADS41B4914-bit family9-bit — — — — — ADS58B1911-bit — — — — ADS58B18 —

1


2PowerPAD is a trademark of Texas Instruments Incorporated.3All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ADS4126, ADS4129ADS4146, ADS4149

SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011 www.ti.com



ORDERING INFORMATION(1)SPECIFIED

PACKAGE- PACKAGE TEMPERATURE LEAD/BALL PACKAGE ORDERING TRANSPORT MEDIA,PRODUCT LEAD DESIGNATOR RANGE ECO PLAN(2) FINISH MARKING NUMBER QUANTITY

ADS4126IRGZR Tape and reel, 2500GREEN (RoHS, noADS4126 QFN-48 RGZ –40°C to +85°C Cu/NiPdAu AZ4126Sb/Br) ADS4126IRGZT Tape and reel, 250




(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit thedevice product folder at www.ti.com.

(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) andfree of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for moreinformation.

The ADS412x/4x family is pin-compatible with the previous generation ADS6149 family; this architecture enableseasy migration. However, there are some important differences between the generations, summarized in Table 1.

Table 1. MIGRATING FROM THE ADS6149 FAMILYADS6149 FAMILY ADS4149 FAMILY

PINS

Pin 21 is NC (not connected) Pin 21 is NC (not connected)

Pin 23 is MODE Pin 23 is RESERVED in the ADS4149 family. It is reserved as a digital control pin for an (as yet) undefined function in thenext-generation ADC series.

SUPPLY

AVDD is 3.3V AVDD is 1.8V

DRVDD is 1.8V No change

INPUT COMMON-MODE VOLTAGE

VCM is 1.5V VCM is 0.95V

SERIAL INTERFACE

Protocol: 8-bit register address and 8-bit register data No change in protocol

New serial register map

EXTERNAL REFERENCE MODE

Supported Not supported

ADS61B49 FAMILY ADS41B29/B49/ADS58B18 FAMILY

PINS

Pin 21 is NC (not connected) Pin 21 is 3.3V AVDD_BUF (supply for the analog input buffers)

Pin 23 is a digital control pin for the RESERVED function.Pin 23 is MODE Pin 23 functions as SNR Boost enable (B18 only).

SUPPLY

AVDD is 3.3V AVDD is 1.8V, AVDD_BUF is 3.3V

DRVDD is 1.8V No change

INPUT COMMON-MODE VOLTAGE

VCM is 1.5V VCM is 1.7V

SERIAL INTERFACE

No change in protocolProtocol: 8-bit register address and 8-bit register data New serial register map

EXTERNAL REFERENCE MODE

Supported Not supported


Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149



ProDucT: THS4521

Key Features

• Fully Differential Architecture

• Bandwidth: 145 MHz

• Slew Rate: 490 V/μs

• HD2: –133 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)


• Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz)

• THD+N: –112dBc (0.00025%) at 1 kHz (22 kHz BW, G = 1, 5 VPP)

• Open-Loop Gain: 119 dB

• NRI - Negative Rail Input

• RRO - Rail-to-Rail Output

• Output Common-Mode Control (with Low Offset and Drift)

• Power Supply:

• Voltage: +2.5 V (±1.25 V) to +5.5 V (±2.75 V)

• Current: 1.14 mA/ch

• Power-Down Capability: 20 μA (typ) ISP #4 – THS4521Very Low Power Rail-to-Rail Output

Fully Differential Amplifier

VIN-

- +

1

2

3

4

8

7

6

5

VOCM

VS+

VOUT+

VIN+

PD

VS-

VOUT-

THS4521 SOIC-8, MSOP-8 (D, DGK Packages)(Top View)

All

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ISSuE

Driving the input of an AD converter can be a challenge. Besides the fact that the topology of an ADC defines your input stage the power supply and ground plane design need to be considered. The dynamic input range of the incoming signal can be negative and your operational amplifier should be able to handle the signal up to the negative rail. Overall the power consumption combined with

a dense design can influence the overall system performance. Last but not least the DC coupling has to be considered.

SoluTIon

The THS4521, THS4522, and THS4524 family of devices are very low-power, fully differential Op Amps with rail-to-rail output and an input common-mode range that includes the negative rail. These amplifiers are designed for low-power data acquisition systems and high-density applications where power dissipation is a critical parameter, and provide exceptional performance in audio applications. The family includes single (THS4521), dual (THS4522), and quad (THS4524) versions. These fully differential op amps feature accurate output common-mode control that allows for dc-coupling when driving analog-to-digital converters (ADCs). This control, coupled with an input common-mode range below the negative rail as well as rail-to-rail output, allows for easy interfacing between single-ended, ground-referenced signal sources.

ISP #4 – THS4521Very Low Power Rail-to-Rail Output


1 kΩ

49.9 kΩ

49.9 kΩ

1 kΩ

1 kΩ

1 kΩ

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2.2 nF

1.5 nF

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-60

-80

-100

-120

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Tone (Hz) Signal (dBFS) Snr (dBc) THD (dBc) SInAD (dBc) SFDr (dBc)

1k -0.50 109.1 -107.9 105.5 113.7

THS4521 and ADS1278 Combined Performance

Special Edition

SAmPlE PAck




ProDucT: THS4521

Key Features

• Fully Differential Architecture

• Bandwidth: 145 MHz

• Slew Rate: 490 V/μs



• Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz)

• THD+N: –112dBc (0.00025%) at 1 kHz (22 kHz BW, G = 1, 5 VPP)

• Open-Loop Gain: 119 dB

• NRI - Negative Rail Input

• RRO - Rail-to-Rail Output

• Output Common-Mode Control (with Low Offset and Drift)

• Power Supply:

• Voltage: +2.5 V (±1.25 V) to +5.5 V (±2.75 V)

• Current: 1.14 mA/ch

• Power-Down Capability: 20 μA (typ) ISP #4 – THS4521Very Low Power Rail-to-Rail Output


VIN-

- +

1

2

3

4

8

7

6

5

VOCM

VS+

VOUT+

VIN+

PD

VS-

VOUT-

THS4521 SOIC-8, MSOP-8 (D, DGK Packages)(Top View)

THS4522

THS4521

THS4524

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THS4521THS4522THS4524

www.ti.com SBOS458E –DECEMBER 2008–REVISED DECEMBER 2010

VERY LOW POWER, NEGATIVE RAIL INPUT, RAIL-TO-RAIL OUTPUT,FULLY DIFFERENTIAL AMPLIFIERCheck for Samples: THS4521, THS4522, THS4524

1FEATURES APPLICATIONS• Low-Power SAR and ΔΣ ADC Drivers23• Fully Differential Architecture• Low-Power Differential Driver• Bandwidth: 145 MHz• Low-Power Differential Signal Conditioning• Slew Rate: 490 V/ms• Low-Power, High-Performance Differential• HD2: –133 dBc at 10 kHz (1 VRMS, RL = 1 kΩ) Audio Amplifier

• HD3: –140 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)• Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz) DESCRIPTION• THD+N: –112dBc (0.00025%) at 1 kHz (22-kHz The THS4521, THS4522, and THS4524 family of

BW, G = 1, 5 VPP) devices are very low-power, fully differential op amps• Open-Loop Gain: 119 dB with rail-to-rail output and an input common-mode

range that includes the negative rail. These amplifiers• NRI—Negative Rail Inputare designed for low-power data acquisition systems• RRO—Rail-to-Rail Output and high-density applications where power

• Output Common-Mode Control (with Low dissipation is a critical parameter, and provideOffset and Drift) exceptional performance in audio applications.

• Power Supply: The family includes single (THS4521), dual(THS4522), and quad (THS4524) versions.– Voltage: +2.5 V (±1.25 V) to +5.5 V (±2.75 V)

– Current: 1.14 mA/ch These fully differential op amps feature accurateoutput common-mode control that allows for• Power-Down Capability: 20 mA (typ)dc-coupling when driving analog-to-digital converters(ADCs). This control, coupled with an inputcommon-mode range below the negative rail as wellas rail-to-rail output, allows for easy interfacingbetween single-ended, ground-referenced signalsources. Additionally, these devices are ideally suitedfor driving both successive-approximation register(SAR) and delta-sigma (ΔΣ) ADCs using only a single+2.5V to +5V and ground power supply.

The THS4521, THS4522, and THS4524 family of fullydifferential op amps is characterized for operationover the full industrial temperature range from –40°Cto +85°C.

RELATEDPRODUCTS

THD(dBc)

BW at 100 VN RAIL-DEVICE (MHz) IQ (mA) kHz (nV/√Hz) TO-RAILTHS4520 570 15.3 –114 2 OutTHS4121 100 16 –79 5.4 In/OutTHS4130 150 16 –107 1.3 No

1


2I2S is a trademark of NXP Semiconductor.3All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

THS4521THS4522THS4524SBOS458E –DECEMBER 2008–REVISED DECEMBER 2010 www.ti.com



PACKAGE/ORDERING INFORMATION(1)SPECIFIED

PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA,PRODUCT LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY

THS4521ID Rails, 75SOIC-8 D TH4521

THS4521IDR Tape and reel, 2500THS4521 –40°C to +85°C

THS4521IDGKT Tape and reel, 250MSOP-8 DGK 4521

THS4521IDGKR Tape and reel, 2500

THS4522IPW Rails, 90THS4522 TSSOP-16 PW –40°C to +85°C THS4522

THS4522IPWR Tape and reel, 2000

THS4524IDBT Rails, 50THS4524 TSSOP-38 DBT –40°C to +85°C THS4524

THS4524IDBTR Tape and reel, 2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see therelevant product folders at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)Over operating free-air temperature range (unless otherwise noted).

PARAMETER THS4521, THS4522. THS4524 UNIT

Supply Voltage, VS– to VS+ 5.5 V

Input/Output Voltage, VI (VIN±, VOUT±, VOCM pins) (VS–) – 0.7 to (VS+) + 0.7V V

Differential Input Voltage, VID 1 V

Output Current, IO 100 mA

Input Current, II (VIN±, VOCM pins) 10 mA

Continuous Power Dissipation See Thermal Characteristic Specifications

Maximum Junction Temperature, TJ +150 °C

Maximum Junction Temperature, TJ (continuous operation, long-term reliability) +125 °C

Operating Free-air Temperature Range, TA –40 to +85 °C

Storage Temperature Range, TSTG –65 to +150 °C

Human Body Model (HBM) 1300 VESD Charge Device Model (CDM) 1000 VRating:

Machine Model (MM) 50 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.


Product Folder Link(s): THS4521 THS4522 THS4524



PRODUCT: TPS6223x

Key Features

• 2 MHz/3 MHz switch frequency

• Up to 94% efficiency

• Output peak current

• Excellent AC and transient load

• High PSRR (up to 90 dB)

• Small external output filter components 1 µH/4.7 µF

• VIN range from 2.05...6 V

• Optimised power save mode for low output ripple voltage

• Forced PWM mode operation

• Typ. 22 µA quiescent current

• 100% duty cycle for lowest drop-out

• Small 1 × 1.5 × 0.6 mm3 SON package

• 12 mm2 minimum solution size

• Supports 0.6 mm maximum solution height

• Soft start with typ. 100 µs start-up time

MODE

SW

1

2

3 4

6

5

VIN

FB

EN

GND

Dry Package (Top View)

ISP #5 – TPS622313 MHz Ultra Small Step-Down Converter

GND VOUT

Total areais less than 12 mm2

VIN

L1

C2

C1

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ISSUE

The overall design is done, PCB layout ready, but a last minute specification change requires adding another power rail – but there is hardly any space left on the PCB. In addition, overall power budget has only very little margin left, since the selected battery cannot be replaced with a larger one. Key parameters in choosing the adequate component are: Overall solution foot print (active and passive components) determined by switching frequency, since inductor size (which dominates solution size) reduces for higher switching frequencies (for a given load current). Highest efficiency over complete load scenarios, e.g. also during light load operation.

SOlUTIOn

Highest possible switching frequency results in smallest inductor size while maintaining high efficiency. Automatic transition into PFM mode during light load operation leads to improved system efficiency over all applications. Low quiescent current will additionally prolong battery life.


BandgapVREF

0.70 VUndervoltage

LockoutCurrent

Limit Comparator

LimitHigh Side

PMOS

VIN

SW

GND

NMOS

Gate DriverAnti

Shoot-Through

ControlLogic

Softstart

VIN

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VREF

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MODE

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Min. ON Time

Min. OFF Time

ErrorComparator

IntegratedFeed BackNetwork

EN

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MODE

TPS62230L

1/2.2 μHVOUT2.5 V

COUT4.7 μF

CIN2.2 μF

VIN2.7...6 V

VINENMODE

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GND

TPS62231L

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COUT4.7 μF

CIN2.2 μF

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GND

TPS62232 L1/2.2 μHVOUT1.2 V

COUT4.7 μF

CIN2.2 μF

VIN2.05...6 V

VINENMODE

SWFB

GND

TPS62230 2.5 V Output



Special Edition

SAmPlE PACK




PRODUCT: TPS6223x

Key Features

• 2 MHz/3 MHz switch frequency

• Up to 94% efficiency

• Output peak current

• Excellent AC and transient load

• High PSRR (up to 90 dB)

• Small external output filter components 1 µH/4.7 µF

• VIN range from 2.05...6 V

• Optimised power save mode for low output ripple voltage

• Forced PWM mode operation

• Typ. 22 µA quiescent current

• 100% duty cycle for lowest drop-out

• Small 1 × 1.5 × 0.6 mm3 SON package

• 12 mm2 minimum solution size

• Supports 0.6 mm maximum solution height

• Soft start with typ. 100 µs start-up time

MODE

SW

1

2

3 4

6

5

VIN

FB

EN

GND

Dry Package (Top View)


GND VOUT

Total areais less than 12 mm2

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1

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TPS62230, TPS62231, TPS62232, TPS62233, TPS62234, TPS62235, TPS62236TPS62237, TPS62238, TPS62239, TPS622310, TPS622311, TPS622312

TPS622313, TPS622314, TPS622315, TPS622316, TPS622317, TPS622318www.ti.com SLVS941E –APRIL 2009–REVISED DECEMBER 2010

2 MHz / 3 MHz Ultra Small Step Down Converter in 1x1.5 SON Package1FEATURES

DESCRIPTION• 2 MHz / 3 MHz Switch Frequency• Up to 94% Efficiency The TPS6223X device family is a high frequency

synchronous step down DC-DC converter optimized• Output Peak Current up to 500mAfor battery powered portable applications. It supports• Excellent AC and Transient Load Regulation up to 500mA output current and allows the use of tiny

• High PSRR (up to 90dB) and low cost chip inductors and capacitors.• Small External Output Filter Components 1mH/ With a wide input voltage range of 2.05V to 6V the

4.7mF device supports applications powered by Li-Ionbatteries with extended voltage range. The minimum• VIN range from 2.05V to 6Vinput voltage of 2.05V allows as well the operation• Optimized Power Save Mode For Low Outputfrom Li-primary or two alkaline batteries. DifferentRipple Voltage fixed output voltage versions are available from 1.0V

• Forced PWM Mode Operation to 3.3V.• Typ. 22 mA Quiescent Current The TPS6223X series features switch frequency up• 100% Duty Cycle for Lowest Dropout to 3.8MHz. At medium to heavy loads, the converter

operates in PWM mode and automatically enters• Small 1 × 1.5 × 0.6mm3 SON PackagePower Save Mode operation at light load currents to• 12 mm2 Minimum Solution Size maintain high efficiency over the entire load current

• Supports 0.6 mm Maximum Solution Height range.• Soft Start with typ. 100ms Start Up Time Because of its excellent PSRR and AC load

regulation performance, the device is also suitable toAPPLICATIONS replace linear regulators to obtain better power• LDO Replacement conversion efficiency.• Portable Audio, Portable Media The Power Save Mode in TPS6223X reduces the• Cell Phones quiescent current consumption down to 22mA during

light load operation. It is optimized to achieve very• Low Power Wirelesslow output voltage ripple even with small external• Low Power DSP Core Supplycomponent and features excellent ac load regulation.• Digital CamerasFor very noise sensitive applications, the device canbe forced to PWM Mode operation over the entireload range by pulling the MODE pin high. In theshutdown mode, the current consumption is reducedto less than 1mA. The TPS6223X is available in a 1 ×1.5mm2 6 pin SON package.

1



TPS62230, TPS62231, TPS62232, TPS62233, TPS62234, TPS62235, TPS62236TPS62237, TPS62238, TPS62239, TPS622310, TPS622311, TPS622312TPS622313, TPS622314, TPS622315, TPS622316, TPS622317, TPS622318SLVS941E –APRIL 2009–REVISED DECEMBER 2010 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)PACKAGE PACKAGEFREQUENCYTA PART NUMBER(2) OUTPUT VOLTAGE ORDERING[MHz] DESIGNATOR MARKING

TPS62230 2.5 V 3 DRY TPS62230DRY GVTPS62231 1.8 V 3 DRY TPS62231DRY GWTPS62232 1.2 V 3 DRY TPS62232DRY GXTPS62239 1.0 V 3 DRY TPS62239DRY OPTPS622311 1.1V 2 DRY TPS622311DRY PATPS622315 1.15V 2 DRY TPS622315DRY RITPS62235 1.2V 2 DRY TPS62235DRY OQTPS622318 1.25V 3 DRY TPS622318DRY STTPS622313 1.3 V 3 DRY TPS622313DRY QF

–40°C to 85°C TPS622314 1.5 V 3 DRY TPS622314DRY QGTPS62236 1.85V 2 DRY TPS62236DRY ORTPS622312 2.0 V 3 DRY TPS622312DRY QETPS62234 2.1 V 3 DRY TPS62234DRY OHTPS62238 2.25 V 3 DRY TPS62238DRY ONTPS622310 2.3 V 3 DRY TPS622310DRY OTTPS622316 2.7 V 3 DRY TPS622316DRY RJTPS622317 2.9 V 3 DRY TPS622317DRY RKTPS62233 3.0 V 3 DRY TPS62233DRY OGTPS62237 3.3V 2 DRY TPS62237DRY OS

(1) For detailed ordering information see the PACKAGE OPTION ADDENDUM at the end of this data sheet.(2) The DRY package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel.

ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted) (1)

VALUE UNITVoltage at VIN and SW Pin(2) –0.3 to 7 V

VI Voltage at EN, MODE Pin(2) –0.3 to VIN +0.3, ≤7 VVoltage at FB Pin (2) –0.3 to 3.6 VPeak output current internally limited A

HBM Human body model 2kV

ESD rating(3) CDM Charge device model 1Machine model 200 V

Power dissipation Internally limitedTJ Maximum operating junction temperature –40 to 125 °CTstg Storage temperature range –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF

capacitor discharged directly into each pin.




PRODUCT: TPS60150

Key Features

• 2.7...5.5 V input voltage range

• Fixed output voltage of 5.0 V

• X2 charge pump

• 1.5 MHz switching frequency

• Maximum output current : 140 mA

• 2 x 2 QFN with 0.8 mm height

• Typical 90 μA quiescent current at no load condition (skip mode)

• Hardware en/disable function

• Built-in soft start

• Built-in under voltage lock-out protection

• Thermal and over-current protection

ISP #6 – TPS60150Charge Pump for Battery-Powered USB OTG Applications

VIN

VOUT

VREF

CP+

GND

CP-

Φ1

Φ2

Φ2

Φ1

CF

ENA

TSDUVLO

Regulation

Current LimitSoft Start

Control

OSC1.5 MHz

Bias circuit

Enable IC

TPS60150

2

4

3

ErrorAmp+-

++- -

Skip Comp

R1

R2

1

5

6

Functional Block Diagram

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ISSUE

When implementing USB ´On the Go´ (OTG) support for battery-powered portable devices, a designer can select either a boost converter or a charge pump topology. USB OTG requires a 5 V rail and up to 140 mA of current. Key parameters choosing the adequate component are:

• Cost

• Solution size

• Customer preference for charge pumps

Highest efficiency is usually not the key selection criteria since USB OTG devices typically consume 10 mA of current at 3.6 V battery voltage (average). Output voltage regulation accuracy is not critical either since both charge pump as well as boost converter output voltage regulation easily meet the USB OTG specification.

SOlUTIOn

A very cost-effective, simple and easy to implement solution is based on a charge pump architecture. The flying cap of a charge pump (0603: 1.6 x 0.8 mm²) compared to the size of the 1 µH inductor (2012 housing: 2 x 1.25 mm²) used with a 3.5 MHz boost converter exhibits the size advantage of the charge pump. In addition, there is a cost advantage both for the IC and the conversion element (flying cap vs. inductor). Furthermore and sometimes most important, some customers prefer the ease of design of a charge pump (1st order control loop) over the complexity that comes with a boost converter (2nd order control loop). Layout is simple and straight forward.


VIN = 2.7...5.5 V

140 mA (VIN ≥ 3.3 V)

GND

VIN

VBUS5 V

GND

ID

D+

D-

VOUT

ENA

CP- C21 µF

C12.2 µF

C32.2 µF

CP+

50 mA (VIN ≥ 2.7 V)

Controller

Comparator

USBTransceiver

VIN

VOUT

C14.7 μF

C32.2 μF

C22.2 μF

ENABLE/DISABLE

VOUT(5.0 V)

VIN

GND

CP-

CP+

ENA

Typical Application Circuit for a Charge Pump USB OTG 5 V Supply

Application Example

Special Edition

SAmPlE PACk




PRODUCT: TPS60150

Key Features

• 2.7...5.5 V input voltage range

• Fixed output voltage of 5.0 V

• X2 charge pump

• 1.5 MHz switching frequency

• Maximum output current : 140 mA

• 2 x 2 QFN with 0.8 mm height

• Typical 90 μA quiescent current at no load condition (skip mode)

• Hardware en/disable function

• Built-in soft start

• Built-in under voltage lock-out protection

• Thermal and over-current protection


VIN

VOUT

VREF

CP+

GND

CP-

Φ1

Φ2

Φ2

Φ1

CF

ENA

TSDUVLO

Regulation

Current LimitSoft Start

Control

OSC1.5 MHz

Bias circuit

Enable IC

TPS60150

2

4

3

ErrorAmp+-

++- -

Skip Comp

R1

R2

1

5

6

Functional Block Diagram

C14.7μF

CP-VIN

VOUT

GND

CP+

ENA

C32.2μF

C22.2μF

VIN

VOUT(5.0V)

ENABLE/DISABLE

TPS60150

www.ti.com SLVS888B –DECEMBER 2008–REVISED FEBRUARY 2011

TPS60150 5V/140mA Charge Pump DeviceCheck for Samples: TPS60150

1FEATURES DESCRIPTION• 2.7V to 5.5V Input Voltage Range The TPS60150 is a switched capacitor voltage

converter which produces a regulated, low noise, and• Fixed Output Voltage of 5.0Vlow-ripple output voltage (5V) from an unregulated• X2 Charge Pumpinput voltage.

• 1.5 MHz Switching FrequencyThe 5V output can supply a minimum of 140mA• Maximum Output Current : 140mA current with a small 2X2 QFN package.

• 2X2 QFN With 0.8mm HeightTPS60150 operates in skip mode when the load• Typical 90μA Quiescent Current at no Load current falls below 8mA under typical condition. InCondition (Skip mode) skip mode operation, quiescent current is reduced to

• Hardware En/Disable Function 90μA.• Built-in Soft Start Only 3-external capacitors are needed to generate• Built-in Under Voltage Lock Out Protection the output voltage, therefore saving PCB space.• Thermal and Over Current Protection Inrush current is limited by the soft start function

during power on and power transient states.APPLICATIONS• USB OTG• HDMI• Portable Communication Devices• Personal Digital Assistance• PCMCIA Cards• Cellular Phones• Handheld Meters

Figure 1. Typical Application Circuit

ORDERING INFORMATIONPART OUTPUT PACKAGETA PACKAGE(2) ORDERING PKG MARKINGNUMBER(1) VOLTAGE DESIGNATOR

–40°C to 85°C TPS60150 5.0V SON 2x2-6 DRV TPS60150DRV CGO

(1) The DRV (2-mm x 2-mm 6-terminal SON) package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reeland T suffix to order quantities with 250 parts per reel.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.

1


PRODUCTION DATA information is current as of publication date. © 2008–2011, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

TPS60150

SLVS888B –DECEMBER 2008–REVISED FEBRUARY 2011 www.ti.com

ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted) (1)

VALUE UNITVI Input voltage range (all pins) –0.3 to 7 V

HBM ESD Rating (2) 2 kVCDM ESD Rating(3) 500 VMM ESD Rating (4) 200 V

TA Operating temperature range –40 to 85 °CTJ Maximum operating junction temperature 150 °CTst Storage temperature –55 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The Human body model (HBM) is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The testing is done accordingJEDECs EIA/JESD22-A114.

(3) Charged Device Model(4) Machine Model (MM) is a 200pF capacitor discharged through a 500nH inductor with no series resistor into each pin. The testing is

done according JEDECs EIA/JESD22-A115.

THERMAL INFORMATIONTPS60150

THERMAL METRIC(1) UNITSDRV (6 Pins)

θJA Junction-to-ambient thermal resistance 69.1θJCtop Junction-to-case (top) thermal resistance 79.8θJB Junction-to-board thermal resistance 38.6 °C/WψJT Junction-to-top characterization parameter 1.2ψJB Junction-to-board characterization parameter 38.4θJCbot Junction-to-case (bottom) thermal resistance 9.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNIT

VIN Input voltage range 2.7 5.5 VTA Operating ambient temperature –40 85 °CTJ Operating junction temperature –40 125 °CCin Input capacitor 2.2 μFCo Output capacitor 2.2 μFCf Flying capacitor 1.0 μF

ELECTRICAL CHARACTERISTICSVIN=3.6V, TA = –40°C to 85°C, typical values are at TA = 25°C, C1 = C3 = 2.2μF, C2 = 1.0μF (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER STAGEVIN Input voltage range 2.7 5.5 VVUVLO Undervoltage lockout threshold 1.9 2.1IQ Operating quiescent current IOUT = 140 mA, Enable = VIN 4.7 mAIQskip Skip mode operating quiescent IOUT = 0 mA, Enable=VIN (No switching) 80 μA

current IOUT = 0 mA, Enable = VIN(Minimum switching) 90 μAISD Shut down current 2.7 V ≤ VIN ≤ 5.5 V, Enable = 0 V 1 μAVOUT Output voltage(1) IOUT ≤ 50 mA, 2.7 V ≤ VIN < 5.5V 4.8 5.0 5.2 V

(1) When in skip mode, Output voltage can exceed VOUT spec because VOUT(skip)=VOUT+0.1.

2 Submit Documentation Feedback © 2008–2011, Texas Instruments Incorporated

Product Folder Link(s): TPS60150



ProDucT: cDcE72010

Key Features

• Outputs can be 10 LVPECL or 10 LVDS or 20 LVCMOS or any combination up to 1.5 GHz

• Output divider is selectable to divide by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70 & 80 on each output individually up to eight dividers (Except for output 0 & 9. Output 0 follows output 1 divider and output 9 follows output 8 divider.)

• Accepts two differential inputs (LVPECL or LVDS) up to 500 MHz (or two LVCMOS inputs up to 250 MHz) as PLL reference IPS #7 – CDCE72010

10 Outputs Low Jitter Clock Synchroniser & Jitter Cleaner w/ext. VC(X)O

3.3 V

10 In

div

idu

al D

ivid

erW

ide

Ran

ge

Inte

gerInput

Divider

EEPROM

ExtVCXO

LVDS/LVPECL/LVCMOSLVPECL/LVCMOS/LVDS

Ph

ase

Ad

just

PFDCharge Pump

FeedbackDivider

LoopFilter

SPI

EEPROM

• VCXO_IN frequencies up to 1.5 GHz (LVPECL) , 800 MHz for (LVDS) and 250 MHz for LVCMOS level signaling

• Output 9 can be converted to an auxiliary input as a 2nd VC(X)O or to serve as PLL feedback signal

• Optional configuration default pins to select between two default settings stored in EEPROM

• SPI controllable device settings

Device Block Diagram

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ISSuE

Jitter is the most commonly used measure of the performance of a clock. It is defined as any signal edge deviation from ideal. There are three main types of jitter that are commonly considered. These are period, phase, and cycle-to-cycle. Common Jitter performance can range from < 200 fs to 100 ps. PeriodThe deviation in cycle time of a signal with respect to ideal period over a random sample of cycles. This is also referred to as short-term jitter.Cycle-to-CycleThe variation in cycle time of a signal between consecutive cycles, over a random sample of successive cycle pairs. Also known as adjacent cycle jitter.PhaseThe integrated value from phase noise plot in time over a specific band of frequencies. This is long term jitter.

SoluTIon

The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The built-in synchronisation latches ensure that all outputs are synchronised for very low output skew. All device settings, including output signaling, divider value selection, input selection, and many more, are programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device settings.

• Wide input/output frequency range supports, high and low end of frequency standards

• Selectable input/output standards reduces translation logic

• External loop filter provides maximum flexibility

• EEPROM saves default start-up settings

• SPI interface provides in-system programming

• QFN-64 package, Temp -40...+85 °C

IPS #7 – CDCE7201010 Outputs Low Jitter Clock Synchroniser

& Jitter Cleaner w/ext. VC(X)O

Yx, FBOUT

Yx, FBOUT

tcycle n

tjit(per) = tcycle n fO1

tjit(cc) = tcycle n - tcycle n+1

tcycle n+1tcycle n

Yx, FBOUT

Yx, FBOUT

-30

-50

-70

-90

-110

-130

-150

10 100 1000 10000 100000Frequency (Hz offset from carrier)

Ph

ase

No

ise

(dB

c/H

z)

phase noise plotintegration area

Phase Noise

Cycle-to-Cycle

Period Jitter

Special Edition

SAmPlE PAck




ProDucT: cDcE72010

Key Features

• Outputs can be 10 LVPECL or 10 LVDS or 20 LVCMOS or any combination up to 1.5 GHz

• Output divider is selectable to divide by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70 & 80 on each output individually up to eight dividers (Except for output 0 & 9. Output 0 follows output 1 divider and output 9 follows output 8 divider.)

• Accepts two differential inputs (LVPECL or LVDS) up to 500 MHz (or two LVCMOS inputs up to 250 MHz) as PLL reference IPS #7 – CDCE72010

10 Outputs Low Jitter Clock Synchroniser & Jitter Cleaner w/ext. VC(X)O

3.3 V

10 In

div

idu

al D

ivid

erW

ide

Ran

ge

Inte

gerInput

Divider

EEPROM

ExtVCXO

LVDS/LVPECL/LVCMOSLVPECL/LVCMOS/LVDS

Ph

ase

Ad

just

PFDCharge Pump

FeedbackDivider

LoopFilter

SPI

EEPROM

• VCXO_IN frequencies up to 1.5 GHz (LVPECL) , 800 MHz for (LVDS) and 250 MHz for LVCMOS level signaling

• Output 9 can be converted to an auxiliary input as a 2nd VC(X)O or to serve as PLL feedback signal

• Optional configuration default pins to select between two default settings stored in EEPROM

• SPI controllable device settings

Device Block Diagram

1FEATURES

APPLICATIONS

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A–JUNE 2008–REVISED JULY 2009

Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor• Wide Charge-Pump Current Range From

200µA to 3mA• High Performance LVPECL, LVDS, LVCMOSPLL Clock Synchronizer • Dedicated Charge-Pump Supply for Wide

Tuning Voltage Range VCOs• Two Reference Clock Inputs (Primary andSecondary Clock) for Redundancy Support • Presets Charge-Pump to VCC_CP/2 for Fastwith Manual or Automatic Selection Center-Frequency Setting of VC(X)O,

Controlled Via the SPI Bus• Accepts Two Differential Input (LVPECL orLVDS) References up to 500MHz (or Two • SERDES Startup Mode (Depending on VCXOLVCMOS Inputs up to 250MHz) as PLL Range)Reference • Auxiliary Input: Output 9 can Serve as 2nd

• VCXO_IN Clock is Synchronized to One of Two VCXO Input to Drive All Outputs or to Serve asReference Clocks PLL Feedback Signal

• VCXO_IN Frequencies up to 1.5GHz (LVPECL) • RESET or HOLD Input Pin to Serve as Reset or800Mhz for LVDS and 250MHz for LVCMOS Hold FunctionsLevel Signaling • REFERENCE SELECT for Manual Select

• Outputs Can be a Combination of LVPECL, Between Primary and Secondary ReferenceLVDS, and LVCMOS (Up to 10 Differential ClocksLVPECL or LVDS Outputs or up to 20 LVCMOS • POWER DOWN (PD) to Put Device in StandbyOutputs), Output 9 can be Converted to an ModeAuxiliary Input as a 2nd VC(X)O. • Analog and Digital PLL Lock Indicator

• Output Divider is Selectable to Divide by 1, 2, • Internally Generated VBB Bias Voltages for3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, Single-Ended Input Signals40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each

• Frequency Hold-Over Mode Activated byOutput Individually up to Eight Dividers.HOLD Pin or SPI Bus to Improve Fail-Safe(Except for Output 0 and 9, Output 0 FollowsOperationOutput 1 Divider and Output 9 Follows Output

• Input to All Outputs Skew Control8 Divider)• Individual Skew Control for Each Output with• SPI Controllable Device Setting

Each Output Divider• Individual Output Enable Control via SPI• Packaged in a QFN-64 PackageInterface• ESD Protection Exceeds 2kV HBM• Integrated On-Chip Non-Volatile Memory

(EEPROM) to Store Settings without the Need • Industrial Temperature Range of –40°C to 85°to Apply High Voltage to the Device

• Optional Configuration Pins to Select Between• Low Jitter Clock Driver for High-End TelecomTwo Default Settings Stored in EEPROM

and Wireless Applications• Efficient Jitter Cleaning from Low PLL Loop• High Precision Test EquipmentBandwidth

• Very Low Phase Noise PLL Core• Programmable Phase Offset (Input Reference

to Outputs)These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

1



DESCRIPTION

PFD

ChargePump

PPRRII __II NN

SSEECC__II NN

AAuuxxiilliiaarryy IInnppuutt

VCXO/�VCO�IN

EEPROM

Output�Divider�1

U0N

U0P

U1N

U1P

U2N

U2P

U3N

U3P

U4N

U4P

U5N

U5P

U6N

U6P

U7N

U7P

U8N

U8P

U9N�or AUX�IN–

U9P or AUX�IN+








PLL_LOCKREF_SEL

POWER�DOWNRESET HOLDor

MODE_SEL

AUX_SEL

SPI_MISOSPI_LE�(CD1)

SPI_CLK�(CD2)SPI_MOSI�(CD3)

Interface&�Control

FeedbackDivider

CDCE72010

SCAS858A–JUNE 2008–REVISED JULY 2009.............................................................................................................................................................. www.ti.com

The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes aVCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of tworeference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. Thefollowing relationship applies to the dividers:

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)

The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filtercomponents. The PLL loop bandwidth and damping factor can be adjusted to meet different systemrequirements.

The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supportsfrequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are userdefinable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. Thebuilt-in synchronization latches ensure that all outputs are synchronized for very low output skew.

All device settings, including output signaling, divider value selection, input selection, and many more, areprogrammable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the devicesettings.

The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C.

Figure 1. High Level Block Diagram of the CDCE72010


Product Folder Link(s): CDCE72010



ProDucT: TLK100

Key Features

• Low and deterministic channel latency

• Extended cable reach to 200 m

• 16 kV ESD protection on Bus pins

• IEEE 802.3 compliance

• Industry-standard MII interface to MAC

• Auto-MDIX/auto-negotiation/auto-polarity

• Flexible supply options: 3.3 V or 3.3 V & 1.8 V & 1.1 V

• Cable diagnostics (breaks/damage/length)

• IEEE 1149.1 JTAG

• 48-pin TQFP package

ISP #8 – TLK100Industrial Ethernet PHY

MII Connector5 V FROM MII

3.3 V

1.8 VRegulator

1.1 VRegulator BUS MII

1.1 V

25M CLK OUT

25 MHz Crystal Oscillator

LED

s

Boot Resistors/Jumpers

JTAG

TLK100DUT

1.8 V3.3 V

LED ACT/COL

LED SPEED

LED LINK

Reset

Magnetics Pulse HX 1188

RJ45

POR

3.3 VRegulator

EVM: TLK100EXTEVM

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ISSuE

If you are looking at wire-based data transmission in a network system, you are faced with bandwidth constraints, data fault and data corruption issues. Also compliancy and interoperability is in order to connect to an existing network can be a challenge.

The TLK100 is a single-port Ethernet PHY for 10BASE-T and 100BASE-TX signaling. It integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. This device supports the standard Media Independent Interface (MII) for direct connection to a Media Access Controller (MAC).

SoLuTIon

The TLK100 Fast Ethernet transceiver is the physical layer core for Ethernet 100BASE-TX and 10BASE-T applications. It contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.3 Standard Fast Media Independent Interface (MII) for direct connection to a MAC/Switch port.

The TLK100 uses mixed signal processing to perform equalisation, data recovery and error correction to achieve robust and low power operation over the existing CAT 5 twisted pair wiring. The TLK100 architecture not only meets the requirements of IEEE802.3, but maintains a high level of margin over the IEEE requirements for NEXT and Alien noise.

ISP #8 – TLK100Industrial Ethernet PHY

MPU/CPUMII

25 MHzClock

Source

StatusLEDs

TLK100

10/100 Mb/s

10BASE-Tor

100BASE-TX

Med

ia A

cces

s C

on

tro

ller

Mag

net

ics

RJ-

45

System Diagram

Special Edition

SAmPLE PAcK




ProDucT: TLK100

Key Features

• Low and deterministic channel latency

• Extended cable reach to 200 m

• 16 kV ESD protection on Bus pins

• IEEE 802.3 compliance

• Industry-standard MII interface to MAC

• Auto-MDIX/auto-negotiation/auto-polarity

• Flexible supply options: 3.3 V or 3.3 V & 1.8 V & 1.1 V

• Cable diagnostics (breaks/damage/length)

• IEEE 1149.1 JTAG

• 48-pin TQFP package

Documents

First Aid Kit TI_First Aid Kit_2011.pdf · Octal, 144 kHz, Simultaneous Sampling 24-bit Delta Sigma ADC • REF5025 Low Noise, Very Low Drift, Precision Voltage Reference • TLV431A