7
Field-programmable technology: today’s and tomorrow’s Wayne LUK Computer Engineering, Imperial College, London, UK - [email protected] 1 Field-Programmable Technology: Today’s and Tomorrow’s Wayne Luk Imperial College London TWEPP-07 Prague 4 September 2007 2 Outline: technology = devices + design 1. overview: motivation and vision 2. field-programmable devices: today - Xilinx Virtex-4, Virtex-5; Stretch S5 3. field-programmable design : today - enhance optimality and re-use 4. field-programmable devices: tomorrow - hybrid FPGA, die stacking 5. field-programmable design : tomorrow - guided synthesis, representation, upgradability 6. summary Thanks to colleagues, students and collaborators from Imperial College, University of British Columbia, Chinese University of Hong Kong, University of Massachusetts Amherst, UK Engineering and Physical Sciences Research Council, Stretch, Xilinx 3 1. Motivation: good - Moores Law • rising – capacity – speed • falling – power/MHz – price Source: Xilinx 4 1 L o g i c T r a n s i s t o r s p e r C h i p ` ( K ) P r o d u c t i v i t y T r a n s . / S t a f f - M o n t h 10 100 1,000 10,000 100,000 1,000,000 10,000,000 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Logic (Moore’s Law) Transistors/Chip Transistor/Staff Month 58%/Yr. compound Complexity growth rate 21%/Yr. compound Productivity growth rate 1 9 8 1 1 9 8 3 1 9 8 5 1 9 8 7 1 9 8 9 1 9 9 1 1 9 9 3 1 9 9 5 1 9 9 7 1 9 9 9 2 0 0 3 2 0 0 1 2 0 0 5 2 0 0 7 2 0 0 9 x x x x x x x P P P challenge: reduce the design productivity gap Not so good: design productivity gap Source: SEMATECH 5 Our vision: unified synthesis + analysis C/Matlab/Premiere Compiler Machine code Run-time interface Configuration information Custom computing system /Progol application description manual/automatic partition, compile, analysis, validate system-specific architecture system-specific programming interface Java/ CPUs + DSPs FPGAs + sensors 6 500MHz Flexible Soft Logic Architecture 500MHz Programmable DSP Execution Units 0.6-11.1Gbps Serial Transceivers 450MHz PowerPC™ Processors with Auxiliary Processor Unit 1Gbps Differential I/O 500MHz multi-port Distributed RAM 500MHz DCM Digital Clock Management 2a. Devices today: Virtex-4 FPGA • fine-grain fabric + special function units • challenge: use resources effectively Source: Xilinx 47

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Page 1: Field-programmable technology: today s and tomorrow s ... fileField-programmable technology: today s and tomorrow s Wayne LUK Computer Engineering, Imperial College, London, UK - w.luk@imperial.ac.uk

Field-programmable technology: today’s and tomorrow’s Wayne LUK

Computer Engineering, Imperial College, London, UK - [email protected]

1

1

Field-Programmable Technology: Today’s and Tomorrow’s

Wayne LukImperial College London

TWEPP-07Prague

4 September 20072

Outline: technology = devices + design1. overview: motivation and vision2. field-programmable devices: today

- Xilinx Virtex-4, Virtex-5; Stretch S5 3. field-programmable design : today

- enhance optimality and re-use 4. field-programmable devices: tomorrow

- hybrid FPGA, die stacking 5. field-programmable design : tomorrow

- guided synthesis, representation, upgradability6. summary Thanks to colleagues, students and collaborators from Imperial College, University of

British Columbia, Chinese University of Hong Kong, University of Massachusetts Amherst, UK Engineering and Physical Sciences Research Council, Stretch, Xilinx

3

1. Motivation: good - Moore’s Law

• rising– capacity– speed

• falling– power/MHz– price

Source: Xilinx4

1

Logi

cT r

ansi

stor

spe

r Ch i

p`(K

)

Pro d

uct i v

i tyTr

ans.

/ Sta

f f- M

onth

10

100

1,000

10,000

100,000

1,000,000

10,000,000

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic (Moore’s Law) Transistors/ChipTransistor/Staff Month

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

1 98 1

1 98 3

1 98 5

1 98 7

1 98 9

1 99 1

1 99 3

1 99 5

1 99 7

1 99 9

2 00 3

2 00 1

2 00 5

2 00 7

2 00 9

xx xx x

x

x

challenge: reduce the design productivity gap

Not so good: design productivity gap

Source: SEMATECH

5

Our vision: unified synthesis + analysis

C/Matlab/Premiere

Compiler

Machinecode

Run-timeinterface

Configurationinformation

Fixed processor Custom processor

Custom computing system

/Progolapplicationdescription

manual/automatic partition, compile, analysis, validate

system-specific architecture

system-specific programming interface

Java/

CPUs + DSPs FPGAs + sensors

6

500MHz FlexibleSoft Logic Architecture

500MHz Programmable DSP Execution Units

0.6-11.1GbpsSerial Transceivers

450MHz PowerPC™ Processorswith

Auxiliary Processor Unit

1Gbps DifferentialI/O

500MHz multi-portDistributed RAM

500MHz DCM DigitalClock Management

2a. Devices today: Virtex-4 FPGA

• fine-grain fabric + special function units• challenge: use resources effectively

Source: Xilinx

47

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2

7

2b. Virtex-5 FPGA

Source: Xilinx

• capacity– rises

• logic speed– rises

• I/O speed– rises

• all good news?

8

Growing gap: amount of gates vs I/O

Source: Xilinx

• I/O off-chip– serial

• I/O on-chip– scalable– flexible– easy to use

• interconnect– heterogeneous– customisable

9

2c. Software configurable engine: S5Wide Register File (WRF)• 32 Wide Registers (WR)• 128-bit WideLoad/Store Unit• 128-bit Load/Store• Auto Increment/Decrement• Immediate, Indirect, Circular• Variable-byte Load/Store• Variable-bit Load/Store

ISEF• Instruction Specialization Fabric• Compute Intensive• Arbitrary Bit-width Operations• 3 Inputs and 2 Outputs• Pipelined, Bypassed, Interlocked• Random Logic Support• Internal State Registers

ALUFPU

32-BIT RF

CO

NTR

OL 128-BIT WRF32-BIT RF

ALUFPU

S5 ENGINE

ISEFInstruction-Set

Extension Fabric

DATA RAM32KB

SRAM256KB

D-CACHE32KB

I-CACHE32KB

MMU

RISC Processor• Tensilica – Xtensa V• 32 KB I & D Cache• On-Chip Memory, MMU• 24 Channels of DMA, FPU

Source: Stretch

10

3. Design today: overview• structural or register-transfer level (RTL)

– e.g. VHDL, Verilog– low-level, little automation, small designs

• behavioural, system-level descriptions– e.g. SystemC (public-domain: systemc.org)– MARTES: +UML for real-time embedded systems

• general-purpose software languages– e.g. C, Java; with hardware support: Handel-C– high-level, large automation, large designs

• special-purpose descriptions– e.g. System Generator (signal processing)– high-level, domain-specific optimisations

11

3a. Enhance optimality and re-use

• design optimality: quality– select algorithm and devices: meet requirements– mapping: regular to systolic, rest to processor– I/O: dictates on-chip parallelism, buffering schemes– control speed/area/power: pipelining, layout plan– partitioning: coarse vs fine grain logic and memory

• design re-use: productivity– separate aspects specific to application/technology– library of customisable components with trade-offs– compose and customise to meet requirements– uniform interface to memory and I/O: hide details– pre-verified parts: ease system verification

12

Example: systolic summation tree• n-input adder

– tree of (n-1)2-input adders

• each adder– has k stages– each stage

has s-bit adder• figure shows

– k = 3– s = 3

• high k, low s– less cycle time– more area– less power

48

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13

Finance application: value-at-risk

• sampling from multivariateGaussian distribution

• DSP units: matrix multiplication

• systolic tree: accumulate result

• RC2000 board– Virtex-4 xc4vsx55– 400MHz

64DSPs

48DSPs

GaussianRNG

Delta GammaAccumulator

Control RC2000Interface

IO Clock domain

FIFO

FIFO

+ + + +

+ +

+

33 times faster than 2.2GHz quad Opteron(including all IO overheads, PC-FPGA communications, and using AMD

optimised BLAS for software)14

CO

NTR

OL

3b. Stretch program development• profile code

–identify hotspots• special instruction

–implement ‘C’functions in single instructions

–bit-width optim.• software compiler

–generate instruction–schedule instruction

• multiple data (WR)–perform operations

in parallel • efficient data

movement – intrinsic load store

operations–20+ DMA channels

APPLICATIONC/C++

COMPILEDMACHINE

CODE

Compiler

InstructionDefinition

NEW INSTRUCTIONS

INSTRUCTIONGENERATION

TAILOR ISEF TO APPLICATION

AUTOMATIC

Source: Stretch

15

500MHz FlexibleSoft Logic Architecture

500MHz Programmable DSP Execution Units

0.6-11.1GbpsSerial Transceivers

450MHz PowerPC™ Processorswith

Auxiliary Processor Unit

1Gbps DifferentialI/O

500MHz multi-portDistributed RAM

500MHz DCM DigitalClock Management

4. Devices tomorrow: more diversed

Source: Xilinx

Replaced by other functional units, e.g. floating-point units

16

4a. Hybrid FPGA: architecture

• most digital circuits– datapath: regular, word-based logic– control: irregular, bit-based logic

• hybrid FPGA– customised coarse-grained block:

domain-specific requirements– fine-grained blocks:

existing FPGA architecture– good match to computing

applications for given domain

17

Coarse-grained fabric library

D=9, M=4, R=3, F=3, 2 add, 2 mul: best density over benchmarks18

Evaluation

• 6 benchmark circuits– digital signal processing kernels: e.g. bfly (for FFT)– linear algebra: e.g. matrix multiplication– complete application: e.g. bgm (financial model)

• circuits: partitioned to control + datapath– control: vendor tools to fine-grained units– datapath: manually map to coarse-grained units

• comparison – directly synthesized to Xilinx Virtex-II devices

49

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19

Results

2.4818.3Geometric Mean

2.4316.724.343020710.001810bgm

2.2515.121.9382389.74545ode

2.6313.823.488898.90642mm3

2.6130.423.68112909.06371fir4

2.2514.522.78961410.11661dscg

2.7224.324.57137339.02565bfly

Delay(times)

Area(times)

Delay(ns)

Area(slices)

Delay(ns)

Area(slices)

XC2V3000-6Floating Point hybrid FPGA

20

4b. On-chip memory bandwidth

• storage hierarchy: registers, LUT RAM, block RAM• processor cache: address lack of I/O bandwidth

Source: Xilinx

21

High density die stacking

Source: Xilinx 22

Programmable circuit board

Source: Xilinx

• die stacking: 3D interchip connections• customisable system-in-package: productivity gap?

23

5a. Design tomorrow: guided synthesis• guided transformation of design descriptions

– automate tedious and error-prone steps– applicable to various levels of abstraction

• focus: two timing models– strict timing model: cyclecycle--accurate accurate -- efficiencyefficiency– flexible timing model: behaviouralbehavioural -- productivityproductivity

• combine cycle-accurate and behavioural models– rapid development with high quality– design maintainability and portability

• based on high-level language– library developer: provide optimised building blocks– application developer: customise building blocks

24

Timing models: strict vs flexible

{delta = b*b - ((a*c) << 2);if (delta > 0)

num_sol = 2;else if (delta == 0)

num_sol = 1;else

num_sol = 0;}

{delta = b*b - ((a*c) << 2);if (delta > 0)

num_sol = 2;else if (delta == 0)

num_sol = 1;else

num_sol = 0;}

b a c

* *<<

-delta

> 0

num_sol

== 02

1

0

2

MU

X

MU

X

executed executed at cycleat cycle 11

executed executed at cycle 2at cycle 2

cc

cctrue

c

*

a

b b

* << 2

-

>

=

= =

==

true false

false

num_sol

num_sol num_sol

0

0

0

2

1

strict timing(Handel-C)

flexibletiming

behavioural model- partial-ordering- abstract operations

cycle accurate model- total-ordering- resource-bound

scheduling unscheduling

50

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{delta = b*b - ((a*c) << 2);if (delta > 0)

num_sol = 2;else if (delta == 0)

num_sol = 1;else

num_sol = 0;}

{delta = b*b - ((a*c) << 2);if (delta > 0)

num_sol = 2;else if (delta == 0)

num_sol = 1;else

num_sol = 0;}

cc

cctrue

c

*

a

b b

* << 2

-

>

=

= =

==

true false

false

num_sol

num_sol num_sol

0

0

0

2

1

unschedulingunscheduling(flexible timing)(flexible timing)

schedulingscheduling

constraintsconstraints

+

par {// ================== [stage 1]pipe_mult[0].in(b,b);pipe_mult[1].in(a,c);// ==================[stage 8]tmp0 = pipe_mult[0].q;tmp1 = pipe_mult[1].q << 2;// ==================[stage 9]tmp2 = tmp0 - tmp1;// ==================[stage 10]if (tmp2 > 0) num_sol = 2;else if (tmp2 == 0) num_sol = 1;else num_sol = 0;delta = tmp2;

}

synthesissynthesis(strict timing)(strict timing)

b a c

pmult[0]

delta

> 0

num_sol

==2

10

pmult[1]

<< 2

tmp1

-tmp2

tmp0

stage 1-7

stage 8

stage 9

stage 10

cyclecycle 11M

UX

MU

X

Rapid design: automated scheduling

• support combination of manual and automatic scheduling 26

par {{ // ================= [stage 1]

pipe_mult[0].in(b,b);pipe_mult[0].in(a,c);

}....

}

Maintainability: retarget design

par {// ================== [stage 1]pipe_mult[0].in(b,b);pipe_mult[1].in(a,c);// ==================[stage 8]tmp0 = pipe_mult[0].q;tmp1 = pipe_mult[1].q << 2;// ==================[stage 9]tmp2 = tmp0 - tmp1;// ==================[stage 10]if (tmp2 > 0) num_sol = 2;else if (tmp2 == 0) num_sol = 1;else num_sol = 0;delta = tmp2;

}

b a c

pmult [0]

delta

> 0

num_sol

==2

10

pmult [1]

<< 2tmp1

-tmp2

tmp0

stage 1-7

stage 8

stage 9

stage 10

cyclecycle 11

MU

X

MU

X

cc

cctrue

c

*

a

b b

* << 2

-

>

=

= =

==

true false

false

num_sol

num_sol num_sol

0

0

0

2

1

schedulingscheduling

constraintsconstraints

+

unschedulingunscheduling(flexible timing)(flexible timing)

b a c

pmult[0]

> 0

num_sol

==2 1

0

tmp1

tmp0

-tmp2

pmult[0]

cycle 2cycle 2

cycle 1cycle 1

<< 2

stage 1-4

stage 5

stage 6

cycle 1cycle 1

cycle 2cycle 2

cycle 1cycle 1

cycle 2cycle 2

MU

X

MU

X

synthesissynthesis(strict timing)(strict timing)

27

Implementation

28

Automatically generated results

• ffd: free-form deformation; dct: discrete cosine transform

with respect to smallestwith respect to software

29

5b. Data representation optimisationIn1 In2 In3 In4 In5

+ *

-

+

*+

+

Out1 Out2

X

Y

• In1..In5– known width

• Out1..Out2– width determines

accuracy– defined by user

• find representation– minimise width of

nodes, e.g. X, Y

• trade-off in speed, area, power, error

30

Floating-point design Fixed-point design

Output Design Descriptions

Xilinx System GeneratorVHDL

A Stream Compiler (ASC) CodeAnnotated DFG HandelC

Designdatabase

Range analysis( Interval analysis )

Precision analysis( Automatic Differentiation )

Bit-width determination Bit-width determination

Design Selection

BitSize bit-width analysis system - Frontend

BitSize bit-width analysis system - Backend

User Specified designconstraints

Input Design DescriptionsXilinx System GeneratorC/C++ ASC CodeHandelC

Design Selection

Fixed-point- range: integer

- precision: fraction

Floating-point

- range: exponent

- precision: mantissa

51

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0 5 10 15 20 250

500

1000

1500

2000

2500

3000

Error Percentage

Area

- Vi

rtex2

Slic

es

DFT4-Tap FIR filter

FIR filter and DFT: area vs error

1% more error: 65% less area

32

0 5 10 15 20 2520

30

40

50

60

70

80

90

Error Percentage

Spee

d - M

Hz

DFT4-Tap FIR filter

FIR filter and DFT: speed vs error

2% more error: 20% higher speed

33

5c. Upgradable design

initial release

Number of new users

upgradabledesign

non-upgradabledesign

10 20 30

upgrade 1

upgrade 2

Time (months)

Source: Xilinx

• upgradability: minimise time-to-marketmaximise time-in-market

• add new functions, fix bugs• very rapid upgrade?

34

Dynamic upgrade: turbo coder

• error correction code: add redundancy• need: fast, low-power, adapt to noise level• recursive systematic convolutional (RSC)

encoder, decoder, interleaver

RSC

RSC

Interleaver

Decoder

Decoder

InterleaverDe-Interleaver

Interleaver

DecideIn Out

Turbo encoder Turbo decoder

noisycommun.channel

Source: Liang, Tessier, Goeckel

35

Self-tuning: run-time reconfiguration• adapt: less channel noise, so lower power • larger Nmax: better correction, more area/power • sample channel noise every 250K bits• find Signal to Noise Ratio (SNR), select Nmax

• if Nmax current Nmax, configure new bitstream• configuration overhead: about 30ms, 54.8mW

controller

LUTSNR =?

Nmax

current Nmax

ConfigureFPGA

Source: Liang, Tessier, Goeckel 36

Performance of dynamic upgrade

111.6131.7216.2power (mW)

487.9301.2173.4speed (Kbps)static

134.3205.8447.7power (mW)

dynamic

18%36%52%power saving

598.6429.4359.1speed (Kbps)

6925/10000

6306/10000

8369/10000

requiredreconfigs

(15,13)(31,27)(65,57)code

• up to 0.5x power, 2x speed over static decoder• 100 times faster than processor decoder

Source: Liang, Tessier, Goeckel

52

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• domain-specific design automation– languages + tools: for particle physics systems?

• multi-core, sensor network co-design– multiple hardware/software: FPGA + CPU + sensors

• extending processor and compiler capabilities– static and dynamic optimizations, self-tuning

• power-aware, radiation-aware design– transforms e.g. pipelining, damage monitoring

• rapid and informative design validation– simulation + FPGA prototype + formal verification

Other directions

38

• good: Moore’s Law, bad: productivity gap• vision: unified design synthesis and analysis• devices and design today

– growing gap: amount of I/O and amount of logic – enhance optimality and re-use: I/O driven

• devices tomorrow– hybrid FPGA: multi-granularity fabric– 3D FPGA: customisable system-in-package

• design tomorrow– guided synthesis: optimised and portable design – data representation optimisation– upgradable and self-tuned design

6. Summary

53