Evaluating the ADuC7026 MicroConverter - Analog Devices · 2017. 2. 15. · To enter serial download mode, the user must pull the P0.0/BM pin low while reset is toggled. On the evaluation

EVAL-ADuC7026 User Guide UG-669

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the ADuC7026 MicroConverter

Rev. B | Page 1 of 16

FEATURES Full featured evaluation system for the ADuC7026 2-layer PCB (4” × 5” form factor) 9 V power supply regulated to 3.3 V on board 4-pin UART header to connect to RS-232 interface cable 20-pin standard JTAG connector Demonstration circuit 32.768 kHz watch crystal to drive the PLL clock ADR291 2.5 V external reference chip Reset/download/IRQ0 push-buttons Power indicator/general-purpose LEDs Access to all ADC inputs and DAC output from external

header. All device ports are brought out to external header pins.

Surface-mount and through-hole general-purpose prototype area

External memory and latch footprint

QUICKSTART DEVELOPMENT SYSTEM KIT CONTENTS ADuC7026 evaluation board Serial download cable International power supply CD containing

evaluation software ADuC7026 data sheet example code

QUICKSTART PLUS DEVELOPMENT SYSTEM KIT CONTENTS ADuC7026 evaluation board mIDAS-Link JTAG emulator USB cable Serial download cable International power supply CD containing

evaluation software ADuC7026 data sheet example code

GENERAL DESCRIPTION This user guide, which replaces AN-744, refers to revision B2 of the ADuC7026 MicroConverter® evaluation boards. Two models of the development kit are available: EVAL-ADuC7026QSZ is the QuickStart™ Development System; EVAL-ADuC7026QSPZ is the QuickStart Plus Development System. All references in this user guide to the physical orientation of components on the evaluation board are made with respect to a component-side view of the board with the prototype area appearing at the bottom of the board. The evaluation board is laid out to minimize coupling between the analog and digital sections of the board. To this end, the ground plane is split with the analog section on the left side and a digital plane on the right side of the board. The regulated 3.3 V power supply is routed directly to the digital section and is filtered before being routed into the analog section of the board.

EVALUATION BOARD

0503

2-10

1

Figure 1. Typical Evaluation Board

http://www.analog.com/

http://www.analog.com/aduc7026?doc=EVAL-ADuC7026_UG-669.pdf


http://www.analog.com/adr291?doc=EVAL-ADuC7026_UG-669.pdf






http://www.analog.com/eval-aduc7026qsz?doc=EVAL-ADuC7026_UG-669.pdf

http://www.analog.com/eval-aduc7026qspz?doc=EVAL-ADuC7026_UG-669.pdf

UG-669 EVAL-ADuC7026 User Guide


TABLE OF CONTENTS Features .............................................................................................. 1 QuickStart Development System Kit Contents ............................ 1 QuickStart Plus Development System Kit Contents .................... 1 General Description ......................................................................... 1 Evaluation Board .............................................................................. 1 Revision History ............................................................................... 2 Getting Started with the Evaluation Hardware ............................ 3

Power Supply ................................................................................. 3 RS-232 Interface ........................................................................... 3 Emulation Interface ...................................................................... 3 Crystal Circuit ............................................................................... 3 External Reference (ADR291) .................................................... 3 Reset/Download/IRQ0 Push-buttons ........................................ 3 Power Indicator/General-Purpose LEDs .................................. 4 Analog I/O Connections ............................................................. 4 General-Purpose Prototype Area ............................................... 4 External Memory and Latch Footprint ..................................... 4

DIP Switch Link Options ................................................................. 5 S1-1 VREF ........................................................................................ 5

S1-2 VOCM ........................................................................................5 S1-3 POT ........................................................................................5 S1-4 ADC3 .....................................................................................5 S1-5 VIN− ......................................................................................5 S1-6 VIN+ ......................................................................................5 S1-7 ADC4 .....................................................................................5 S1-8 LED .........................................................................................5

External Connectors .........................................................................6 Analog I/O Connector J3 .............................................................6 Power Supply Connector J5 .........................................................6 Emulation Connector J4 ...............................................................6 Serial Interface Connector J1 .......................................................6 Digital I/O Connector J2 ..............................................................6

External Memory Interface ..............................................................8 Connections ...................................................................................8

Potentiometer Demonstration Circuit ........................................ 10 Schematic and Artwork ................................................................. 11 Bill of Materials ............................................................................... 13

REVISION HISTORY 2/14—Rev. A to Rev. B

Reorganized Layout (from AN-744 to UG-669) ............ Universal Added Figure 1; Renumbered Sequentially and Changes to General Description Section ........................................................... 1 Change to Figure 6 ......................................................................... 12 Changes to Table 5 .......................................................................... 13

2/07—Rev. 0 to Rev. A

Reorganized Layout ............................................................ Universal Added Table 4 and changes to Figure 2 ......................................... 9 Changes to Figure 4 ........................................................................ 11 Changes to Table 5 .......................................................................... 13

2004—Revision 0: Initial Version



GETTING STARTED WITH THE EVALUATION HARDWARE POWER SUPPLY Connect the 9 V power supply via the 2.1 mm input power socket (J5). The input connector is configured as a center negative, that is, as GND on the center pin and +9 V on the outer shield.

The 9 V supply is regulated via the Linear Voltage Regulator U5. The 3.3 V regulator output is used to drive the digital side of the board directly. The 3.3 V supply is also filtered and then used to supply the analog side of the board.

When on, the LED (D3) indicates that a valid 3.3 V supply is being driven from the regulator circuit. All active components are decoupled with 0.1 µF at device supply pins to ground.

RS-232 INTERFACE The ADuC7026 (U1) P1.1 and P1.0 lines are connected to the RS-232 interface cable via Connector J1. The interface cable generates the required level shifting to allow direct connection to a PC serial port. Ensure that the cable supplied is connected to the board correctly, that is, DVDD is connected to DVDD and DGND is connected to DGND.

EMULATION INTERFACE Nonintrusive emulation and download are possible on the ADuC7026, via JTAG, by connecting a JTAG emulator to the J4 connector.

CRYSTAL CIRCUIT The board is fitted with a 32.768 kHz crystal, from which the on-chip PLL circuit can generate a 41.78 MHz clock.

EXTERNAL REFERENCE (ADR291) The external 2.5 V Reference Chip U2 has two functions. It is provided on the evaluation board to demonstrate the external reference option of the ADuC7026, but its main purpose is to generate the VOCM voltage of the differential amplifier if required.

RESET/DOWNLOAD/IRQ0 PUSH-BUTTONS A reset push-button is provided to allow the user to reset the part manually. When the button is pushed, the reset pin of the ADuC7026 is pulled to DGND. Because the reset pin on the ADuC7026 is Schmidt triggered internally, there is no need to use an external Schmidt trigger on this pin.

When pushed, the IRQ0 push-button switch drives P0.4/IRQ0 high. This can be used to initiate an external interrupt 0.

To enter serial download mode, the user must pull the P0.0/BM pin low while reset is toggled. On the evaluation board, serial download mode can easily be initiated by holding down the serial download push-button (S2) while inserting and releasing the reset button (S3) as shown in Figure 2.

S3(RESET = 1)

S2(BM = 1)

(A) S3 AND S2 RELEASED

S2(BM = 0)

S3(RESET = 1)

(B) PUSH S2

S3(RESET = 1)

S2(BM = 0)

(D) RELEASE S3

S2(BM = 0)

S3(RESET = 0)

(C) PUSH S3

S2(BM = 1)

S3(RESET = 1)

(E) RELEASE S2

0503

2-00

1

Figure 2. Entering Serial Download Mode on the Evaluation Board









POWER INDICATOR/GENERAL-PURPOSE LEDS A power LED (D3) is used to indicate that a sufficient supply is available on the board. A general-purpose LED (D2) is directly connected to P4.2 of the ADuC7026. When P4.2 is cleared, the LED is turned on, and when P4.2 is set, the LED is turned off.

ANALOG I/O CONNECTIONS All analog I/O connections are brought out on Header J3.

ADC0 and ADC1 are buffered using an AD8606 to evaluate single-ended and pseudo differential mode. A potentiometer can be connected to ADC0 (buffered).

ADC3 and ADC4 can be buffered with a single-ended to differential op amp on-board, with the AD8132 used to evaluate the ADC in fully differential mode.

ADC2 and ADC5 to ADC11 are not buffered. Be sure to follow the data sheet recommendations when connecting signals to these inputs.

DAC1 can be used to control the brightness of the LED D1, when connected via the S1 switch.

GENERAL-PURPOSE PROTOTYPE AREA General-purpose prototype areas are provided at the bottom of the evaluation board for adding external components as required in the user’s application. AVDD, AGND, VDDIO, and DGND tracks are provided in the prototype area.

EXTERNAL MEMORY AND LATCH FOOTPRINT Footprints for a 32 k × 16 static RAM (CY7C1020CV33), a 64 k × 16 flash (AT29LV1024), and a16-bit latch are also on board. See the External Memory Interface section.


http://www.analog.com/ad8606?doc=EVAL-ADuC7026_UG-669.pdf




DIP SWITCH LINK OPTIONS S1-1 VREF Function

Connects the output of the 2.5 V external reference (ADR291) to the VREF pin (Pin 68) of the ADuC7026.

Use Slide S1-1 to the on position to connect the external reference to the ADuC7026.

Slide S1-1 to the off position to use the internal 2.5 V reference or a different external reference on the VREF pin of Header J3.

S1-2 VOCM Function

Connects 1.67 V to the VOCM pin of the AD8132. No extra dc voltage is required on the board to use the ADC in differential mode.

Use

Slide S1-2 to the on position to connect VOCM of the differential amplifier to the 1.67 V divided output of the ADR291 reference.

Slide S1-2 to the off position to use a different voltage for VOCM by connecting a dc voltage to the VOCM pin of Header J3. Note that the VOCM value is dependent on the reference value, as shown in Table 1.

Table 1. VOCM Range VREF VOCM Minimum VOCM Maximum 2.5 V 1.25 V 2.05 V 2.048 V 1.024 V 2.276 V 1.25 V 0.75 V 2.55 V

S1-3 POT Function

Connects the potentiometer output to ADC0. This input is buffered by an AD8606. This is for demonstration purposes.

Use

Slide S1-3 to the on position to connect the potentiometer to the op amp of the ADC0 input channel.

Slide S1-3 to the off position to use the ADC0 input on Header J3.

S1-4 ADC3 Function

Brings out ADC3 (Pin 80) on Header J3.

Use

Slide S1-4 to the on position to connect ADC3 of Header J3 directly to the ADC3 pin (Pin 80) of the ADuC7026.

Slide S1-4 to the off position to disconnect ADC3 of Header J3 from the ADC3 pin (Pin 80) of the ADuC7026.

S1-5 VIN− Function

Connects the −OUT pin of the single-ended to differential op amp (AD8132) to ADC3. S1-5 and S1-6 must be used together. When VIN− is in the on position, VIN+ must also be in the on position to use the differential op amp on Channel ADC3 and Channel ADC4.

Use

Slide S1-5 to the on position to connect −OUT of the AD8132 to ADC3.

Slide S1-5 to the off position to use ADC3 without the AD8132.

S1-6 VIN+ Function

Connects the +OUT pin of the single-ended to differential op amp (AD8132) to ADC4. When VIN+ is in the on position, VIN− must also be in the on position to use the differential op amp on Channel ADC3 and Channel ADC4.

Use

Slide S1-6 to the on position to connect +OUT of the AD8132 to ADC4.

Slide S1-6 to the off position to use ADC4 without the AD8132.

S1-7 ADC4 Use

Slide S1-7 to the on position to connect ADC4 of Header J3 directly to the ADC4 pin (Pin 1) of the ADuC7026.

Slide S1-7 to the off position to disconnect ADC4 of Header J3 from the ADC4 pin (Pin 1) of the ADuC7026.

S1-8 LED Function

Connects the DAC1 output to the green LED of the demonstration circuit, D1.

Use

Slide S1-8 to the on position to connect the DAC1 output to D1.

Slide S1-8 to the off position to use the DAC1 output on Header J3.



















EXTERNAL CONNECTORS ANALOG I/O CONNECTOR J3 Connector J3 provides external connections for all ADC inputs, reference inputs and DAC outputs. The pinout of the connector is shown in Table 2.

POWER SUPPLY CONNECTOR J5 Connector J5 allows for the connection between the evaluation board and the 9 V power supply provided in the ADuC7026 development system.

EMULATION CONNECTOR J4 Connector J4 provides a connection of the evaluation board to the PC via a USB cable and mIDAS link provided in the ADuC7026 QuickStart Plus development system only.

SERIAL INTERFACE CONNECTOR J1 Connector J1 provides a simple connection of the evaluation board to the PC via a PC serial port cable provided with the ADuC7026 development system.

DIGITAL I/O CONNECTOR J2 Connector J2 provides external connections for all GPIOs. The pinout of the connector is shown in Table 3.

Table 2. Pin Functions for Analog I/O Connector J3 Pin No. Pin Description J3-1 AVDD J3-2 AGND J3-3 VREF J3-4 DACREF J3-5 ADC0 J3-6 ADC1 J3-7 ADC2 J3-8 ADC3 J3-9 ADC4 J3-10 ADC5 J3-11 ADC6 J3-12 ADC7 J3-13 ADC8 J3-14 ADC9 J3-15 ADC10 J3-16 ADC11 J3-17 VDIFF J3-18 VOCM J3-19 DAC0 J3-20 DAC1 J3-21 DAC2 J3-22 DAC3 J3-23 ADCNEG J3-24 AGND






Table 3. Pin Functions for Digital I/O Connector J2 Pin No. Pin Description J2-1 DGND J2-2 P4.5

AD13/PLAO[13] J2-3 P4.4

AD12/PLAO[12] J2-4 P4.3

AD/11PLAO[11] J2-5 P4.2

AD10/PLAO[10] J2-6 P1.0

T1/SIN/SCL0/PLAI[0] J2-7 P1.1

SOUT/SDA0/PLAI[1] J2-8 P1.2

RTS/SCL1/PLAI[2] J2-9 P1.3

CTS/SDA1/PLAI[3] J2-10 P1.4

IRQ2/RI/CLK/PLAI[4] J2-11 P1.5

IRQ3/DCD/MISO/PLAI[5] J2-12 P4.1

AD9/PLAO[9] J2-13 P4.0

AD8/PLAO[8] J2-14 P1.6

DSR/MOSI/PLAI[6] J2-15 P1.7

DTR/CSL/PLAO[0] J2-16 P2.2

PWM0L/RS/PLAO[7] J2-17 P2.1

PWM0H/WS/PLAO[6] J2-18 P2.7

PWM1L/MS3

J2-19 P3.7 PWMSYNC/AD7/PLAI[15]

J2-20 P3.6 PWMTRIP/AD6/PLAI[14]

J2-21 P0.7 ECLK/XCLK/SIN/PLAO[4]

Pin No. Pin Description J2-22 P2.0

CONVSTART/SOUT/PLAO[5]

J2-23 P0.5 IRQ1/ADCBUSY/MS0/PLAO[2]

J2-24 P0.4 IRQ0/PWMTRIP/MS1/PLAO[1]

J2-25 P3.5 PWM2L/AD5/PLAI[13]

J2-26 P3.4 PWM2H/AD4/PLAI[12]

J2-27 P2.6 PWM1H/MS2

J2-28 P2.5 PWM0L/MS1

J2-29 P0.3 TRST/A16/ADCBUSY

J2-30 P2.4 PWM0H/MS0





J2-35 P0.2 PWM2L/BHE

J2-36 P0.6 T1/MRST/AE/PLAO[3]

J2-37 P0.0 CMP/MS2/PLAI[7]

J2-38 P4.7 AD15/PLAO[15]

J2-39 P4.6 AD14/PLAO[14]

J2-40 P2.3 AE

J2-41 P0.1 PWM2H/BLE

J2-42 DGND



EXTERNAL MEMORY INTERFACE A footprint for a 32 k × 16 SRAM, a 64 k × 16 flash, and a 16-bit D-latch are provided on board because address and data are multiplexed on the external bus.

The memory footprints are for a CY7C1020CV33 and AT29LV1024. The latch footprint is for a 74LVT16373AGG.

Note that you can use different versions of the CY7C1020CV33 memory, with different access times. Wait states can be added in the XMxPAR register to allow for interfacing to slower memory, if required.

CONNECTIONS

Table 4. Connection Description

Controls RS, WS, and AE are the minimum control signals of any memory interface.

MS0 and MS1, memory select signals, are connected to the CE of the SRAM and the flash, respectively, to enable the memory when necessary.

BHE and BLE allows the high or low byte of the 16-bit SRAM to be selected.

Data 16 bits of address data, (AD[15:0]), are directly connected from the ADuC7026 to the memory circuitry. Addresses 16 bits of address IO[16:1] are connected from the ADuC7026 to AD[15:0] of the memory devices. AD[0] addresses a byte. To address the 32 k of the SRAM only, 14-bit addresses are required. 15-bit addresses are required for the 64 k flash.





0503

2-00

2

U7 DECOUPLING CAPACITORS U8 DECOUPLING CAPACITORS U6 DECOUPLING CAPACITORS

5A04A13A22A318A444A543A642A727A826A925A1024A1121A1220A1319A14

6CE41OE17WE

29IO9

8IO2 9IO3 10IO4 13IO5 14IO6 15IO7 16IO8

33VCC

12VSS

38IO16

40BHE

7IO1

30IO10 31IO11 32IO12 35IO13 36IO14 37IO15

11VCC

39BLE

34VSS

U8CY7C1020CV33-12

471D0461D1441D2431D3411D4401D5381D6371D7362D0352D1332D2322D3302D4292D5272D6

11OE242OE252LE

132Q0

31Q1 51Q2 61Q3 81Q4 91Q5 111Q6 121Q7

15GND

28GND

232Q7

21Q0

142Q1 162Q2 172Q3 192Q4 202Q5 222Q6

10GND

34GND

262D7

481LE7VCC18VCC31VCC42VCC

21GND

39GND 45GND

4GND

U774LVT16373ADGG

C25

0.1µF

C26

0.1µF

C27

0.1µF

C28

0.1µF

C29

0.1µF

C30

0.1µF

2A03A14A25A36A47A59A610A711A8

12VSS

13A914A1015A1117A1218A1319A1420A15

22WE

23VCC

27CE

28O15

29O14

30O13

31O12

32O11

34O10

35O9

36O8

37VSS

38O7

39O6

40O5

42O4

43O3

44O2

45O1

46O0

47OE

U6AT29LV1024

C31

0.1µF

R23

0Ω

AD[0:15]

VDDIO

ADR[0:15]

ADR0ADR1ADR2ADR3ADR4ADR5ADR6ADR7ADR8ADR9ADR10ADR11ADR12ADR13ADR14

BLEBHE

WSRS

MS0

ADR0ADR1ADR2ADR3ADR4ADR5ADR6ADR7ADR8ADR9ADR10ADR11ADR12ADR13ADR14

AE

VDDIO

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15


VDDIO VDDIO

ADR15

MS1

WS

RS

VDDIO

ADR0ADR1ADR2ADR3ADR4ADR5ADR6ADR7ADR8ADR9ADR10ADR11ADR12ADR13ADR14ADR15


VDDIO

Figure 3. External Memory Connections



POTENTIOMETER DEMONSTRATION CIRCUIT By using the sample code in pot.c located in the code example folder on the accompanying CD, the variation in the potentiometer resistance can be seen on the output LED.

Note that the internal and external reference are 2.5 V, which gives an ADC input range of 0 V to 2.5 V in single-ended mode. The potentiometer can give a voltage between 0 V and AVDD = 3.3 V.

AVDD

AVDD

APPLICATIONCODE

DACADC

0503

2-00

3

Figure 4. Circuit Diagram of the RTD Circuit



SCHEMATIC AND ARTWORK

05032–004

JTAG CONNECTOR

POW

ER S

UPP

LIES

IRQ

0

RES

ET

DEM

O C

IRC

UIT

ANALOG INTERFACE

U1

BYP

ASS

CA

PAC

ITO

RS

DIGITAL INTERFACE

P4.5

P4.4

P4.3

P4.2

P1.1

P1.2

P1.3

P1.4

P1.5

P4.1

P4.0

P1.6

P3.6

P0.7

P2.0

P0.5

P0.4

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

P0.6

P0.0

P4.7

P4.6

P1.7

P1.0

SER

IAL

DO

WN

LOA

D

DEM

O C

IRC

UIT

P4.2

VREF

VOC

M

LED

POT

AD

C3

AD

C4

IN–

IN+

UA

RT

P2.6

N/C

N/C

TDO

TDI

TMS

TCK

TRST

C9

AN

D C

10 N

OT

POPU

LATE

D

P2.2

P2.1

P2.7

P3.7

P0.1

P2.3

P0.2

P2.4

P0.3

P2.5

C9

10nF

C10

10nF

D3

1A

DC

42

AD

C5

3A

DC

64

AD

C7

5A

DC

86

AD

C9

7A

DC

108

GN

DR

EF9

AD

CN

EG10

DA

C0

11D

AC

112

DA

C2

13D

AC

314

TMS

15TD

I16

P0.1

17P2

.318

P4.6

19P4

.720

P0.0

21P0.6 22TCK 23TDO 24P0.2 25IOGND 26IOVDD 27LVDD 28DGNG 29P3.0 30P3.1 31P3.2 32P3.3 33P2.4 34P0.3 35P2.5 36P2.6 37RST 38P3.4 39P3.540P0.4

41P0

.542

P2.0

43P0

.744

XCLK

O45

XCLK

I46

P3.6

47P3

.748

P2.7

49P2

.150

P2.2

51P1

.752

P1.6

53IO

GN

D54

IOVD

D55

P4.0

56P4

.157

P1.5

58P1

.459

P1.3

60P1

.2

61 P1.162 P1.063 P4.264 P4.365 P4.466 P4.567 REFGND68 VREF69 DACREF70 DACGND71 AGND72 AGND73 AVDD74 AVDD75 DACVDD76 ADC1177 ADC078 ADC179ADC280 ADC3

U1

AD

UC

7026

C21

12pF

C20

12pF

Y1 32.7

68kH

z

S3

S4

R16 1kΩ

R17 1kΩ

C19470nF

C24 0.1µ

F

L1

R20

270Ω

R19

1.5Ω

C7 22pF

D4

R15

1kΩ

R14 0Ω

3+

2–

1

U4–

A AD

8606

AR

Z

5+

6–

7

U4–

B AD

8606

AR

Z

8V+

4V–

U4–

C

8+I

N2

VOC

M1

–IN

5–O

UT

4+O

UT

6V–3 V+

U3

AD

8132

R10

60.4Ω

R11

60.4Ω

C8 22pF

R5

348Ω

R6

348Ω

R9

348ΩR8

348Ω

C4

0.1µ

FC

1147

0nF

R22100kΩ

R21100kΩ

R18

270Ω

C12

0.1µ

F

D1

R12 270Ω

R13 0Ω

CW

R1

C2

0.1µ

F

R2

100Ω

R3

200Ω

1 2 3 4 5 6 7 8910111213141516

S1SW

8DIP

S2

2+V

IN

5TR

IM

6VO

UT

4G

NDU2

AD

R29

1E

C3

0.1µ

F

R7 24.9Ω

R4

49.9Ω

C6

0.1µ

F+

C5

10µF

+C

110

µF

J1–1

J1–2

J1–3

J1–4

D2

J4Z1

0J4

-9

J4-3

J4-4

J4-5

J4-6

J4-7

J4-8

2IN 7SD

3G

ND

1O

UT

U5

+C

2210

µF

+C

2310

µF

+ C13

10µF

C14

0.1µ

F+ C

1510

µFC

160.

1µF

C17

0.1µ

F+

C18

10µF

J5–1

J5–2

J5–3

J5–4

R24100kΩJ2

-2J2

-3J2

-4J2

-5J2

-6J2

-7

J2-8

J2-9

J2-1

0J2

-11

J2-1

2J2

-13

J2-1

4J2

-15

J2-1

6J2

-17

J2-1

8J2

-19

J2-2

0J2

-21

J2-2

2J2

-23

J2–2

4

J2-2

5J2

-26

J2-2

7J2

-28

J2-2

9J2

-30

J2-3

1J2

-32

J2-3

3

J4-2

J4-1

1J4

-12

J4-1

3J4

-14

J4-1

5J4

-16

J4-1

7J4

-18

J4-1

9J4

-20

J4-1

J2-3

4J2

-35

J2-3

6J2

-37

J2-3

8J2

-39

J2-4

0J2

-41

J3-1

J3-2

J3-3

J3-4

J3-5

J3-6

J3-7

J3-8

J3-9

J3-1

0J3

-11

J3-1

2J3

-13

J3-1

4J3

-15

J3-1

6J3

-17

J3-1

8J3

-19

J3-2

0J3

-21

J3-2

2J3

-23

J3-2

4

J2-1

J2–4

2

VDD

IO

VDD

IOA

VDD

AVD

D

VDD

IO

VDD

IO

VDD

IO

AVD

D

AVD

D

AVD

D

VDD

IO

AVD

D

VDD

IO

DG

ND

AVD

DVD

DIO

AD13AD12AD11AD10

AD8

AD7AD6

AD

14

AD0AD1AD2AD3

AD4AD5

WSRS

MS0

AVD

D

AVD

D

AD9

VDD

IO

AE

VDD

IO

VDD

IO

BLE

BHE

AVD

DA

GN

DVR

EFD

AC

REF

AD

C0

AD

C1

AD

C2

AD

C3

AD

C4

AD

C5

AD

C6

AD

C7

AD

C8

AD

C9

AD

C10

AD

C11

DIF

FVO

CM

DA

C0

DA

C1

DA

C2

DA

C3

AD

CN

EGA

GN

D

DG

ND

DG

ND

AD

15

MS1

Figure 5. Evaluation Board Schematic



0503

2-00

5

Figure 6. Evaluation Board Silkscreen



BILL OF MATERIALS Table 5. Component Qty Part Description Order No. Mfg. ADuC7026 Evaluation Board, Revision B2

1 PCB-1 2-sided, surface-mount PCB Analog Devices

PCB Standoff 4 Standoff Stick-on mounting feet 148-922 Farnell U1 1 ADuC7026 MicroConverter (80-lead LQFP) ADuC7026CP Analog Devices U2 1 ADR291 Band gap reference ADR291ER Analog Devices U3 1 AD8132 Differential op amp AD8132ARM Analog Devices U4 1 AD8606 Dual op amp, (8-pin SOIC) AD8606AR Analog Devices U5 1 ADP3333 Fixed 3.3 V linear voltage regulator ADP3333ARM3.3 Analog Devices U6 0 AT29LV1024 64 k × 16 flash AT29LV1024 Not populated U7 0 74LVT16373ADGG 16-bit D-latch 74LVT16373ADGG Not populated U8 0 CY7C1020CV33-12 32 k × 16 static RAM CY7C1020CV33-12 Not populated Y1 1 32.768 kHz Watch crystal 971-3220 Farnell S1 1 SW\8DIP 8-way DIP switch GH7242-ND DigiKey S2, S3, S4 3 Push-button switch PCB-mounted push-button switch 177-807 Farnell D1, D2, D3 3 LED 1.8 mm miniature LED 359-9954 Farnell D4 1 PRLL4002 Diode BAV103TPMSCT-ND DigiKey C1, C5, C13, C15, C18, C22, C23

7 10 µF Surface-mount tantalum capacitor, Taj-B case 197-130 Farnell

C2 to C4, C6, C12, C14, C16, C17, C24

10 0.1 µF Surface-mount ceramic capacitor, 0603 case 317-287 Farnell

C7, C8 2 22 pF Surface-mount ceramic capacitor, 0603 case 722-005 Farnell C9, C10 2 10 nF Surface-mount ceramic capacitor, 0603 case 301-9561 Farnell C11, C19 2 470 nF Surface-mount ceramic capacitor, 0603 case 318-8851 Farnell C20, C21 2 12 pF Surface-mount ceramic capacitor, 0603 case 721-979 Farnell R1 1 10 kΩ

potentiometer 0.25W, 4 series, (4 mm × 4 mm square) TS53YJ 10K 20% TR

(lead free) Vishay

R2 1 100 Ω Surface-mount resistor, 0603 case 933-2375 Farnell R3 1 200 Ω Surface-mount resistor, 0603 case 933-2758 Farnell R4 1 49.9 Ω Surface-mount resistor, 0805 case 311-49.9HRCT-ND DigiKey R5, R6, R8, R9 4 348 Ω Surface-mount resistor, 0603 case 311-348HRCT-ND DigiKey R7 1 24.9 Ω Surface-mount resistor, 0805 case 311-24.9HRCT-ND DigiKey R10, R11 2 60.4 Ω Surface-mount resistor, 0805 case 311-60.4HRCT-ND DigiKey R12, R18, R20 3 270 Ω Surface-mount resistor, 0603 case 933-0917 Farnell R13, R14, R23 3 0 Ω Surface-mount resistor, 0603 case 933-1662 Farnell R15, R16, R17 3 1 kΩ Surface-mount resistor, 0603 case 933-0380 Farnell R19 1 1.5 Ω Surface-mount resistor, 0603 case 9331832 Farnell R21, R22, R24 3 100 kΩ Surface-mount resistor, 0603 case 933-0402 Farnell L1 1 Ferrite bead Surface-mount inductor, 1206 case 952-6862 Farnell J1 1 4-pin header 4-pin, 90º single-row header TSM-104-02-T-SH Samtec J2 1 42-pin header 42-pin, straight single-row header TSM-121-01-T-DV Samtec J3 1 42-pin header 24-pin, straight single-row header TSM-124-01-T-SV Samtec J4 1 20-pin header 20-pin, connector HTST-110-01-L-DV Samtec J5 1 Power socket PCB mounted socket (2 mm pin diameter) KLD-SMT2-0202-A Kycon










http://www.analog.com/adp3333?doc=EVAL-ADuC7026_UG-669.pdf

http://www.analog.com/adp3333?doc=EVAL-ADuC7026_UG-669.pdf



NOTES



NOTES



NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2004–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG05032-0-2/14(B)

Documents

Evaluating the ADuC7026 MicroConverter - Analog Devices · 2017. 2. 15. · To enter serial download mode, the user must pull the P0.0/BM pin low while reset is toggled. On the evaluation