Ethernet Switch Chip Specification - fujitsu.com€¦ · Confidential MB87Q3141 Chip Speciﬁcation Overview This speciﬁcation describes the 3rd generation Fujitsu 10Gbps Ethernet

MB87Q3141Chip Specification

Confidential

Overview

This specification describes the 3rd generation Fujitsu 10Gbps Ethernet switch chip, MB87Q3141-F. This chip supports twelve 10Gigabit ports which operate at wire speed with enhanced XAUI interfaces. The enhanced XAUI interface supports XAUI (802.3ae) and 10GBASE-CX4 (802.3ak), and enables up to 25m interconnection with copper cables and over 1m backplane interconnection. The switch chip has a large shared packet memory inside using our Stream memory technology. The memory realizes multi-port memory using conventional high-density memories as a solution for the memory bandwidth bottleneck in a shared memory switch and provides enough bandwidth required for high performance switch. This chip also has several features such as Jumbo frame support, cut-through and priority queues to achieve higher performance in cluster applications.

Chip Specification

Copyright © 2001, 2002, 2003, 2004, 2005 Fujitsu Laboratories of America, Inc. All rights reserved.

This document contains confidential information and trade secrets of Fujitsu Laboratories of America, Inc. which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission of Fujitsu Laboratories of America, Inc. Use of copyright notice is precautionary and does not imply publication or intent thereof.

All information contained in this document is subject to change without notice. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness.

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Table of ContentsChapter 1: Introduction .........................................................................................................................................................1

1.1 General Description ..................................................................................................................................................11.2 Features ..................................................................................................................................................................11.3 Enhanced XAUI Interface ..........................................................................................................................................31.4 Multi-port Stream Memory........................................................................................................................................41.5 Credit-based Buffer Management for Stream Memory ....................................................................................................51.6 High-performance features for Cluster Application........................................................................................................61.7 Multiple Chip Configuration for Cluster Application.....................................................................................................7

Chapter 2: Functional Description...........................................................................................................................................92.1 Frame Format..........................................................................................................................................................92.2 Input Port ...............................................................................................................................................................92.3 Central Switching Structure..................................................................................................................................... 102.4 Output Port........................................................................................................................................................... 142.5 EEPROM Interface ................................................................................................................................................. 152.6 Processor Interface.................................................................................................................................................. 162.7 Auxiliary Register Interface...................................................................................................................................... 192.8 Initialization.......................................................................................................................................................... 20

Chapter 3: Network Management .......................................................................................................................................... 213.1 Introduction .......................................................................................................................................................... 213.2 Management Packet Handler.................................................................................................................................... 213.3 Management Information Base (MIB) Counters .......................................................................................................... 24

Chapter 4: Register Description ............................................................................................................................................ 274.1 Notation ............................................................................................................................................................... 274.2 Address Map .......................................................................................................................................................... 284.3 Device Level Registers ............................................................................................................................................. 344.4 Processor Buffer Registers...................................................................................................................................... 1134.5 Per Port Registers ................................................................................................................................................ 1154.6 PHY Registers...................................................................................................................................................... 155

Chapter 5: Error Handling ................................................................................................................................................. 1795.1 Introduction ........................................................................................................................................................ 1795.2 Input Errors ........................................................................................................................................................ 1795.3 Bridge Errors....................................................................................................................................................... 1805.4 Output Errors ...................................................................................................................................................... 1805.5 Hardware Errors .................................................................................................................................................. 1805.6 Software Errors.................................................................................................................................................... 181

Chapter 6: IO Signals ......................................................................................................................................................... 1836.1 External Pins ....................................................................................................................................................... 183

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Chip Specification

Chapter 7: Mechanical Description.......................................................................................................................................1897.1 Dimensions ..........................................................................................................................................................1897.2 Pin Organization ..................................................................................................................................................1907.3 Pin Listing...........................................................................................................................................................191

Chapter 8: Electrical Description .........................................................................................................................................1958.1 Absolute Maximum Ratings....................................................................................................................................1958.2 Recommended Operating Conditions .......................................................................................................................1958.3 3.3V Tolerant 2.5V CMOS Electrical Specifications ................................................................................................1968.4 Reference Clock Input (LVDS) Electrical Specifications ..........................................................................................1968.5 Non-XAUI (2.5V CMOS) Electrical Specifications ....................................................................................................1978.6 Enhanced-XAUI Electrical Specifications ..............................................................................................................1978.7 Power Dissipation.................................................................................................................................................1988.8 Reset Sequence......................................................................................................................................................198

Chapter 9: Appendix ..........................................................................................................................................................1999.1 Supported Frame Formats .....................................................................................................................................1999.2 VLAN ID Routing ................................................................................................................................................201

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MB87Q3141

Chapter 1: Introduction

1.1 General DescriptionThis specification describes the 3rd generation Fujitsu 10Gbps Ethernet switch chip, MB87Q3141-F. This chip supports twelve 10Gigabit ports which operate at wire speed with enhanced XAUI interfaces. The enhanced XAUI interface supports XAUI (802.3ae) and 10GBASE-CX4 (802.3ak), and enables up to 25m interconnection with copper cables and over 1m backplane interconnection. The switch chip has a large shared packet memory inside using our Stream memory technology. The memory realizes multi-port memory using conventional high-density memories as a solution for the memory bandwidth bottleneck in a shared memory switch and provides enough bandwidth required for high performance switch. This chip also has several features such as Jumbo frame support, cut-through and priority queues to achieve higher performance in cluster applications. Figure 1-1 shows the block diagram of the switch and switch core.

1.2 FeaturesThe switch chip has following features:

Twelve 10Gigabit ports switching operation at wire speed 240Gbps aggregate throughput Integrated SerDes and enhanced XAUI Interface Support XAUI and 10GBASE-CX4 On-chip Multi-port Stream Memory and buffer management Cut-through, Priority queues and Jumbo Frame support for

high-performance cluster Jumbo frame (Max. 15KB) for 10Gigabit port up to 4 Priority queues Pin-to-pin switching latency of 450nS (including SerDes and

enhanced XAUI Interface)

Link aggregation (802.3 clause 43) IGMP and MLD snooping Diffserv for IPv4 and IPv6 Deficit Round Robin (DRR) for fair bandwidth sharing Shaper (CIR: Committed Information Rate) Meter (PIR: Peak Information Rate) Port Security (Filtering based on Source MAC address) Early Detection to avoid blocking WAN PHY support Multiple chip configuration for cluster application L2 unicast forwarding, address learning and aging L2 multicast forwarding using GMRP L2 lookup table with 8K MAC address 802.1Q VLAN VLAN table with 4K VLAN address User-programmable VLAN Tag Protocol Type 802.1Q(802.1s) Multiple Spanning Tree 802.3ae Full-duplex operation using PAUSE flow control RMON and SMON statistics counters sFlow (RFC3176) support EEPROM Interface for initialization Processor Interface for housekeeping Burst support for MPC8260 External NP support Jumbo frame (Max. 4KB) for processor interface 0.11um CMOS Technology

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Chip Specification

Figure 1-1. Block Diagram

Crossbar Switch CoreBIST/

Management

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

Crossbar Switch CoreBIST/Management

XAUIPortXAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

Shared Memory

0

1

2

10

11

0

1

2

10

11

InputLogic

Input Buffer

Output Logic

(a) Switch global view

(b) Switch Core

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

XAUIPort

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MB87Q3141

1.3 Enhanced XAUI InterfaceThe XAUI Interface is designed as an extender of XGMII Interface for 10Gigabit Ethernet but its max. length is limited to 50cm. Beyond this distance, optical fibers are required. The switch

integrates SerDes and provides enhanced XAUI Interfaces which extend the length up to 25m with copper cables. With this enhanced XAUI interface, board to board interconnection becomes easier and a large system can be constructed without optical fibers (Figure 1-2).

Figure 1-2. Conventional XAUI and Enhanced XAUI

XAUI - XGMII Transceiver

Physical

Medium Chip

XAUI

Optical Fiber10Gb/s

XAUI: 10Gbit Attachment Unit Interface

10Gbit Ethernet Switch Chip

.... ....XGMII

3.125Gbps differential x4 channels per dir

312.5Mbps differentialx36 bits per dir

Max. 50cm

Max. 7cm

XGMII: 10Gbit Media Independent Interface

10Gbit Ethernet Switch Chip

Enhanced XAUI

3.125Gbps differential x4 channels per dir

Max. 25m

(a) Conventional XAUI

(b) Enhanced XAUI


Chip Specification

1.4 Multi-port Stream MemoryFor a switch on a chip, a large capacity of packet memory needs to be integrated inside and the memory is desired to be used effectively. A shared memory is desired from the point of effective usage of memory, however it is difficult to scale to multiple 10 Gigabit Ethernet switching because it requires extremely high memory bandwidth. For example, twelve 10 Gigabit Ethernet switching at wire speed requires 15GB/s read bandwidth and 15GB/s write bandwidth. If we assume 312.5Mhz core frequency, the width of the

1RW memory is 768bits to achieve the required bandwidth. This memory width is much longer than the minimum inter-packet gap and a wire speed switching is not possible. To solve this problem, a specific memory, called Stream Memory, is designed. The Stream Memory realizes a high bandwidth and large capacity 12R12W shared memory optimized for a stream data processing using conventional high-density 1RW memories of 64bit wide and enables switching operation at wire speed. Figure 1-3 shows Stream Memory architecture using a multi-stage interconnection network.

Figure 1-3. Stream Memory Architecture

InputBufferIOInputBufferIO



InputBuffer

IO InputBuffer

IO

InputBuffer

IO InputBuffer

IO

InputBuffer

IO InputBuffer

IO

InputBuffer IOInputBuffer IO



InputBuffer

IOInputBuffer

IO

InputBuffer

IOInputBuffer

IO

InputBuffer

IOInputBuffer

IOManagement

Unit

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Memory Bank

Multi -PortTag Memory

(& Center Agent)

Memory Bank

Memory Bank


MB87Q3141

1.5 Credit-based Buffer Management for Stream MemoryThe Stream Memory is managed by credit-based flow control inside chip. Each port has dedicated credits in the shared buffer and it is used for flow control between input buffer and shared buffer or Stream Memory shown in Figure 1-4. IEEE Standard 802.3ae-

defined PAUSE is used for flow control between external and the input buffer. Using credit-based flow control, cut-through operation is done as a default for better performance. Also the shared buffer pool provides flexible buffer allocation depends upon the traffic load of each port. Input Buffer is a temporal buffer to absorb packets when the credit is not available and PAUSE is not effective due to round trip delay. See “Cut-through forwarding” on page 6. also.

Figure 1-4. Credit-based buffer management

SharedBufferPool

Credit

(exported)

Credit

(exported)

InputBuffer

InputBuffer Destination

Credit-based Flow Control

PAUSE Flow Control

Credit

(exported)InputBuffer


Chip Specification

1.6 High-performance features for Cluster ApplicationThe switch chip is designed for a high-performance cluster application in mind. The three major criteria of cluster performances are:

1. Sustained data rate for large messages

2. Latency for short messages

3. Host-CPU utilization per message

The criteria 1 and 2 are closely related to a switch design. The switch chip improved them by providing the following features.

• Jumbo Frame Support

• Cut-through forwarding

• Priority queues

1.6.1 Jumbo Frame SupportAlthough the maximum packet size is 1.5K Bytes for IEEE Ethernet standard, the switch supports 15K Bytes Jumbo frame for better performance in cluster application and it is designed to provide sustained through-put for Jumbo frames at wire speed.

1.6.2 Cut-through forwardingIn order to achieve shorter latency, the switch operates in Cut-through mode as a default. In this mode, an incoming packet is forwarded to output ports as soon as possible without waiting for the entire packet is received. The Cut-through forwarding would significantly reduce latency compared to a store-and-forwarding.Also it would increase reusability of memory blocks reducing the lifetime.

1.6.3 Priority QueuesShort latency is desired for small messages while sustained data rate is required for large messages. Therefore the switch provides separate priority queues for small and large messages. To assign priorities, the switch uses Type Of Service (TOS) field in IPv4 and Traffic Class field in IPv6 which defines differentiated services in DiffServ. If Diffserv is not enabled, the priority will be determined based on priority value in VLAN tag. In the case of neither DiffServ nor VLAN enabled, default priority for the best effort will be used.


MB87Q3141

1.7 Multiple Chip Configuration for Cluster ApplicationMultiple switch chips are used to construct a large scale cluster system. For a cluster application, fat-tree topology is recommended rather than arbitrary topology because it has the following benefits:

• Achieve high bisection1bandwidth

• Preserve link count between upperlink and lower link

• Not require Spanning Tree Protocol

Figure 1-5 shows an example of a cluster configuration.

In a multiple chip configuration, following routing mechanism(s) can be used.

• MAC Address Routing

• VLAN ID Routing

• Uplink Filter Routing

• Outbound Tag Routing

Figure 1-5. Example: 72-node Cluster Configuration

1.7.1 MAC Address RoutingMAC Address Routing is a routing mechanism which is normally used in a Ethernet switch. MB87Q3141-F has a MAC Address Table and compares MAC address in the table with Destination MAC Address in the incoming frame and make forwarding decision of the frame. MAC Address in the Table can be Static or Dynamic. Static MAC Address is learned by CPU and is not aged out by Hardware. Dynamic Address is learned by Hardware based on Source MAC address in the incoming frame and is aged out by Hardware. When IVL (Independent VLAN Learning) is used, MAC Address is learned per VLAN. When SVL (Shard VLAN Learning) is used, MAC Address is learned common to all VLANs.

1.7.2 VLAN ID RoutingVLAN ID Routing is a routing mechanism which makes forwarding decision based on VLAN ID. CPU sets VLAN ID Table to specify the destination port for each VLAN ID. If MAC Address Table is not hit, the frame is forwarded based on settings in the VLAN Table. This routing mechanism assumes Dynamic learning is disabled.

1.7.3 Uplink Filter RoutingUplink Filter Routing is a routing mechanism which makes forwarding decision based on the source port of the incoming frame. The uplink filter is defined for each source port at the output port. Uplink filter is only applied to broadcast, multicast, or flooded frames to avoid duplicated frames when there are multiple paths between end stations. If the frame is not dropped by Uplink Filter, the frame is forwarded to the output port.

1. bisection is the minimum number of links that separates the network into two halves

6 nodes

switch switch switch switch switch switch switch switch switch switch switchswitch

switch switch switch switch switch switch


Chip Specification

1.7.4 Outbound Tag RoutingOutbound Tag Routing is a routing mechanism which makes forwarding decision based on the proprietary Tag attached to the Ethernet frame. The proprietary Tag includes Group ID, Chip ID and Port ID in the network. Outbound Tag Registers are a dedicated routing table for Outbound-tagged frames and needs to be initialized appropriately.

1.7.5 Link AggregationMB87Q3141-F support Link Aggregation (802.3 clause 43) for increased bandwidth and availability. See “Link Aggregation” on page 13 also.

1.7.6 EEPROM Initialization and Auxiliary Register InerfaceMB87Q3141-F can be initialized by EEPROM therefore it operates with or without CPU. This allows denser implementations of a switch board. When there is no CPU attached, Auxiliary Register Interface can be used to access registers after initialization by EEPROM.


MB87Q3141

Chapter 2: Functional Description

2.1 Frame FormatThe switch chip supports standard Ethernet frames with lengths between 64bytes to 1518bytes(no VLAN), 1522bytes(VLAN) or 1526bytes(User VLAN Tag) and Jumbo frames with 15Kbytes. The frames less than 64bytes and longer than 15Kbytes are dropped at the input port. The minimum IPG is assumed to be 96bit IDLE plus 64bit preamble. The packets with shorter IPG are not dropped but the wire speed switching is not guaranteed. The supported frame formats are shown in the Appendix.

2.2 Input PortEach input port consists of the High speed IO Receiver, Media Access Control (MAC) Receiver and Input Control blocks as shown in Figure 2-1. The High speed IO Receiver performs following IEEE 802.3ae compliant functions:

Physical Interface to enhanced XAUI (PHY) Receiver equalization Deserialization Comma Align, 8B/10B Decoder, Lane Deskew XGMII Interface to Media Access Control

Figure 2-1. Input Port

The MAC Receiver performs following IEEE 802.3ae compliant functions:

XGMII Interface to the High speed block Receive PAUSE flow control packet and request the MAC

Transmitter to stop sending a new packet Frame Check Sequence validation Station MAC address matching to detect a management

packet designating the switch Statistics counters for network management Link fault detection

The Input Control performs following protocol dependent and independent functions:

[Protocol Dependent Functions]

Simple proprietary interface to the MAC Receiver

Filtering frames based on the Acceptable Frame Type Assign the priority based on TOS field (IPv4) / Traffic Class

(IPv6) field in the packet. Storing the packet temporarily into the Input Buffer Request to generate PAUSE flow control packet to the MAC

Transmitter if necessary

[Protocol Independent Functions]

Maintaining the credit for the flow control between the Stream Memory and the Input Control

Maintaining the free list of the blocks which are assigned to the port

Checking the credit and store the packet data into the Stream Memory based on the free list if the credit is available

Generating a forwarding request to the Central Agent for routing.

High speed IO Media Access Control

(MAC) Receiver block

Input Control Block

Input Buffer

enhanced XAUI XGMII Proprietary Interface

enhanced XAUI: enhanced 10Gbit Attachment Unit Interface


Receiver block


Chip Specification

2.3 Central Switching StructureFigure 2-2 shows the central switching structure for packet buffering and switching. The structure consists of the Multi-port Stream Memory, TAG Memory and the Central Agent. The packet data is stored in the Stream Memory by the Input Control and read from it by the Output Control for an outgoing packet. The control information which shows the next block storing the packet is stored in the TAG Memory.

The Central Agent performs the following protocol independent and dependent functions:


Maintains the free list of the blocks which belongs to the buffer pool

Supply blocks to the input ports from the buffer pool using Dynamic Thresholding

Accept returned blocks from the output ports Counting the returned blocks for the multicast Generating a request to the Output Control


MAC Address Table and VLAN Table Lookup VLAN Ingress Check VLAN Egress Filter Filtering frames based on port states Port Security (Source Address based filtering) Link Aggregation IGMP/MLD Snooping

.

Figure 2-2. Central Switching Structure

TAG Memory

Multi-port Stream Memory

Central Agent

Input Port 0

Input Port 1

... ...

Input Port 0Input Port 1

...

Input Port 0

Input Port 1

...

Output Port 0

Output Port 1

Output Port 0Output Port 1

...

Output Port 0Output Port 1

...

MAC Address Table / VLAN Table

(Data Storage)

(Control Storage)


MB87Q3141
2.3.1 Multicast MechanismMB87Q3141-F chip uses the logical multicast to utilize the packet memory, or Stream Memory efficiently. After MAC Address Table lookup, the address pointer is replicated and put into designated output queues. Each output port load the packet from Stream Memory in parallel and send it to the link.
2.3.2 IP Multicast SnoopingTo avoid unnecessary traffic in IP Multicast, MB87Q3141-F supports following standard protocols:

Internet Group Management Protocol (IGMP) for IPv4. Multicast Lister Discovery (MLD) for IPv6.

If an incoming frames is Query or Report of membership for IP Multicast, a copy of the frame is forwarded to CPU which sets MAC Address Table and destination ports for the MAC address.

2.3.3 MAC Address TableEthernet protocol uses MAC Address for routing frames. MAC Addresses are stored in the MAC Address Table in the Central Switching Structure. MB87Q3141-F has 8-way set-associative routing table that is 8K entry in total. In addition to this, it has 16-entry full set-associative routing table. Figure 2-3 shows MAC Address Table format.

Figure 2-3. MAC Address Table

Lookup, Learning, Aging are the three processes which are performed on MAC address table for routing.

1. A learning process creates and updates table entries (Dynamic address learning by On Chip Hardware, Static address learn-ing by Processor).

2. A lookup process examines table entries for forwarding deci-sion (On Chip Hardware)

3. Aging process removes stale entries from the table on a regular basis (On Chip Hardware)

The table search algorithm is hash-based, with MAC address as input to create table index using CRC when SVL is used. MAC address and VLAN ID are input when IVL is used. The static entries are programmed by the Processor and not learned and not aged out.

For dynamic entries, the chip learns source address in the incoming frames from 10G ports and stores them in MAC address table. If the source address already learned and port vector matches, the time stamp is updated. If port vector does not match, no further action is taken.

The chip looks up entries in the table using hash-based search for the destination address to determine the output port to forward the packet. If the destination address is not found, the frame will be flooded to all the ports that are member of the VLAN other than the incoming port.

MB87Q3141-F also supports Port Security feature. When Port security feature is enabled at the source port. the chip also looks up entries in the table using hash-based search for the source address if it is already learned in the MAC Address Table. If the source address

01102383

MAC Address

bit 0 Valid

Port bit 1 Static

bit[10:2] Time Stamp

bit[35:24] VLAN ID

bit[83:36] MAC address

EDC VLANIdVector

Time S VStamp

bit[91:84] EDC

bit[23:11] Port Vector

3591

bit 23 Processor Port

bit 22 Port 11 ...bit 11 Port 08k+16

Entries


Chip Specification
is not found, the frame is forwarded to Processor for further decision and processing. Processor may add the MAC Address in the MAC Address Table if it is ok. Processor may completely shut down the port if it is necessary for security reasons.
Switch chip does aging process to check the stale entries in the table and remove them. If an entry is valid and not updated for a specified time, the aging process clears the valid bit for that entry.

Switch chip provides the table access mechanism for Software on Processor to search, learn or delete an entry in the MAC address table.

Error Protection: EDC

2.3.4 VLAN Table MB87Q3141-F supports Virtual LAN (VLAN) which is defined in IEEE standard 802.1Q. Figure 2-4 shows VLAN table format. The table contains Valid bit, Port state for Multiple Spanning Tree Protocol, USE for VLAN membership, and TAG for VLAN Tagging of outgoing frame and ECC. VLAN ID is used as an index for the table entries.

Figure 2-4. VLAN Table

Port state in the VLAN table is used when Multiple Spanning Tree Protocol is enabled because the port state is supposed to be VLAN dependent. If Multiple Spanning Tree is not enabled, Port state in the Port Configuration register is used.

Lookup, Learning are the two processes which are performed on VLAN table for routing.

1. A lookup process examines VLAN entries for routing. The flooding frames are sent to the ports which belong to the same VLAN (On Chip Hardware)

2. A learning process creates and updates table entries which define VLAN associations between VLAN ID and the member-ship (by Processor).

Error Protection: ECC

USETAG

3750

4kVLAN

Entries

0

ECC V

5157bit 0 Valid

bit[37:25] USE

bit[50:38] TAG

bit[57:51] ECC

24

bit[24:1] Port State

Port State: 2bits per 10G port, bit[24:23] for Port11,..bit[[2:1] for Port0

00: Disable

01: Blocking and Listening

10: Learning

11: Forwarding

USE: bit[37] for Processor Port, bit[36] for Port11,..bit[25] for Port0

0: Not in USE

1: In USE

TAG: bit[50] for Processor Port, bit[49] for Port11,..bit[38] for Port0

0: No Tagging

1: Tagging

Port State


MB87Q3141
2.3.5 Reserved Multicast AddressFollowing Multicast addresses are reserved for special use, for example, STP, GVRP, GMRP, PAUSE, etc.
01-80-c2-00-00-00 to 01-80-c2-00-00-10 01-80-c2-00-00-20 to 01-80-c2-00-00-2f

In the default configuration, MB87Q3141-F chip handles frames with these reserved multicast addresses as follows:

Packet received on 10G ports- If Processor is attached, forward to Processor- If no Processor is attached, lookup MAC address and VLAN tables and make forwarding decision

Packet received on Processor port- Lookup MAC address and VLAN tables and make forward-ing decision

MB87Q3141-F also an additional BPDU handling feature to support Provider VLAN (P802.1ad). Using this feature, some BPDU can be transferred as it is between customer peer while other BPDU is terminated by the provider bridge.

2.3.6 Link AggregationMB87Q3141-F support Link Aggregation (802.3 clause 43) for increased bandwidth and availability. Link Aggregation allows one or more links to be aggregated together to form a Link Aggregation Group (LAG) as if it were a single link. Based on a Distribution algorithm selected, all frames of a given conversation are forwarded to a single port. Distribution algorithm is based on either of DA, SA, DA/SA or Reception port. In addition, a tuning mechanism is supported for better load balancing if the number of end stations is small. When a link failure happens in LAG, the conversation can be moved to another link in the LAG.


Chip Specification
2.4 Output PortEach output port consists of the Output Control, Media Access Control (MAC) Transmitter and the High speed IO Transmitter blocks as shown in Figure 2-5.
The Output Control performs following protocol independent and protocol dependent functions:


Accepting an output request from the Central Agent and puts the request in the output queues

Arbitrating output requests in the output queues

Sharing the bandwidth fairly using Deficit Round Robin (DRR)

Loading the packet data from the Stream Memory Returning a block to the Central Agent if the data in the block

is loaded


Filtering frames based on VLAN egress rules Output the packet data to the MAC Transmitter Simple proprietary interface to the MAC Transmitter

Figure 2-5. Output Port

The MAC Transmitter performs following IEEE 802.3ae compliant functions:

XGMII Interface to the high speed block including PHY register access

Generate PAUSE flow control packet by a request from the Input Control

Stop sending a new packet by a request from the MAC receiver Frame Check Sequence generation and insertion Statistics counters for network management Link fault signaling WAN-PHY (OC-192) data rate control

The High speed IO Transmitter performs following IEEE 802.3ae compliant functions:

XGMII Interface to Media Access Control 8B/10B Encoder Serialization Transmitter equalization enhanced XAUI (PHY) to physical Interface

2.4.1 SchedulingThe codepoint is mapped to a priority using the Priority Mapping Register. The Strict Priority is used for arbitration between 4 priorities. DRR is used for arbitration among 13 output queues of the same priority if enabled. The Simple Round Robin is used if disabled. It is possible turn off DRR on priority basis by setting 0 to the corresponding quantum value in DRR Control register. The scheduling is done on packet level.

Media Access Control

(MAC) Transmitter

Output Control Block

enhanced XAUIXGMIIProprietary Interface

enhanced XAUI: enhamced 10Gbit Attachment Unit Interface


High speed IO

blockTransmitter block

Output Queues


MB87Q3141
2.5 EEPROM InterfaceThe EEPROM Interface is provided for the configuration and initialization of the switch as an option. If there is no EEPROM, the switch is configured and initialized through Processor Interface or Auxiliary Register Interface.
Figure 2-6 shows the data formats of the EEPROM of 8bit wide. The EEPROM Interface loads the data based on these formats and writes them into the registers or tables. This procedure repeats until the End of Data is detected. The packet size for Table Data is equal or greater than 8 and depends on the table entry size.

Note that the slave address of EEPROM device is fixed to 1010000b.

Figure 2-6. EEPROM Data Formats

ex. to write 01020304h into

07h10h00h

00h

04h03h02h01h

Priority Mapping Register (0010h)

‘00000111’ (Byte length)

Address[7:2] ‘00’

Address[15:8]

Data[7:0]

7 00

1

2

Data[15:8]

Data[23:16]

Data[31:24]

3

4

5

6

‘00001000’ (Byte length)

‘0’ TableId[2:0] ‘0011’

Entry[7:0]

Entry[15:8]

7 00

1

2

Data[15:8]

Data[23:16]

Data[31:24]

3

4

5

6

‘00000000’ (End of Data)7 0

0

7

Data[7:0]

Register Data Table Data (minimum) End of Data


Chip Specification
2.6 Processor InterfaceThe processor interface is provided for the configuration and initialization of the switch and the processing of the management packets.
The management packets to be processed by processor are as follows:

BPDU for the spanning tree protocol GVRP for the virtual LAN

GMRP for the Layer 2 multicast ICMP for the switch control such as ping SNMP for the network management such as statistics

monitoring and switch reset

2.6.1 Signal Block Diagram Figure 2-7 shows the signal block diagram of the Switch and External Processor Interface when External Processor is MPC860.

Figure 2-7. Signal Block Diagram (MPC860)

MPC860 SWITCH

D[0:31]

A[16:29]

TSIZ[0:1]

DP[0:3]

*TS

RD/*WR

*TA

*BI

*TEA

XB_PER_DATA[31:0]

XI_PER_ADDR[15:2]

XB_PER_DP[3:0]

XI_PER_ICTRL[2]

XI_PER_ICTRL[1]

XO_PER_OCTRL[0]

XO_PER_OCTRL[1]

XI_PER_ICTRL[0]

XO_PER_IRQ_N[2:0]

XI_PER_CLK

XI_PER_RESET_N

*IRQ[0:2]

*CS[X] XI_PER_CS_N

CLKOUT

*HRESET

XI_PER_TSIZ[1:0]


MB87Q3141
Figure 2-8 shows the signal block diagram of the Switch and External Processor Interface when External Processor is MPC8260.
Figure 2-8. Signal Block Diagram (MPC8260)

Switch chip communicates with external processor for initialization, handling management protocols, transferring frames, performing MAC address Table, VLAN Table updates and support network management functions.

Switch chip employs interrupt signal to report event when certain jobs are finished or some hardware error has occurred. Upon

receiving such an interrupt, the processor can access the interrupt vector register to identify the source causing the interrupt and then respond accordingly. On the other hand, an interrupt mask register is provided for the Processor to mask any unwanted interrupt event when they are non fatal. Polling for management packets arrival on inbound buffers is also an functional option.

MPC8260 SWITCH

D[0:31]

DP[0:3]

A[16:29]

*CS[x]

*CS[y]

TSIZ[2:3]

PGPL2

XB_PER_DATA[31:0]

XB_PER_DP[3:0]

XI_PER_ADDR[15:2]

XI_PER_CS_N

XI_PER_ICTRL[4]

XI_PER_TSIZ[1:0]

XI_PER_ICTRL[3]

*IRQ[0-2]

*HRESET

XI_PER_IRQ_N[2:0]

XI_PER_RESET_N


Chip Specification
2.6.2 Processor BlockFigure 2-9 shows the block diagram of the Processor Block. The Processor Block will be communicating between the switch core and the external processor.
Figure 2-9. Processor Block

The Processor Block consists of

1. Inbound Registers are used to store management packet from processor and transfer it to stream memory in switch chip.

2. Outbound Registers are used to store management packet to be transferred from switch chips stream memory to processor.

3. Control and Access Internal Registers submodule generates control signals for the data transfer from internal registers and other control signals required for processor interface.

ControlFor

AccessInternalRegister

Control &Internal

Registers

From switchcore

To switchcore

OutboundBuffer

Register

InboundBuffer

Register

Processor block

Processor interface


MB87Q3141
2.7 Auxiliary Register InterfaceThe auxiliary register interface (or I2C interface) is also provided to access registers in the switch. The address space of switch registers is 16-bit so that it uses indirect 16-bit addressing by sending two 8-bit
data first to read or write the registers. Figure 2-10 shows Auxiliary Register Interface Data Format. Note that once the address is set by read or write access, it’s not necessary for the following read accesses to the same address to set read address again.

.

Figure 2-10. Auxiliary Register Interface Data Format

STA

RT

DEV SEL ADDR[7:0] ADDR[15:8]

STO

P

R/W

AC

K

AC

K

AC

K

2 Byte Write Set read address.

6 Byte Write Write 32 bit data to the specified 16 bit address.

STA

RT

DEV SEL ADDR[7:0] ADDR[15:8]

R/W

AC

K

AC

K

AC

K

AC

K

DATA[7:0]

DATA[15:8] DATA[23:16] DATA[31:24]

4 Byte Read Retrieve read data.

DEV SEL DATA[7:0] DATA[15:8] DATA[23:16] DATA[31:24]

DEV SEL is 1010xxxb where lower 3 bits is defined by XI_CONFIG[6:4].

STO

P

AC

K

AC

K

AC

K

STA

RT

R/W

AC

K

AC

K

AC

K

AC

K

NA

CK

STO

P


Chip Specification
2.8 InitializationThe initialization is a three step processes.
1. Hardware Initialization

2. Load Initialization by EEPROM or Processor based on the configuration

3. Port State Initialization using Spanning Tree Protocol (optional)

The hardware initialization includes the followings:

Internal registersThe all internal registers are initialized to their default values as defined in the Chapter 4.

TAG MemoryTAG Memory is initialized to store indices which shows the next blocks, that is, address 0 is initialized to 1, address 1 is initialized to 2, and so forth.

MAC address and VLAN TablesAll entries are initialized as invalid.

Built In Self Test(BIST)

The load initialization includes the followings:

Internal registersThe internal registers are initialized based on the configura-tion.

MAC address and VLAN TablesThe static entries are loaded and initialized as valid.

The port state initialization using Spanning Tree Protocol includes the followings:

Port statesThe port states can be programmed to be in the port states as required by the spanning tree protocol if this option is enabled.

Note: We will define sticky bits/registers if necessary.


MB87Q3141
Chapter 3: Network Management
3.1 IntroductionOur chip facilitates for collecting management information by using various statistical counters. These counters are accessed by the processor through register access mechanism. The counters support BRIDGE MIB, RMON MIB, SMON MIB, IF MIB, Etherlike MIB. Routine Network Management packet transactions are performed on processor interface between switch chip and processor. Management packet handler provides a mechanism for data transfer.

3.2 Management Packet HandlerFigure 3-11 shows the data flow through the switch for the processor interface. Incoming management packets to switch are forwarded to the external processor through the Processor block based on some criteria. As well as management packets can be forwarded from processor to switch port by following some routing rules.

Figure 3-11. Data flow through Switch for Processor Interface

IncomingFrame

Processor Block

Processor Interface

Outgoing Frame

Sync anddecoder

Switch Chip

Shared Memory

O/Pctrl I/ Pctrl

InternalRegisters


Chip Specification
3.2.1 Management Packet Flow-outbound pathFigure 3-12 shows the transactions involved in outbound data transfer.
Management packets are transmitted as follows:

0. Input packet arrival bound for processor.

1.a Notify packet arrival to processor.

1.b Transfer packet from stream memory to outbound registers.

2. Processor checks the status register for complete packet availability.

3. Packet is transferred from outbound buffers to processor.

4. Processor sends notification for transfer completed.

Figure 3-12. Outbound transactions

SWITCH

Pkt arrival

Check (status)

Pkt Transfer From streamMemory to Out boundBuffer registerThen update status register

Packet

Transfer

PROCESSOR

Notify

(Transfer completed)

3

0

1.a

2

Notify (pkt arrival)

1.b

4


MB87Q3141
3.2.2 Management Packet Flow-inbound pathFigure 3-13 shows the transactions involved in inbound data transfer
Management packets are received as follows:

1. Processor writes data into inbound buffers in the switch.

2. Processor notifies switch start and end address of the switch.

3. Switch will transfer the packet from inbound buffer to share memory.

4. Switch will notify the processor the end of transfer.

Figure 3-13. Inbound Transactions

SWITCH

Notify(start,end)

Setting upInboundBuffer

Packet TransferFrom InboundTo Shared Mem

Write Data

Notify(end of transfer)

PROCESSOR

1

2

3

4


Chip Specification
3.3 Management Information Base (MIB) CountersEthernet Switch Chip supports a number of MIB counters for network management. These MIB counters are updated based on data received and transmitted by MAC, Input Control, Output Control, MAC address Table, VLAN table and Processor Interface.
These counters are accessed by CPU periodically through the Processor Interface. All counter is defined as 32bit wide registers and actual counter width is specified in the following tables. For the counters with actual width less than 32 bits, unused upper bits are padded by 0.

Table 3-1. Transmit and Receive Counters (per port)

Name Width Description

TRC64 25 bits Transmit and Receive 64 Byte Frame Counter

TRC127 25 bits Transmit and Receive 65 to 127 Byte Frame Counter

TRC255 25 bits Transmit and Receive 128 to 255 Byte Frame Counter

TRC511 25 bits Transmit and Receive 256 to 511 Byte Frame Counters



TRMGVC 25 bits Transmit and Receive 1519 to 1522 Byte Good VLAN Frame CNT

Table 3-2. Receive Statistics Counters (per port)


RXBYTC 31 bits Number of Bytes received

RXPKTC 25 bits Number of Packets received

RXFCSC 25 bits Number of FCS errors received

RXMCAC 25 bits Number of Multicast packets

RXBCAC 25 bits Number of Broadcast packets received

RXCFC 16 bits Number of Control frames received

RXPFC 16 bits Number of Pause Frame packets received

RXUOC 16 bits Number of Unknown OP codes received

RXALNC 16 bits Number of Alignment Errors received

RXFLRC 25 bits Number of Frame Length Errors receiveda

RXCDEC 25 bits Number of Code Errors received

RXCSEC 16 bits Number of Carrier Sense Errors received

RXUNDC 16 bits Number of Undersize packets received

RXOVRC 25 bits Number of oversize packets received

RXFRGC 16 bits Number of Fragments received

RXJBRC 25 bits Number of Jabbers received

RXDRPC 25 bits Number of packets dropped

a. Length errors are not counted in VLAN Tagged frame.


MB87Q3141
Table 3-3. Transmit Statistics Counters (per port)

TXBYTC 31 bits Number of bytes transmitted

TXPKTC 25 bits Number of packets transmitted

TXMCAC 25 bits Number of Multicast packets transmitted

TXBCAC 25 bits Number of Broadcast packets transmitted

TXPFC 16 bits Number of PAUSE control frames transmitted

TXTOC 16 bits Number of packets dropped because of Lifetime

TXDRPC 25 bits Number of Dropped frames

TXJBRC 25 bits Number of Jabber frames

TXFCSC 25 bits Number of FCS errors

TXCFC 16 bits Number of Control frames

TXOVRC 25 bits Number of Oversize frames

TXUNDC 14 bits Number of Undersize frames

TXFRGC 14 bits Number of Fragments frames

Table 3-4. Flow Control Statistics Counters (per port)


FWpkts 29 bits Number of good frames that were forwarded as normal

FLDpkts 25 bits Number of good frames that were flooded due to an unknown destination

VLANDrops 25 bits Number of good frames that were dropped because of different VLANs for source/destination

FULLDrops 25 bits Number of good frames that were dropped because the Input Buffer is full

STMDrops 25 bits Number of good frames that were dropped because of the Storm Control

EDDrops 25 bits Number of good frames that were dropped because of the Early Detection Control

Table 3-5. VLAN Statistics Counters (per monitored VLANa)


VLANunicastPkts 29 bits Number of good unicast packets received on a designated VLAN

VLANunicastBytesL 32 bits Lower 32 bits of Number of bytes in good unicast packets received on a designated VLAN

VLANunicastBytesH 3 bits Upper 3 bits of Number of bytes in good unicast packets received on a designated VLAN

VLANMulticastPkts 29 bits Number of good Multicast packets received on a designated VLAN

VLANMulticastBytesL 32 bits Lower 32 bits of Number of bytes in good Multicast packets received on a designated VLAN

VLANMulticastBytesH 3 bits Upper 3 bits of Number of bytes in good Multicast packets received on a designated VLAN

a. up to 32 VLANs can be monitored, xxxByteL needs to be read before xxxByteH to guarantee correct 35 bit value


Chip Specification
Table 3-6. Priority Statistics Counters (per port)
3.3.1 Statistics Collection TaskSwitch software is assumed to use Polling scheme to collect statistics with one second interval. The procedure using AUTOZ* mode is as follows:

1. Wait for one second

2. Read all counter registers

3. Go to 1)

*If AUTOZ is enabled, a counter is cleared when it is read.

The width of counters are decided based on packet switching rate and this statistics collection task with one second interval. Therefore an overflow won’t happen in normal operation. If it happened, an interrupt will be generated.

If AUTOZ is disabled, Carry registers can be used to detect rollover conditions and adjust counter values maintained by Processor.


RxPriority0Pkts 25 bits Number of good packets received at 802.1Q user priority levela 0

RxPriority0Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 0

RxPriority1Pkts 25 bits Number of good packets received at 802.1Q user priority level 1














a. This is the priority level in the incoming packet.

Table 3-7. Host Monitoring Statistics


Hostinpkts 25 bits Number of frames transmitted to Host

Hostoutpkts 25 bits Number of good frames received from host

HostoutErrors 25 bits Number of bad frames received from host.


MB87Q3141
Chapter 4: Register Description
4.1 Notation

Bits are numbered in descending order from left to right.

Numerical notation are as follows:Hexadecimal numbers are followed by h.Binary numbers are followed by b.Decimal numbers are default and has no suffix.

Register access types are as follows:RW: Read and WriteRO: Read onlyRC: Read and Clear, The register is cleared when it is read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MSB LSB


Chip Specification

4.2 Address Map

Addressing is Little Endian byte addressing

Each word is 32bit long and the register is accessed by Processor using word-access only.

Figure 4-14 shows Address Space Mapping. For details of the statistics counters, please refer to Chapter 3.

Figure 4-14. Address Space Map

Table 4-8 shows a list of registers and its addresses. To access per-port registers, 3xxxxh is used for broadcast and write only. If it is read, the returned value is undefined. 4xxxh to fxxxh are used for single port access.

0000h

Device Level Registers

Port X Registers

2000h

Port Control Registers

MAC Control Registers

PHY Access Registers

Statistics Counters

+800h

+840h

+880h

+000h

ffffh

e000h

Processor Buffer Registers

Port 0 Registers

Port 1 Registers

Port 2 Registers

Port 10 Registers

Port 11 Registers

(for broadcast)

3000h

4000h

5000h

6000h

f000h

1fffh


MB87Q3141

Table 4-8. Register Address Map

Register Name AddressNumber of Registers

Reset Value Notes

Chip ID Register 0000h 10003 1401h (Revision B),

0003 1400h (Revision A)

General Purpose Register 0004h 1 0000 0000h

Switch Configuration Register 0008h 1 pppp 0000hp reflects ext.pins. Cleared by Hard Reset only.

Switch Status Register 000ch 1 0000 0000h

Priority Mapping Register 0010h 1 fa41 fa41h

DRR Control Register 0014h 1 0000 0000h

TimeStamp Register 0018h 1 0000 0000h

Broadcast Storm Register 001ch 1 0000 0000h

Buffer Management Register 0020h 1 0000 0033h

Aging Timer Register 0024h 1 0000 0059h

Mirroring Control Register 0028h 1 0000 0000h

Management Frame Tag Register 002ch 1 8000 8001h

Processor Port Configuration Register 0030h 1 0000 0001h

Processor Port Status Register 0034h 1 0000 0000h

Outbound Tag Routing Register 0 0038h 1 0000 0000h

Outbound Tag Routing Register 1 003ch 1 0000 0000h

IRQ Status Register 0040h 1 0000 0000h

IRQ Enable Register 0044h 1 0000 0000h

Table Access Command Register 0048h 1 0000 0000h

Table Slice Register 004ch 1 0000 0000h

Inbound Length Register 0050h 1 0000 0000h

Outbound Length Register 0054h 1 0000 0000h

IBUF FCS Value Register 0058h 1 0000 0000h

IBUF Access Control Register 005ch 1 0000 0000h

OBUF FCS Value Register 0060h 1 0000 0000h

OBUF Access Control Register 0064h 1 0000 0000h

MAC Address Table Information Register 0068h 1 0000 0000h

Inbound Destination Register 006ch 1 0000 0000h

LAG Register H 0070h 1 0000 0000h

LAG Register L 0074h 1 0000 0000h

Distribution Function Register 0078h 1 0000 0000h

Distribution Tuning Register 007ch 1 0000 0000h

Tag Memory Error Logging Register 0080h 1 0000 0000h

Tag Redundant Column Register 0084h 1 0000 0000h Revision A only

MST Error Logging Register 0088h 1 0000 0000h

Output Queue Error Status Register 008ch 1 0000 0000h

Stream Memory Error Status Register 0090h 1 0000 0000h

MAC Address Table Error Logging Register 0094h 1 0000 0000h

VLAN Table Error Logging Register 0098h 1 0000 0000h


Chip Specification

IBUF Error Logging Register 009ch 1 0000 0000h

MAC Address Buffer Allocation Status Register 00a0h 10000 0101h (Revision B),

0000 0000h (Revision A)

Management Packet Forwarding Port Register 00a4h 1 0000 1000h

Drop Port Selection Register 00a8h 1 0000 0000h

Learn Drop Count Register 00ach 1 0000 0000h

Broadcast Frame Control Register 00b0h 1 0000 0000h

Processor Port Output Queue Status Register 00c0h 1 0000 1fffh

Processor Port Output Queue Error Injection Register 00c4h 1 0000 0000h

Max Pending Lookup Register 00d0h 1 0000 000fh

Traffic Monitoring Control Register 00d8h 1 0000 0000h

Traffic Monitoring Status Register 00dch 1 0000 0000h

Port Interrupt Status Register 00e0h 1 0000 0000h

Link Fault Status Register 00e4h 1 0000 0000h

Output Queue Status Register 00e8h 1 0000 0000h

Processor Bus Occupancy Control Register 00ech 1 0000 00f3h Cleared by Hard Reset only.

Processor Bus Logging Register 1 00f0h 1 0000 0000h Cleared by Hard Reset only.

Processor Bus Logging Register 2 00f4h 1 0000 0000h Cleared by Hard Reset only.

Table Buffer Register 0100h to 01fch 64 0000 0000h

External XGMII Command Register 0200h 1 0000 0000h

External XGMII Field Register 0204h 1 6086 0000h

External XGMII Configuration Register 0208h 1 0000 003eh

External XGMII Link Fail Vector Register 020ch 1 0000 0000h

External XGMII Indicator Register 0210h 1 0000 0000h

Statistics Counter Hostinpkts 0300h 1 0000 0000h

Statistics Counter Hostoutpkts 0304h 1 0000 0000h

Statistics Counter HostoutErrors 0308h 1 0000 0000h

VLAN Monitor Register 0380h to 03fch 32 0000 0000h

Statistics Counter VLANunicastPkts 0 0400h 1 0000 0000h

Statistics Counter VLANunicastBytesL 0 0404h 1 0000 0000h

Statistics Counter VLANunicastBytesH 0 0408h 1 0000 0000h

Statistics Counter VLANMulticastPkts 0 040ch 1 0000 0000h

Statistics Counter VLANMulticastBytesL 0 0410h 1 0000 0000h

Statistics Counter VLANMulticastBytesH 0 0414h 1 0000 0000h

Statistics Counter VLANunicastPkts 1 0420h 1 0000 0000h

Statistics Counter VLANunicastBytesL 1 0424h 1 0000 0000h

Statistics Counter VLANunicastBytesH 1 0428h 1 0000 0000h

Statistics Counter VLANMulticastPkts 1 042ch 1 0000 0000h

Statistics Counter VLANMulticastBytesL 1 0430h 1 0000 0000h

Statistics Counter VLANMulticastBytesH 1 0434h 1 0000 0000h

(continued for 2 through 30)

Table 4-8. Register Address Map (Continued)


Reset Value Notes


MB87Q3141

Statistics Counter VLANunicastPkts 31 07e0h 1 0000 0000h

Statistics Counter VLANunicastBytesL 31 07e4h 1 0000 0000h

Statistics Counter VLANunicastBytesH 31 07e8h 1 0000 0000h

Statistics Counter VLANMulticastPkts 31 07ech 1 0000 0000h

Statistics Counter VLANMulticastBytesL 31 07f0h 1 0000 0000h

Statistics Counter VLANMulticastBytesH 31 07f4h 1 0000 0000h

Carry Register 1 0800h 1 0000 0000h



Carry Register 4 080ch 1 0000 0000h


Carry Mask Register 1 0814h 1 ffff ffffh


Carry Mask Register 3 081ch 1 ffff ffffh


Carry Mask Register 5 0824h 1 0000 0007h

Debug Port Selection Register 0840h 1 0000 0000h

Inbound Buffer Registers 2000h to 27fch 512 0000 0000h

Outbound Buffer Registers 2800h to 2ffch 512 0000 0000h

Port Configuration Register [3-f]000h 12 0000 0001h

Port Status Register [3-f]004h 12 0000 0001h

Uplink Multicast Filter Register [3-f]008h 12 0000 0000h

PAUSE Control Register [3-f]00ch 12 0055 0000h

Early Detection Control Register [3-f]010h 12 0000 0000h

User VLAN Tag Register [3-f]014h 12 8100 0000h

Port Configuration Register 2 [3-f]018h 12 e032 0000h

IBUF/SM Error Injection Register [3-f]01ch 12 0000 0000h

Output Queue Error Injection Register [3-f]020h 12 0000 0000h

Output Queue Purge Status Register [3-f]024h 12 0000 0000h

Port Output Queue Status Register [3-f]028h 12 0000 1fffh

BPDU Control Register [3-f]02ch 12 0000 0000h

Port IRQ Status Register [3-f]030h 12 0000 0000h

Port IRQ Enable Register [3-f]034h 12 0000 0000h

VLAN Filter State 1/0 Register [3-f]038h 12 0000 0000h

VLAN Filter State 3/2 Register [3-f]03ch 12 0000 0000h

Meter Control Register [3-f]040h 12 0000 0000h

CIR Control Register [3-f]044h 12 0000 0000h

Statistics Counter FWpkts [3-f]080h 12 0000 0000h

Statistics Counter FLDpkts [3-f]084h 12 0000 0000h

Statistics Counter VLANDrops [3-f]088h 12 0000 0000h

Statistics Counter FULLDrops [3-f]08ch 12 0000 0000h



Reset Value Notes


Chip Specification

Statistics Counter STMDrops [3-f]090h 12 0000 0000h

Statistics Counter EDDrops [3-f]094h 12 0000 0000h

Statistics Counter RxPriority0Pkts [3-f]400h 12 0000 0000h

Statistics Counter RxPriority0Bytes [3-f]404h 12 0000 0000h


Statistics Counter RxPriority1Bytes [3-f]40ch 12 0000 0000h













Port Carry Register [3-f]440h 12 0000 0000h

Port Carry Mask Register [3-f]444h 12 003f ffffh

MAC Configuration Register 0 [3-f]800h 12 0000 0000h

MAC Configuration Register 1 [3-f]804h 12 0000 002dh

MAC Configuration Register 2 [3-f]808h 12 040d 0000h

MAC Configuration Register 3 [3-f]80ch 12 0000 ffffh

MAC Station Address LS Word Register [3-f]810h 12 0000 0000h

MAC Station Address MS Word Register [3-f]814h 12 0000 0000h

MAC Maximum Frame Length Register [3-f]820h 12 0180 0600h

MAC Revision Level Register [3-f]82ch 12 0000 0607h

XGMII Command Register [3-f]840h 12 0000 0000h

XGMII Field Register [3-f]844h 12 6086 0000h

XGMII Configuration Register [3-f]848h 12 0000 003eh

XGMII Link Fail Vector Register [3-f]84ch 12 0000 0000h

XGMII Indicator Register [3-f]850h 12 0000 0000h

XAUI Device ID Register [3-f]870h 12 0000 0000h

XAUI Device Type Port Address Register [3-f]874h 12 0000 0001h

Statistics Counter TRC64 [3-f]880h 12 0000 0000h



Statistics Counter TRC511 [3-f]88ch 12 0000 0000h





Reset Value Notes


MB87Q3141

Statistics Counter TRMGVC [3-f]898h 12 0000 0000h

Statistics Counter RXBYTC [3-f]89ch 12 0000 0000h

Statistics Counter RXPKTC [3-f]8a0h 12 0000 0000h

Statistics Counter RXFCSC [3-f]8a4h 12 0000 0000h

Statistics Counter RXMCAC [3-f]8a8h 12 0000 0000h

Statistics Counter RXBCAC [3-f]8ach 12 0000 0000h

Statistics Counter RXCFC [3-f]8b0h 12 0000 0000h

Statistics Counter RXPFC [3-f]8b4h 12 0000 0000h

Statistics Counter RXUOC [3-f]8b8h 12 0000 0000h

Statistics Counter RXALNC [3-f]8bch 12 0000 0000h

Statistics Counter RXFLRC [3-f]8c0h 12 0000 0000h

Statistics Counter RXCDEC [3-f]8c4h 12 0000 0000h

Statistics Counter RXCSEC [3-f]8c8h 12 0000 0000h

Statistics Counter RXUNDC [3-f]8cch 12 0000 0000h

Statistics Counter RXOVRC [3-f]8d0h 12 0000 0000h

Statistics Counter RXFRGC [3-f]8d4h 12 0000 0000h

Statistics Counter RXJBRC [3-f]8d8h 12 0000 0000h

Statistics Counter RXDRPC [3-f]8dch 12 0000 0000h

Statistics Counter TXBYTC [3-f]8e0h 12 0000 0000h

Statistics Counter TXPKYC [3-f]8e4h 12 0000 0000h

Statistics Counter TXMCAC [3-f]8e8h 12 0000 0000h

Statistics Counter TXBCAC [3-f]8ech 12 0000 0000h

Statistics Counter TXPFC [3-f]8f0h 12 0000 0000h

Statistics Counter TXTOC [3-f]910h 12 0000 0000h

Statistics Counter TXDRPC [3-f]914h 12 0000 0000h

Statistics Counter TXJBRC [3-f]918h 12 0000 0000h

Statistics Counter TXFCSC [3-f]91ch 12 0000 0000h

Statistics Counter TXCFC [3-f]920h 12 0000 0000h

Statistics Counter TXOVRC [3-f]924h 12 0000 0000h

Statistics Counter TXUNDC [3-f]928h 12 0000 0000h

Statistics Counter TXFRGC [3-f]92ch 12 0000 0000h

Statistics Counter Control CAR1 [3-f]930h 12 0000 0000h

Statistics Counter Control CAR2 [3-f]934h 12 0000 0000h

Statistics Counter Control CAM1 [3-f]938h 12 fe01 ffffh

Statistics Counter Control CAM2 [3-f]93ch 12 000f ffffh



Reset Value Notes


Chip Specification
4.3 Device Level Registers
Name: Chip ID Register

Address: 0000h

Purpose: Ethernet switch chip identification and revision number.

Field Description:

Note:

Table 4-9. Chip ID Register

Bit(s) Field Name DescriptionAccess Type

Reset Value

31:4 Device Number Device unique number for the chip RO 3140h

3:0 Revision Revision number RO1 (Revision B),0 (Revision A)


MB87Q3141
Name: General Purpose Register
Address: 0004h

Purpose: The usage of this register is up to the firmware.

Field Description:

Note:

Table 4-10. General Purpose Register


Reset Value

31:0 user defined user programmable RW 0


Chip Specification
Name: Switch Configuration Register
Address: 0008h

Purpose: This register defines the configuration of the switch chip.

Field Description:

Table 4-11. Switch Configuration Register


Reset Value

31 SwitchSoftReset

Switch Soft Reset. This similar to power on reset, however, it does not reset CPU Interface and Aux. Register Interface within the switch. The software set it then clear it.0: no1: yes

RW 0

30:29 Reserved Reserved RO 0

28 Processor TypeProcessor Type0: External processor port is connected to MPC8601: External processor port is connected to MPC82xx

RO XI_PIF_MODE[3]

27 UPMUse UPM (User-programmable machine)0: no1: yes

RO XI_PIF_MODE[2]

26:24 RAMPowerControl EnableRAM power control enable. [26:24]=SM/Port/(Reserved).0: no1: yes

RW 0

23 UplinkFilteringMode

Uplink Filtering Mode.0: Leaf Switch, follow Uplink filter settings when MAC Table Hit.1: Root Switch, use Port Vector in MAC Table when MAC Table Hit (MB87Q3141-E compatible)

RW 0

22 VlanTblWbEnable

VLAN Table Writeback Enable when Single Bit Error is detected and cor-rected.0: no (SBE correction, no writeback)1: yes (SBE correction, writeback)

RW 0

21 OddParityOdd Parity on Processor Bus0: no (even parity)1: yes (odd parity)

RO XI_PIF_MODE[1]

20 DisableParityCheckDisable Parity Check on Processor Bus0: no1: yes

RO XI_PIF_MODE[0]

19 BufCfgbyCPUBuffer Configuration by CPU0: no1: yes

RO XI_CONFIG[3] input pin

18 EEPROMPresentEEPROM Present0: no1: yes


17 CPUPresentCPU Present0: no1: yes


16 CPUConfigReadyCPU Configuration Ready. This bit is set by the CPU and shows CPU com-pleted the register initialization.

RW 0


MB87Q3141

15 AgingEnableAging Enable.0: no1: yes

RW 0

14 DRREnable

Deficit Round Robin (DRR) Enable. If enabled, Output queue is arbitrated using DRR for fair bandwidth sharing.0: no1: yes

RW 0

13 VLANEnablePort-based Virtual LAN Enable.0: no1: yes

RW 0

12 DiffServEnableDifferential Services Enable.0: no1: yes

RW 0

11 STPEnableSpanning Tree Protocol Enable0: no1: yes

RW 0

10 MSTPEnable

802.1s Multiple Spanning Tree Protocol Enable. This bit is valid only when STPEnable=10:no1:yes

RW 0

9 JumboEnableJumbo Packet Enable. If enabled, Jumbo packet of 9KB is supported.0:no1:yes

RW 0

8 StoreForwardEnableStore and Forward Enable.0:no (Cut-through)1:yes (Store-n-forward)

RW 0

7 StormControlEnableBroadcast Storm Control Enable.0:no1:yes

RW 0

6 FrameTimeoutDisable

Frame Timeout Disable. If disabled, a packet exceeds the life time is not dropped.0:no1:yes

RW 0

5 InputPortMirroringInput Port Mirroring0:no1:yes

RW 0

4 OutputPortMirroringOutput Port Mirroring0:no1:yes

RW 0

3 SVLShared VLAN Learning0:no (IVL, use VLAN Id as input to Hash function)1:yes (SVL, does not use VLAN Id as input to Hash function)

RW 0

2 DisablePVCompareDisable port vector comparison in Learning0:no (compare port vector)1:yes (not compare port vector)

RW 0

Table 4-11. Switch Configuration Register (Continued)


Reset Value


Chip Specification

Note:

If both EEPROM and CPU are present, CPU initialization process needs to wait for the completion of the EEPROM download. Soft Reset should not be applied by EEPROM initialization code. This register is cleared only by Hard Reset.

1 LearningPrecedence

Learning Precedence. If yes, learning takes precedence over lookup. If no, lookup takes precedence over learning.0:yes1:no

RW 0

0 MACBufEnableMAC Address Buffer Enable.0:no1:yes

RW 0

Table 4-11. Switch Configuration Register (Continued)


Reset Value


MB87Q3141
Name: Switch Status Register
Address: 000ch

Purpose: This register shows the switch status.

Field Description:

Note:

Table 4-12. Switch Status Register


Reset Value


13 EEPROMloadDoneEEPROM Downloading Done0: not done1: done

RO 0

12 L2TableInitDoneL2 Table Initialization Done0: not done1: done

RO 0

11 VLANTableInitDoneVLAN Table Initialization Done0: not done1: done

RO 0

10 TAGMemoryInitDoneTAG Memory Initialization Done0: not done1: done

RO 0

9 BISTDoneBuilt-In-Self-Test Done0: not done1: done

RO 0


5 EEPROMDownloadEEPROM Downloading in Progress0: not in progress1: in progress

RO 0

4 L2TableInitializeL2 Table Initialization in Progress0: not in progress1: in progress

RO 0

3 VLANTableInitializeVLAN Table Initialization in Progress0: not in progress1: in progress

RO 0

2 TAGMemoryInitializeTAG Memory Initialization in Progress0: not in progress1: in progress

RO 0

1 BISTBuilt-In-Self-Test in Progress0: not in progress1: in progress

RO 0

0 BISTFailedBuilt-In-Self-Test Failed0: normal1: failed

RO 0


Chip Specification
Name: Priority Mapping Register
Address: 0010h

Purpose: This register defines the user priority mapping to the output queues.

If DiffServ is enabled, upper 3 bits in TOS / Traffic Class field (DSCP[0:2) defined in RFC2474) is used for the priority mapping. If DiffServ is disabled and VLAN is enabled, the user priority in the VLAN tag is used for the priority mapping. If neither DiffServ nor VLAN is enabled, the default port priority in the Port Configuration Register is used as the user priority for

the priority mapping.

Field Description:

Table 4-13. Priority Mapping Register


Reset Value

31:30 VLANPriority7

VLAN Priority Level 7 Mapping.00b: queue001b: queue110b: queue211b: queue3

RW 11b

29:28 VLANPriority6 VLAN Priority Level 6 Mapping. RW 11b







15:14 DiffServ7

DiffServ Codepoint 7 Mapping.00b: queue001b: queue110b: queue211b: queue3

RW 11b

13:12 DiffServ6 DiffServ Codepoint 6 Mapping. RW 11b








MB87Q3141
Name: DRR Control Register
Address: 0014h

Purpose: This register defines the quantum value for DRR.

The quantum value is described in the unit of 256B. The minimum quantum value corresponds to the max. packet size. ex. 6 for 1500B packet, 36 for 9000B packet If the quantum is zero, DRR is disabled for the priority. If multiple priorities are enabled, DRR is applied to the lowest priority queue among them. For example, all priorities are enabled,

queue 0 is selected.

Field Description:

Note:

When CIR is enable, this register is used to define Quantum values to select for each input port. See CIR Control Register in detail.

Table 4-14. DRR Control Register


Reset Value

31:24 DRRQuantum3 DRR Quantum for Output queue3 RW 0





Chip Specification
Name: Time Stamp Register
Address: 0018h

Purpose: Specifies the interval of the time stamp updates, and the time stamp value.

The current TimeStamp value is attached to an incoming frame. Input/Output ports keep the current TimeStamp and the last TIme Stamp value. An outgoing frame is dropped if the time stamp value of a frame does not match either one of the TimeStamp values (including check

code), and (SwitchConfigurationRegister.FrameTimeoutDisable==0).

Field Description:

Note:

The base counter is reset when Processor writes any value to the Time Stamp Register. The Time Stamp value field is incremented by one and the base counter is reset when the base counter reaches the interval specified in

the Interval field.

Table 4-15. TIme Stamp Register


Reset Value

31 ShortTimerModeShort timer mode0: no1: yes

RW 0


25:24 Interval

Interval00b: 3.2 second (2^30 core cycles) if [31] is 0, otherwise 12.8 ms (2^22 core cycles)01b: 1.6 second (2^29 core cycles) if [31] is 0, otherwise 6.4 ms (2^21 core cycles)10b: 0.8 second (2^28 core cycles) if [31] is 0, otherwise 3.2 ms (2^20 core cycles)11b: 0.4 second (2^27 core cycles) if [31] is 0, otherwise 1.6 ms (2^19 core cycles)

RW 0


20:16 CheckCode Check Code. Calculated by hardware, based on the counter value. RO 0


12:0 CounterValue TimeStampCounterValue RW 0


MB87Q3141
Name: Broadcast Storm Control Register
Address: 001ch

Purpose: This register defines the parameters for the broadcast storm control.

Field Description:

Note:

Table 4-16. Broadcast Storm Control Register


Reset Value


4 BroadcastOnly Drop Broadcast frames only RW 0


1:0 MaxNumStorm

Maximum Number of Broadcast for Storm Control. This defines the maximum number of broadcast (and multicast) frames that can be accumulated in each input port.00b: 31 frames01b: 6310b: 12711b: 255

RW 0


Chip Specification
Name: Buffer Management Register
Address: 0020h

Purpose: This register defines the following parameters for the buffer management.

The port-dedicated size in the unit of a credit which corresponds to 192B. The number of used ports. Dynamic Threshold Factor to control Block Supply

Field Description:

Note:

PertDedicatedSize must be larger than the max. packet size to avoid the other ports from blocking the port. For Processor port, credits of 10 to 18 is assigned depending on the 10G-port configuration. In BufCfgbyCPU mode, MB87Q3141 chip waits for CPUConfigReady becomes 1 before buffer configuration, therefore NumUsed-

Ports and PortDedicatedSize other than defaults are possible.

Table 4-17. Buffer Management Register


Reset Value


13:12 DTFactor

Dynamic Threshold(DT) Factor, alpha00b: 201b: 110b: 0.511b: Disable DT

RW 0


9:8 NumUsedPorts

Number of Used 10G Ports.0xb: 12 (ports 0 to 11 are used)10b: 8 (ports 0, 2, 3, 5, 6, 8, 9 and 11 are used)11b: 4 (ports 0, 5, 6 and 11 are used)

RW 0

7:0 PortDedicatedSize

Port Dedicated Size for a 10G port.recommended values (minimum values) are: 11 when Jumbo is disabled, 51 when Jumbo is enabledmax. allowable value is: 165

RW 51


MB87Q3141
Name: Aging Control Register
Address: 0024h

Purpose: This register defines the aging period for dynamically learned entries in the MAC Address Table.

Field Description:

Note:

The recommended value of aging time is 300 seconds which corresponds to the aging time parameter of 89.

Table 4-18. Aging Control Register


Reset Value

31 ShortTimerModeShort timer mode0: no1: yes

RW 0

30 Reserved Reserved RO 0

29:19 HashAddress Hash address for entry to be aged out. RW 0

18:16 BucketEntry Entry in the Bucket RW 0


9:0 Aging TimeAging Time. The aging time is incremented by 3.4 second (2^30 core cycles) if [31] is 0, otherwise 0.8 ms (2^18 core cycles). The minimum time is 0. The maximum time is 1737 seconds (Aging Time=1feh).

RW 89


Chip Specification
Name: Mirroring Control Register
Address: 0028h

Purpose: This register defines the monitored port and mirror ports for the port mirroring.

A copy of the incoming traffic in the monitored port is sent to a mirror port. A copy of the outgoing traffic in the monitored port is sent to another mirror port.

Field Description:

Note:

If MirrorPortIn = MirrorPortOut, the outgoing traffic is sent to the mirror port. At MirrorPortIn port, VLAN handling needs to be disabled by setting DisableVLANtagHandling=1 in the Port Configuration

Register 2.

Table 4-19. Mirroring Control Register


Reset Value


11:8 MonitoredPortMonitored Port ID.value: 0 to 12

RW 0

7:4 MirrorPortInMirror Port ID for Incoming Traffic.value: 0 to 11

RW 0

3:0 MirrorPortOutMirror Port ID for Outgoing Traffic.value: 0 to 11

RW 0


MB87Q3141
Name: Management Frame Tag Register
Address: 002ch

Purpose: Specify Ethertype values for Inbound/Outbound Management Frames for external processors at 10G port.

Inbound Management Frame Tag is used for specifying the source port and the chip ID.- Traffic from Public Network to the Management Processor.

Outbound Management Frame Tag is used for specifying the destination port.- Traffic from the Management Processor to Public Network. - Multiple destination can be specified, if bit vector format is used.

Field Description:

Note: Frame formats are as follows:

Inbound Management Frame: DA + SA + Inbound-Tag, Inbound-Tag-Value + Payload Outbound Management Frame: DA + SA + Outbound-Tag, Outbound-Tag-Value* + Payload Tag Value Format: Bit Vector Format (Outbound Only)

Priority[15:13] 0 - 7 Priority Level (Mapping Register is used)Tag Type[12] 1 1: bit vector formatPort Vector[11:0] Bit-0: Port-0, .., Bit-11: Port-11, all-0: force processor port.

Port ID Format (Outbound)Priority[15:13] 0 - 7 Priority Level (Mapping Register is used)Tag Type[12] 0 0: Port ID formatGroup ID[11:8] 0 - 15 To identify the destination MB87Q3141 chip.Chip ID[7:4] 0 - 13 To identify the destination MB87Q3141 chip.Port ID[3:0] 0 - 12 (0-11: 10G Port, 12: Processor Port)

Port ID Format (Inbound)Priority[15:13] 0 - 7 Copied from Port Config 2 [31:29]Tag Type[12] 0 always 0Group ID[11:8] 0-15 Copied from Outbound-Routing Register 1 [31:28]Chip ID[7:4] 0-13 Copied from Outbound-Routing Register 1 [27:24]Port ID[3:0] 0-12 Represent the port ID where the frame is received.

Table 4-20. Management Frame Tag Register


Reset Value

31:16 InboundTag Inbound Management Frame Tag RW 8000h

15:0 OutboundTag Outbound Management Frame Tag RW 8001h


Chip Specification
Name: Processor Port Configuration Register
Address: 0030h

Purpose: This register defines the port configuration of Processor Port.

Field Description:

Note:

AUTOZ, CLRCNT, STEN applied to following counters:- VLAN Statistics Counters- Host Monitoring Statistics Counters- Learn Drop Count Register

Incoming frames from Processor port are never learned.

Table 4-21. Processor Port Configuration Register


Reset Value

31 PortSoftResetPort Soft Reset0: no1: yes

RW 0

30 AUTOZStatistics Counter Auto Zero. If set, the counter is cleared when it is read.0: no1: yes

RW 0

29 CLRCNTStatistics Counter Clear.0: no1: yes

RW 0

28 STENStatistics Counter Enable.0: no1: yes

RW 0

27 PortSharingOutboundProcessor Port Sharing for Outbound (From Switch to Processor)0: Port 11 is sharing B/W with Processor Port1: Port 10 is sharing B/W with Processor Port

RW 0

26 PortSharingInboundProcessor Port Sharing for Inbound (From Processor to Switch)0: Port 11 is sharing B/W with Processor Port1: Port 10 is sharing B/W with Processor Port

RW 0

25:24 MulticastFwdMode

Multicast packet forwarding mode.00b: Filter Unregistered Groups01b: Forward Unregistered Groups10b: Forward All Groups11b: (reserved)

RW 0

23:20 Reserved Reserved RW 0

19 VLANIngressChkVLAN Ingress Checking Enable.0: no1: yes

RW 0


14:12 DefaultPriorityDefault User Priority. value: 0 to 7

RW 0

11:0 DefaultVLANIdDefault Port VLAN IDvalue: 1 to 4094, note 0 and 4096 are reserved

RW 1


MB87Q3141
Name: Processor Port Status Register
Address: 0034h

Purpose: This register shows the port status of Processor Port.

Field Description:

Note:

Table 4-22. Processor Port Status Register


Reset Value


5 SrcVLANViolationSource VLAN Boundary Violation0: Normal1: Violation

RC 0

4 DstVLANViolationDestination VLAN Boundary Violation0: Normal1: Violation

RC 0


1 FrameTimeoutFrame Timeout Detected0: Not detected1: Detected

RC 0



Chip Specification
Name: Outbound Tag Routing Register 0
Address: 0038h

Purpose: dedicated routing table for Outbound-Tagged Frames to support external processors at 10G port.

Field Description:

Note:

Table 4-23. Outbound Tag Routing Register 0


Reset Value

31:28 Chip7DestPort Destination port for Chip-ID:7 RW 0









MB87Q3141
Name: Outbound Tag Routing Register 1
Address: 003ch

Purpose: dedicated routing table for Outbound-Tagged Frames to support external processors at 10G port.

Field Description:

Note: The following algorithm is implemented at the receiver of outbound tagged frames.

if( Received frame is Outbound Tagged ) if( PortConfig2[25:24] == 11b ) discard the frame; else if ( PortConfig2[25:24] == 01b ) if( OutboundTag.Type == 0b) // Port ID format if( OutboundTag.GroupID != OutboundRouting1[31:28] ) discard the frame; else if( OutboundTag.ChipID > 13 ) discard the frame; else if( OutboundTag.PortID > 12 ) discard the frame; else if( OutboundTag.ChipID == OutboundRouting1[27:24] ) forward the frame to Port[OutboundTag.PortID]; else if( OutboundTag.ChipID > 7 ) PortID = pickup_PortID from OutboundRouting1/OutboundRouting0, based on OutboundTagChipID; forward the frame to Port[PortID]; else if( OutboundTag.PortVec == 000h ) // bit vector: null forward the frame to the processor port; else // bit vector forward the frame to the ports, using OutboundTag.PortVec; else forward the frame;

Table 4-24. Outbound Tag Routing Register 1


Reset Value

31:28 GroupID Group ID (0-15) RW 0

27:24 ChipID Chip ID (0-13) RW 0








Chip Specification
Name: IRQ Status Register
Address: 0040h

Purpose: Based on the IRQ Status register, request is generated to trigger Interrupt bit.

Field Description:

Note:

Table 4-25. IRQ Status Register


Reset Value

31:28 Reserved Reserved for fatal errors RO 0

27 LookupQueueOverflowLookup Queue Overflow Error (fatal error) is detected. This bit is cleared by chip reset only. After this fatal event happens lookup is not processed although Table operation works.

RO 0

26 PBusERRError is detected on processor bus(fatal error). This bit is cleared when processor writes 1 to bit 31 of Processor Bus Logging Register 1.

RO 0

25 OutputQueueMBEMBE is detected in Output Queue (fatal error). This bit is cleared when processor writes 1 to corresponding bit of Output Queue Error Status Register.

RO 0

24 TagMBEMBE is detected in Tag Memory (fatal error). This bit is cleared when processor writes 1 to bit[31] of Tag Error Logging Register.

RO 0

23 StatisticsCarry Statistics Counter Carry (non-fatal, uncorrectable error) RO 0

22 MACTableErrorMAC Address Table error(non-fatal, uncorrectable error). This bit is cleared when processor writes 1 to bit[31] of MAC Address TAble Error Logging Register.

RO 0

21 VLANTableErrorVLAN Table error(non-fatal, uncorrectable error). This bit is cleared when processor writes 1 to bit[31] of VLAN Table Error Logging Register.

RO 0

20 MSTErrorMST error(non-fatal, uncorrectable error). This bit is cleared when processor writes 1 to bit[31] of MST Error Logging Register.

RO 0

19 SMTagMBESBE is detected in Stream Memory Tag (non-fatal, uncorrectable error). This bit is cleared when processor writes 1 to corresponding bit of Stream Memory Error Status Register.

RO 0

18 SMTagSBESBE is detected in Stream Memory Tag (correctable error). This bit is cleared when processor writes 1 to corresponding bit of Stream Memory Error Status Register.

RO 0

17 OutputQueueSBESBE is detected in Output queue (correctable error). This bit is cleared when processor writes 1 to corre-sponding bit of Output Queue Error Status Register.

RO 0

16 TagSBESBE is detected in Tag Memory (correctable error). This bit is cleared when processor writes 1 to bit[30] of Tag Error Logging Register.

RO 0

15 IBUFTagMBEMBE is detected in IBUF (non-fatal, uncorrectable error). This bit is cleared when processor writes 1 to corresponding bit of IBUF Error Logging Register.

RO 0

14 IBUFTagSBESBE is detected in IBUF (correctable error). This bit is cleared when processor writes 1 to corresponding bit of IBUF Error Logging Register.

RO 0

13 PortInterruptPort Interrupt event occurred (correctable error).This bit is cleared when processor writes 1 to corre-sponding bit of Port IRQ Status Register[13:0].

RO 0

12 LinkFailureLink failure is detected (correctable error). This bit is cleared when processor writes 1 to bit[0] of Port IRQ Status Register.

RO 0

11:4 Reserved Reserved for no errors RO 0

3 OutputQueueStatusOutput Queue Status event occurred. This bit is cleared when processor sets 0s to mask bits of (Port) Output Queue Status Register.

RO 0

2 TxCmpl Transmission Completed. RO 0

1 FrameRdy Frame Ready. A Frame is ready in Outbound Buffer Registers. RO 0

0 TableOpCmplTable Operation Completion. This bit is cleared when processor writes arbitrary data to the Table Access Command Register.

RO 0


MB87Q3141
Name: IRQ Enable Register
Address: 0044h

Purpose: This register enables to service each of the pending IRQ requests. User can program through the processor to see only the Interrupts of interest.

Field Description:

Note:

Table 4-26. IRQ Enable Register


Reset Value

31:28 Reserved Reserved for fatal errors RO 0

27 LookupQueueOverflow Lookup Queue Overflow interrupt is enabled. RW 0

26 PBusERR Processor Bus interrupt is enabled. RW 0

25 OutputQueueMBE Output Queue MBE interrupt is enabled. RW 0

24 TagMBE Tag Memory MBE interrupt is enabled. RW 0

23 StatisticsCarry Statistics Counter Carry RW 0

22 MACTableError MAC Table Error interrupt is enabled. RW 0

21 VLANTableError VLAN Table Error interrupt is enabled. RW 0

20 MSTError MST Error interrupt is enabled. RW 0

19 SMTagMBE Stream Memory Tag MBE interrupt is enabled. RW 0

18 SMTagSBE Stream Memory Tag SBE interrupt is enabled. RW 0

17 OutputQueueSBE Output Queue SBE interrupt is enabled. RW 0

16 TagSBE Tag Memory SBE interrupt is enabled. RW 0

15 IBUFTagMBE IBUF tag MBE interrupt is enabled. RW 0

14 IBUFTagSBE IBUF tag SBE interrupt is enabled. RW 0

13 PortInterrupt Port Interrupt is enabled. RW 0

12 LinkFailure Link failure Interrupt is enabled. RW 0

11:4 Reserved Reserved for no errors RO 0

3 OutputQueueStatus Output Queue Status Interrupt is enabled. RW 0

2 TxCmplEnable Transmission Completion interrupt is enabled RW 0

1 FrameRdyEnable FrameReady Interrupt is enabled RW 0

0 TableOpCmplEnable Table Operation Completion interrupt is enabled. RW 0


Chip Specification
Name: Table Access Command Register
Address: 0048h

Purpose: Select MAC Address Table, VLAN Table ID to start access.

Field Description:

Note:

Writing any value to this register while the Table Operation Completion bit of the IRQ Status Register is 1, clears the Table Operation Completion bit.

Table 4-27. Table Access Command Register


Reset Value


6:4 TypeofAccess

Type of Table Access000b: No operation001b: Table read010b: Table write011b: Table Block Delete100b: Table search101b: (reserved)110b: Table learn111b: Table delete

RW 0


2:0 Table ID

Table Select000b: MAC Address Table001b: VLAN Table010b: Stream Memory (for debug)011b: TAG Memory (for debug)100b: Multicast State Table (for debug)101b: (reserved)110b: (reserved)111b: (reserved)

RW 0


MB87Q3141
Name: Table Slice Register
Address: 004ch

Purpose: For the range of addresses CPU performs table operations.

Field Description:

Note: The maximum number of entries is 64 because of the buffer size is 256bytes.

Table 4-28. Table Slice Register


Reset Value


22:16 NumEntries The number of entries. RW 0

15:0 StartEntry Start Entry RW 0


Chip Specification
Name: Inbound Length Register
Address: 0050h

Purpose: Shows state of the Inbound Buffer Registers, and controls transfer of packets.

Writing non-zero value to the ByteCount field triggers the frame transfer from the Inbound Buffer to the Switch. The transmission command cannot be canceled. Thus, the processor should check the interface state and the buffer credit before issuing a transmission command. Upon Completion of the transfer, IRQ Status[2] is set by the hardware. Writing any value to the Inbound Length Register will clear the IRQ Status[2].

Field Description:

Table 4-29. Inbound Length Register


Reset Value

31 InterfaceRdyInterface ready.0: no1: yes

RO 0


29 CmdResultCommand Result. 0: the last transmitted frame was not dropped.1: the last transmitted frame was dropped.

RO 0

28 FCSCopyFCS copy. 0: no1: yes

RW 0


23:16 BufCreditBuffer Credit. Unit is 192 byte.If processor tries to send a frame larger than available credit size, the frame will be dropped.

RO 0

15:12 FrameType

Frame Type.0000b: reserved0001b: Ethernet without VLAN tag0010b: SNAP format without VLAN tag0011b: reserved0100b: reserved0101b: Ethernet with VLAN tag0110b: SNAP format with VLAN tag0111b: reserved1000b: BPDU1001b: Untagged GARP frame, Force untag1010b: Tagged GARP frame, UserVLAN tagging by HW (destination port is "Outbound-Tag Handling Disabled") / Outbound-Tagged (Outbound Tag is not removed at the destination port)1011b: Outbound-Tagged, Pop Tag (Outbound Tag is removed at the destination port)1100b: reserved1101b: Tagged GARP frame1110b: reserved1111b: Pause

RW 0

11:0 ByteCount Byte count for transmitting a frame (from DA to FCS) RW 0


MB87Q3141
Note:
In the current definition, the start address of a frame is fixed at Inbound Buffer [0]. Processor cannot send a Jumbo frame if the frame size is bigger than 2047 byte. By nature, the frames from the processor are ‘store&forward’ frames. No storm control is applied to the processor port.


Chip Specification
Name: Outbound Length Register
Address: 0054h

Purpose: Shows state of the Outbound Buffer Registers, and controls transfer of frames.

If FlowControlEnable is 0,- When a frame arrives to the switch, and the destination is the processor port, the frame is transferred to the Outbound Buffer Reg-isters. Byte Count field is set. If error occurs, Reception Error bit is set.- Thus, when a frame is forwarded to the processor port, the Outbound Buffer is always overwritten.

If FlowControlEnable is 1,- When a frame arrives to the switch, and the destination is the processor port, + If IRQ Status[1] is 1, the switch waits until IRQ Status[1] is cleared by processor. + If IRQ Status[1] is 0, the switch sets IRQ Status[1], and clears the byte count field (early notification).- After the frame is transferred to the Outbound Buffer Registers, the Byte Count field is set. If error occurs, Reception Error bit is set.

Writing any value to the Outbound Length Register will clear IRQ Status[1].

Field Description:

Note:

For traffic monitoring, Traffic Monitoring Status Register needs to be read first to make Sampling bit valid. Sampling bit becomes 1 if the frame matches with the captured frame in Traffic Monitoring Status Register. Otherwise 0.

We may need to add more status bits (reception status)

Table 4-30. Outbound Length Register

Bit(s) Field Name Description Access Type Reset Value

31 FlowControlEnableFlow control enable0: no1: yes

RW 0

30 MultibankReceptionEnableMultibank Reception enable0: no (a frame is truncated if the length is greater than 1992 byte).1: yes (a frame is truncated if the length is greater than 4040 byte).

RW 0

29 ResceptionErrorReception Error. A frame was received with error.0: no1: yes

RO 0

28 JumboTruncatedJumbo frame truncated.0: no1: yes

RO 0


24 VLANtaggingVLAN tagging is requested. (frame is not modified)0: no1: yes

RO 0


18 SamplingSampling frame for traffic monitoring.0: no1: yes

RO 0

17:16 ByteCount13_12 Byte Count [13:12] for the received frame (from DA to FCS) RO 0

15:12 InPortNumber In Port Number. RO 0

11:0 ByteCount11_0 Byte Count [11:0] for the received frame (from DA to FCS) RO 0


MB87Q3141
Name: IBUF FCS Value Register
Address: 0058h

Purpose:

IBUF FCS Value register and IBUF Access Control are used for FCS support. Accumulate FCS values when Inbuf is accessed sequentially. Reset with the new value when Inbuf[0] is accessed. The number of padding bytes at the frame tail should be notified before the last 32-bit word is accessed.

Field Description:

Note:

Calculating FCS value for sending frames (when writing to InBuf) void Set_Inbuf ( int len, octet *buf ) int i; unsigned int fcs;

Reg_Write( IBUF_FCS_Padding_Size, 0); // reset padding size reg. for( i=0; i<len-4; i=i+4 ) Reg_Write( InBuf + i, (buf[i]<<24)+(buf[i+1]<<16)+(buf[i+2]<<8)+buf[i+3] ); Reg_Write( IBUF_FCS_Padding_Size, i+4-len ); // set padding length Reg_Write( InBuf + i, 0 ); // FCS field + padding fcs = Reg_Read(IBUF_FCS_Reg ); // get FCS value if( (len - i) == 4) // copy FCS value to the fame Reg_Write( InBuf + i, fcs); else if( (len-i) ==3) Reg_Write( Inbuf + i - 4, (buf[i-4]<<24)+(buf[i-3]<<16)+(buf[i-2]<<8)+(fcs>>24) ); Reg_Write( Inbuf + i, (fcs << 8) ); else if( (len-i) ==2) Reg_Write( Inbuf + i - 4, (buf[i-4]<<24)+(buf[i-3]<<16)+(fcs>>16) ); Reg_Write( Inbuf + i, (fcs << 16) ); else // (len-i) ==1) Reg_Write( Inbuf + i - 4, (buf[i-4]<<24)+(fcs>>8) ); Reg_Write( Inbuf + i, (fcs << 24) );

Table 4-31. IBUF FCS Value Register


Reset Value

31:0 Reserved FCS Value RO 0


Chip Specification
Name: IBUF Access Control Register
Address: 005ch

Purpose:

IBUF FCS Value register and IBUF Access Control Register are used for FCS support. Accumulate FCS values when Inbuf is accessed sequentially. Reset with the new value when Inbuf[0] is accessed. The number of padding bytes at the frame tail should be notified before the last 32-bit word is accessed. Bank switching mechanism to support up to 4KB frame. FCS support for burst traffic.

Field Description:

Note: see IBUF FCS Value Register for usage of this register.

Table 4-32. IBUF Access Control Register


Reset Value

31:28 Bank ID

Bank ID.If 0000b, Inbound Buffer Registers are for octet[0] - octet[2047]if 0001b, Inbound Buffer Registers are for octet[2048] - octet[4095] Otherwise Inbound Buffer Registers are for octet[0] - octet[2047]

RW 0

27 WriteOnlyAccessWrite-only access.0: disable.Both read and write accesses update the IBUF FCS register.1: enable.Only write accesses update the IBUF FCS register.

RW 0

26:25 BurstWriteSupportEnable

Burst-write support enable.00b/1xb: disableIBUF FCS Register is updated always if the target address is for the IBUF. 01b: enableIBUF FCS Register is updated, being aware of Bit[10:0] as the frame length.

RW 0

24 SequentialAccessMonitorFlag

Sequential Access Monitor Flag.Writing 0000b to BankID field will set this bit to 1. Also, an internal variable N is set to zero.When this bit is one, and a data is stored into IBUF[N], N is set to N+1. When a data is stored into other than IBUF[N], this bit is cleared.

RO 0


10:2 FrameLength Frame Length[10:2] in case when Bit[26:25] = 01b. RW 0

1:0 PaddingSizeorFrameLengthNumber of padding byte or Frame Length for FCS generation supportPadding Size when Bit[26:25] = 00b/1xbFrameLength[1:0] when Bit[26:25] = 01b

RW 0


MB87Q3141
Name: OBUF FCS Value Register
Address: 0060h

Purpose:

OBUF FCS Value register and OBUF Access Control Register are used for FCS support. Accumulate FCS values when Outbuf is accessed sequentially. Reset with the new value when Outbuf[0] is accessed. The number of padding bytes at the frame tail should be notified before the last 32-bit word is accessed.

Field Description:

Note:

Checking FCS value for receiving frames (when reading from OutBuf) int ReceiveFrame( int len, octet *buf ) int i, j; unsigned int data, fcs;

Reg_Write( OBUF_FCS_Padding_Size, 0 ); // reset padding size for( i=0; i<len; i=i+4 ) // read frame (including FCS) if( i >= (len - 4) ) Reg_Write( OBUF_FCS_Padding_Size, i - len ); // set padding length data = Reg_Read( OutBuf + i ); for( j=0; j<4; ++j) buf[i+j] = data >> 24; data = data << 8; fcs = Reg_Read(OBUF_FCS_Reg ); // check FCS value return (fcs != 0); // 0: no error

Table 4-33. OBUF FCS Value Register


Reset Value

31:0 Reserved FCS Value RO 0


Chip Specification
Name: OBUF Access Control Register
Address: 0064h

Purpose:

OBUF FCS Value register and OBUF Access Control Register are used for FCS support. Accumulate FCS values when Outbuf is accessed sequentially. Reset with the new value when Outbuf[0] is accessed. The number of padding bytes at the frame tail should be notified before the last 32-bit word is accessed. Bank switching mechanism to support up to 4KB frame. FCS support for burst traffic.

Field Description:

Note: see OBUF FCS Value Register for usage of this register.

Table 4-34. OBUF Access Control Register


Reset Value

31:28 Bank ID

Bank ID.If 0000b, Outbound Buffer Registers are for octet[0] - octet[2047]If 0001b, Outbound Buffer Registers are for octet[2048]-octet[4095] Otherwise, Outbound Buffer Registers are for octet[0] - octet[2047]

RW 0

27 ReadOnlyAccessRead-only access. 0: disable.Both read and write accesses update the OBUF FCS register.1: enable.Only read accesses update the OBUF FCS register.

RW 0

26:25 BurstReadSupportEnable

Burst-read support enable.00b/1xb: disableOBUF FCS Register is updated always if the target address is for the OBUF. 01b: enableOBUF FCS Register is updated, being aware of OutboundLength[10:0]

RW 0

24Sequential Access Monitor-Flag

Sequential Access Monitor Flag.Writing 0000b to BankID field will set this bit to 1. Also, an internal variable N is set to zero.ïWhen this bit is one, and a data is read from IBUF[N], N is set to N+1. When a data is read out from other than IBUF[N], this bit is cleared.

RO 0


1:0 PaddingSize Number of padding byte RW 0


MB87Q3141
Name: MAC Address Table Information Register
Address: 0068h

Purpose:

This register contains the result of the last executed MAC Address Table operation. Effective for MAC Address Table Read/Write/Search/Delete/Learn

Field Description:

Note:

Table 4-35. MAC Address Table Information Register


Reset Value

31 ResultResult.0: no1: yes

RW 0


23:16 AllocationVectorAllocation Vector. (bit[n] for bucket entry (n-16), for example, [23] for bucket entry 7, [16] for bucket entry 0).

RW 0


13:3 HashAddress Hash Address RW 0

2:0 BucketEntryNum Bucket Entry # RW 0


Chip Specification
Name: Inbound Destination Register
Address: 006ch

Purpose:

Defines the destination ports for frames launched by processor.

Field Description:

Note:

When [31] is zero, no side effects (MB87Q3141-F behaves in the same way as MB87Q3141-E) When [31] is one, a frame launched by the processor goes to the ports, specified in the destination port vector field.

(the register value precedes the result of MAC table/VLAN look up results). [30] is cleared when a value is written into the register. [30] is set by hardware after the launched frame is successfully forwarded to the output port. Frame is launched to the destination port even if it belongs to Link Aggregation Group.

Recommended programming model:

1. set up Inbound Buffer for a frame

2. set up Inbound Destination Register

3. check the status in the Inbound Length Register (Interface Ready and Credits)

4. launch the frame by writing a value to Inbound Length Register

5. check the result value of the Inbound Length Register

6. polling [30] of the Inbound Destination Register (typically, it goes 1 immediately)

7. go back to 1

Table 4-36. Inbound Destination Register


Reset Value

31 InboundDestEnableInbound Destination Enable.0: disable1: enable

RW 0

30 FrameLaunchedFrame Launch Status.0: frame not launched1: frame launched

RO 0


11:0 DestPortVector Destination Port Vector. RW 0


MB87Q3141
Name: LAG Register H
Address: 0070h

Purpose: This register shows the members of the Link Aggregation Group (LAG).

Field Description:

Note:

All physical ports in a LAG should have same port state and VLAN membership.

Table 4-37. LAG Register H


Reset Value


15 Port11ActivePort 11 Active.0: inactive (default)1: active

RW 0

14:12 Port11LAG

Port 11 LAG number.0: none (default)1 to 6: LAG to which the port belongs to.7: not used.

RW 0

11 Port10Active Port 10 Active. RW 0

10:8 Port10LAG Port 10 LAG number. RW 0






Chip Specification
Name: LAG Register L
Address: 0074h

Purpose: This register shows the members of the Link Aggregation Group (LAG).

Field Description:

Note:

Table 4-38. LAG Register L


Reset Value

31 Port7ActivePort 7 Active.0: inactive (default)1: active

RW 0

30:28 Port7LAG

Port 7 LAG number.0: none (default)1 to 6: LAG to which the port belongs to.7: not used.

RW 0
















MB87Q3141
Name: Distribution Function Register
Address: 0078h

Purpose: This register defines Distribution Function and Distribution State for Link Aggregation.

Field Description:

Note:

Table 4-39. Distribution Function Register


Reset Value


23 LAG6StateLAG 6 Distribution State.0: enable (default)1: disable

RW 0

22:20 LAG6Function

LAG 6 Distribution Function0: DA only (default)1: SA only2: DA/SA3: Reception port (cluster application only)4 to 7: reserved.

RW 0

19 LAG5State LAG 5 Distribution State RW 0

18:16 LAG5Function LAG 5 Distribution Function. RW 0










Chip Specification
Name: Distribution Tuning Register
Address: 007ch

Purpose: Support a few different distribution patterns for Link Aggregation.

Field Description:

Note:

The following algorithm is used to pick up the N-th link in theDestination LAG, where the number of link is M (M=1, 2, .., 6). if ( DistributionFunction == 0 ) N = ((CRC( DA ) >> (Param & 3)) & 0xf) % min(M,6); else if( DistributionFunction == 1 ) N = ((CRC( SA << 48 ) >> (Param & 3)) & 0xf) % min(M,6); else if( DistributionFunction == 2 ) N = ((CRC((SA << 48)+DA) >> (Param & 3)) & 0xf) % min(M,6); else N = InputPortNumber;

CRC( N )returns 7-bit CRC code of 96-bit integer N, where thepolynomial function is (X7+X+1).

Table 4-40. Distribution Tuning Register


Reset Value


21:20 LAG6DistParam LAG 6 Distribution Parameter. RW 0












MB87Q3141
Name: Tag Memory Error Logging Register
Address: 0080h

Purpose: Log a set of address/data in the Tag memory when SBE/MBE is detected

Field Description:

Note:

Bit31-30 indicates the error status[31:30]==00 no error is logged[31:30]==01 SBE is detected and logged[31:30]==10 MBS is detected and logged[31:30]==11 MBE and SBE is detected, MBE is logged

First occurrence of the most severe error is logged. The error is cleared when processor wries 1 to bit[31:30], or when hardware reset is triggered. (It is not cleared upon software-reset);

writing 1 to bit[31] clears MBE, and writing 1 to bit[30] clears SBE. Upon detection of MBE, the TAG module stops serving request from ICTL/OCTL/CA. Although Tag Memory Module does not

return ACKs to the agent, it continues on draining the request queues.

Table 4-41. Tag Memory Error Logging Register


Reset Value

31 MBE 1: MBE is detected (see also Interrupt Status Register) RW 0

30 SBE 1: SBE is detected (see also Interrupt Status Register) RW 0


26:16 Address Address(11bits) of error entry RW 0

15:11 ErrorCheckCode Error Check Code(5bits) RW 0

10:0 Data Data(11bits) RW 0


Chip Specification
Name: Tag Redundant Column Register (Revision A only)
Address: 0084h

Purpose: To specify unused column (byte column) of the Tag Memory.

Field Description:

Note:

Tag Redundant Column Register is cleared by soft reset.Whenever a value is set to Tag Redundant Column Register,TM module starts TAG initialization automatically.Tag Memory initialization is done by the following steps.a) XI_CONFIG[3] should be 1.b) after hard-reset or soft-reset was done,c) set Tag Redundant Column Registerd) wait for SwitchStatus.TagMemoryInitializationDone.e) set Switch_Config_Reg.CPU_Config_Ready.

Table 4-42. Tag Redundant Column Register


Reset Value


7:0 ColSel

Column Selection. Values other than below are not allowed.0000_0000b column-8 is not used1000_0000b column-7 is not used1100_0000b column-6 is not used1110_0000b column-5 is not used1111_0000b column-4 is not used1111_1000b column-3 is not used1111_1100b column-2 is not used1111_1110b column-1 is not used1111_1111b column-0 is not used

RW 0


MB87Q3141


The table below shows the relationship between TAG Memory Address and Column number.

Table 4-43. Tag Memory Address and Column Number

Tag Memory Address[1:0]Column @ ColSel=

0000_0000bColumn @ ColSel=


1100_0000bColumn @ 1olSel=

1110_0000bColumn @ 1olSel=

1111_0000b

00b 1, 0 1, 0 1, 0 1, 0 1, 0

01b 3, 2 3, 2 3, 2 3, 2 3, 2

10b 5, 4 5, 4 5, 4 6, 4 6, 5

11b 7, 6 8, 6 8, 7 8, 7 8, 7

Tag Memory Address[1:0]Column @ ColSel=




1111_1111b

00b 1, 0 1, 0 2, 0 2, 1

01b 4, 2 4, 3 4, 3 4, 3

10b 6, 5 6, 5 6, 5 6, 5

11b 8, 7 8, 7 8, 7 8, 7

Chip Specification
Name: MST Error Logging Register
Address: 0088h

Purpose: Log a set of address/check-code in the Multicast State Table, and count the number of errors.

Field Description:

Note:

In MST, single bit error/double bit error/up to four bit neighbor error can be detected. First occurrence of the error is logged. Whenever error is detected, ErrorCount field is updated (ErrorCount = ErrorCount +1), even if bit [31] is 1. When an error is detected in a MST entry, the corresponding memory block becomes unusable. Thus, when the value of the Error-

Count field is large, consider to reset the chip. If writing value of Test Write != 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, otherwise no change (compatible to MB87Q3141). If writing value of Test Write = 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, and sets bit[n] if bit[n]=0 (for firmware tests). If written value of Test Write=10b and MST Error Status=0, The address field and Error Detection field is always updated when MST

is read by hardware.

Table 4-44. MST Error Logging Register


Reset Value

31 MSTErrorMST Error Status0: No error is detected.1: Error is detected and logged. (see also Interrupt Status Register)

RW 0

30:29 TestWriteTest Write.10b: Test Writeelse: Not Test Write

RW 0


26:16 Address Address (11bits) of the error entry. RW 0

15:11 EDC Error Detection Code (5bits) RW 0

10:0 ErrorCount Error Count (11bits) RW 0


MB87Q3141
Name: Output Queue Error Status Register
Address: 008ch

Purpose: Show the eror status of Output queues.

Field Description:

Note:

If writing value of Test Write != 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, otherwise no change (compatible to MB87Q3141). If writing value of Test Write = 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, and sets bit[n] if bit[n]=0 (for firmware tests).

Table 4-45. Output Queue Error Status Register


Reset Value



RW 0

28:16 OQMBE Output Queue MBE. bit [n] corresponds to Port [n-16] RW 0


12:0 OQSBE Output Queue SBE. bit [n] corresponds to Port [n] RW 0


Chip Specification
Name: Stream Memory Error Status Register
Address: 0090h

Purpose: Show the error status of Stream Memory Tag.

Field Description:

Note:

If writing value of Test Write != 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, otherwise no change (compatible to MB87Q3141). If writing value of Test Write = 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, and sets bit[n] if bit[n]=0 (for firmware tests).

Table 4-46. Stream Memory Error Status Register


Reset Value



RW 0

28:16 SMTagMBE Stream Memory Tag MBE. bit [n] corresponds to Port [n-16] RW 0


12:0 SMTagSBE Stream Memory Tag SBE. bit [n] corresponds to Port [n] RW 0


MB87Q3141
Name: MAC Address Table Error Logging Register
Address: 0094h

Purpose: Log error information in the MAC Address Table.

Field Description:

Note:

This register cannot be written until MAT error is detected. Writing “1” to bit 31 clears the error condition.

Table 4-47. MAC Address Table Error Logging Register


Reset Value

31 MATErrorMAC Address Table Error Status0: No error is detected.1: Error is detected and logged. (see also Interrupt Status Register)

RW 0


13:3 HashAddress Hash Address RW 0

2:0 BucketEntry Entry Address, Address of Entry in a Bucket RW 0


Chip Specification
Name: VLAN Table Error Logging Register
Address: 0098h

Purpose: Log error information in the VLAN Table.

Field Description:

Note:

Writing “1” to bit 31 clears the error condition.

Table 4-48. VLAN Table Error Logging Register


Reset Value

31 VLTErrorVLAN Table Error Status0: No error is detected.1: Error is detected and logged. (see also Interrupt Status Register)

RW 0

30 ErrorTypeError Type.0: SBE1: MBE

RW 0


11:0 VID VLAN Id RW 0


MB87Q3141
Name: IBUF Error Logging Register
Address: 009ch

Purpose: Show the error status of Input Buffer Tag.

Field Description:

Note:

If writing value of Test Write != 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, otherwise no change (compatible to MB87Q3141). If writing value of Test Write = 10b, writing 1 to bit [n] clears bit [n] if bit[n]=1, and sets bit[n] if bit[n]=0 (for firmware tests). When MBE is observed, the whole contents of the IBUF will be thrown away. The purge is only for the port where a MBE is

detected.IMC starts filling the IBUF with new packets.

Table 4-49. IBUF Error Logging Register


Reset Value



RW 0


27:16 IBUFTagMBE IBUF Tag MBE. bit [n] corresponds to Port [n-16] RW 0


11:0 IBUFTagSBE IBUF Tag SBE. bit [n] corresponds to Port [n] RW 0


Chip Specification
Name: MAC Address Buffer Allocation Status Register
Address: 00a0h

Purpose: Show the allocation status of the MAC Address Buffer

Field Description:

Note:

MAC Address Buffer Allocation status is used in conjunction with Table unavailable bit 2 of the Port Status Register. If Allocation status bits[7:0] = ffh then Bucket with Hash Key 1024 is full.

else if Allocation status bits[15:8] = ffh then Bucket with Hash Key 1025 is full.else if Allocation status bits[15:0] = ffffh then Bucket with Hash Key 1024 and 1025 are full.

In Revision B, the capacity of the MAC address buffer is 14 entries instead of 16 (entries 2000h and 2008h cannot be used). In Revision B, entries 2000h and 2008h are treated as “always allocated” and no MAC address can be written into those locations.

Table 4-50. MAC Address Buffer Allocation Status Register



15:8 Buffer1 Allocation Status of Hash Key 1025 RO01h (Revision B), 00h (Revision A)

7:0 Buffer0 Allocation Status of Hash Key 1024 RO01h (Revision B), 00h (Revision A)


MB87Q3141
Name: Management Packet Forwarding Port Register
Address: 00a4h

Purpose: Specify the port to forward management packets (reserved addresses)

Field Description:

Note:

Table 4-51. Management Packet Forwarding Port Register


Reset Value


12:0 MngFwdPort Port to forward management packet (reserved address) RW 1000h


Chip Specification
Name: Drop Port Selection Register
Address: 00a8h

Purpose: Programmed ports for dropping frames.

Field Description:

Note:

If bit 31 is enabled then the frame which need to be dropped is forwarded by routing table to either one of drop ports specified in [12:0]

If bit 31 is disabled then the frame which need to be dropped is forwarded by routing table to source port.

Table 4-52. Drop Port Selection Register


Reset Value

31 DropPortSelEnableDrop port selection enable.(Test purpose only. This value should be zero)0: no (drop at source port)1: yes (drop based on DropPort)

RW 0


12:0 DropPort Drop ports for dropping the frame other than input port RW 0


MB87Q3141
Name: Learn Drop Count Register
Address: 00ach

Purpose: Count learn drop to study the performance impact of learning drop.

Field Description:

Note:

Ram Access conflict can happen due to 1. Learning drop due to Multicast lookup

2. Unicast programmability switch case. If lookup has higher priority learn request can be dropped.

3. Any processor commands like Write/Read/Learn/Search/Delete has higher priority than learning

Bucket full situation can happen 1. Bucket full situation can happen due to capacity limitations on bucket. This result in learn drop of address mapped to same hash

key multiple times. Note: This counter can give statistical data. However this can not give accurate data because same MAC addresses may be repeatedly counted.

Hardware limitations1. Allocation conflicts: In order to avoid the multiple entries to same location (bucket entry with same hash key) learning requests

are dropped. This is managed by pipeline comparison for hash key.

2. Ingress check failure for learning can lead to learning drop even though addresses are not present in the MAC address table.

FIFO Full1. Learning drop due to FIFO full to store learning requests in the routing table.

Table 4-53. Learn Drop Count Register


Reset Value

31RamAccessConflict CountEn-able

Enable to count MAC addresses not learned due to RAM Access conflict.0: no1: yes

RW 0

30BucketFullCountEnable

Enable to count MAC Addresses not learned due to Bucket full.0: no1: yes

RW 0

29HardwareLimitationCountEna-ble

Enable to count the MAC Address not learned due to hardware limitations. 0: no1: yes

RW 0

28 FIFOFullCountEnableEnable to count the MAC Address not learned due to FIFO full. 0: no1: yes

RW 0


23:0 Learn Drop Count Count of Learning drop due to respective enable bits RW 0


Chip Specification
[Recommend Programming model]
1. Processor Set the enable bit for appropriate counter.

2. Send frames to MB87Q3141 10G ports

3. Learning drops due to various reasons listed above can counted. This is more statistical data. It cannot be accurate. Because the Same Source Address can be repeated dropped.

4. This can used as statistical data to study throughput impacts due to routing table learning limitations.


MB87Q3141
Name: Broadcast Frame Control Register
Address: 00b0h

Purpose: Control forwarding of broadcast frames based on the incoming port as an additional storm control feature.

Field Description:

Note:

When a corresponding bit of the input port vector is one, broadcast frames coming from the input port are not forwarded to the processor.

Table 4-54. Broadcast Frame Control Register


Reset Value


11:0 InputPortVector Input Port Vector to control broadcast frames. RW 0


Chip Specification
Name: Processor Port Output Queue Status Register
Address: 00c0h

Purpose: This register shows Output Queue (OQ) Status and mask in the Processor port.

Field Description:

Note:

Empty bit corresponds to ORed result for all priorities.

Table 4-55. Processor Port Output Queue Status Register


Reset Value


28:16 Mask Mask for the Output queue event. Bit[28] is for input port 12, and Bit[16] is for input port 0. RW 0


12:0 Empty Empty status of the Output queue. bit[12] is for input port 12, and Bit [0] id for input port 0. RO 1fffh


MB87Q3141
Name: Processor Port Output Queue Error Injection Register
Address: 00c4h

Purpose: injects single bit error/multiple bit error to Output Queue (OQ) in the Processor port.

Field Description:

Note:

Table 4-56. Processor Port Output Queue Error Injection Register


Reset Value


23:0 ErrorPatternError Injection Pattern for OQ which is 24bit wide. If error pattern is all zero (default), no error is injected.

RW 0


Chip Specification
Name: Max Pending Lookup Register
Address: 00d0h

Purpose: This register defines the maximum number of Pending Lookups.

Field Description:

Note:

Min. value of MaxLookup is 1.

Table 4-57. Max Pending Lookup Register


Reset Value


3:0 MaxLookup Max. number of lookups. RW 15


MB87Q3141
Name: Traffic Monitoring Control Register
Address: 00d8h

Purpose: This register controls traffic monitoring operation.

Sampling Rate is defined as (Total Packets / Total Samples). Counts frames from input ports with Monitoring enabled.

Field Description:

Note:

Sampling rate is uploaded to an internal counter when it is or becomes zero. Sampling is not performed if FrameCaptured bit=1 in Monitoring Status Register. Sampling frame is forwarded to CPU even if the frame is dropped. Even when a 10G port is selected as a management port, sFlow can be processed at local.

Table 4-58. Traffic Monitoring Control Register


Reset Value


27:16 MonitoringEnableMonitoring Enable, bit[n] corresponds to Input port[n-16]0: disable (default)1: enable

RW 0

15:4 SamplingRate15_4 Sampling Rate[15:4] RW 0

3:0 SamplingRate3_0 Sampling Rate[3:0], fixed to zero. RO 0


Chip Specification
Name: Traffic Monitoring Status Register
Address: 00dch

Purpose: This register shows the Traffic monitoring status.

Field Description:

Note:

This register is updated when a frame is sampled and FrameCaptured bit=0. See Outbound Length Register and definition of Sampling bit.

Table 4-59. Traffic Monitoring Status Register


Reset Value

31 FrameCapturedFrame Captured.0: no (default)1: yes

RC 0


26:16 FrameIdentification Frame Identification of the captured frame. RC 0


12:0 OutputPortVector Output Port Vector of the captured frame. RC 0


MB87Q3141
Name: Port Interrupt Status Register
Address: 00e0h

Purpose: Check Port Interrupt status and enable interrupt generation per port.

Field Description:

Note:

Table 4-60. Port Interrupt Status Register


Reset Value


27:16 PerPortEnablePer Port Enable. 1: Port Interrupt generation is enabled for the corresponding port. Bit[27] is for Port-11, and bit[16] is for Port-0.

RW 0


11:0 PerPortStatusPer Port Status. 1: Port Interrupt generation is requested by the corresponding port. Bit[11] is for Port-11, and bit[0] is for Port-0.

RO 0


Chip Specification
Name: Link Fault Status Register
Address: 00e4h

Purpose: Check Link Fault status and enable interrupt generation per port.

Field Description:

Note:

Table 4-61. Link Fault Status Register


Reset Value


27:16 PerPortEnablePer Port Enable. 1: Link Fault Interrupt generation is enabled for the corresponding port. Bit[27] is for Port-11, and bit[16] is for Port-0.

RW 0


11:0 PerPortStatusPer Port Status. 1: Link Fault Interrupt generation is requested by the corresponding port. Bit[11] is for Port-11, and bit[0] is for Port-0.

RO 0


MB87Q3141
Name: Output Queue Status Register
Address: 00e8h

Purpose: This register shows masked results of Output Queue status from each port and reports an output queue event.

Field Description:

Note:

Output Queue event generates an interrupt to CPU. When CPU sets Mask=0 of this register, the event is cleared.

Table 4-62. Output Queue Status Register


Reset Value


28:16 Mask Mask for the Outputqueue event. Bit[28] is for Port-12, and bit[16] is for Port-0. RW 0


12:0 Status Status from corresponding output port. Bit[12] is for Port-12, and bit[0] is for Port-0. RO 0


Chip Specification
Name: Processor Bus Occupancy Control Register
Address: 00ech

Purpose: Set processor bus occupancy for register read and burst read when UPM is used.

Field Description:

Note:

This register is for debug purpose only and should not be written by software in normal operation. This is a sticky register and only reset by Hardware Reset.

Table 4-63. Processor Bus Occupancy Control Register


Reset Value


16 PPCInterfaceErrorPPC Interface unit detected an unexpected state transition in UPM mode.0: No error is detected1: Error is detected

RO 0


7:4 OccRegRead Set bus occupancy for register read access in UPM mode RW fh

3:0 OccBurstRead Set bus occupancy for burst read access in UPM mode RW 3h


MB87Q3141
Name: Processor Bus Logging Register 1
Address: 00f0h

Purpose: Log error information on Processor Bus.

Field Description:

Note:

This is a sticky register and only reset by Hardware Reset.

Table 4-64. Processor Bus Logging Register 1


Reset Value

31 PBusERRError detected on processor bus.0: No error is detected.1: Error is detected and logged. (see also Interrupt Status Register)

RW 0

30 ErrorTypeError type which was detected on processor bus.0: Parity Error1: TEA detected

RW 0


26 Transaction TypeTransaction Type0: Write1: Read

RW 0

25:24 Transfer Size

Transaction Size00b: Word01b: Byte10b: Half word11b: reserved

RW 0


19:16 Parity Parity of data that has error RW 0

15:2 Address Address of data that has error RW 0



Chip Specification
Name: Processor Bus Logging Register 2
Address: 00f4h

Purpose: Log error information on Processor Bus.

Field Description:

Note:

This is a sticky register and only reset by Hardware Reset.

Table 4-65. Processor Bus Logging Register 2


Reset Value

31:0 Data Data that has error. RW 0


MB87Q3141
Name: Table Buffer Register
Address: 0100h-01fch

Purpose: Buffer register for contents of table slice.

Field Description:

Note: The data format will be defined depending on implementation

Table 4-66. Table Buffer Register


Reset Value

31:0 RW 0


Chip Specification
Name: External XGMII Command Register
Address: 0200h

Purpose: This register defines the operation of the external MDIO Interface.

Field Description:

Note:

Table 4-67. External XGMII Command Register


Reset Value

31 MDIOSoftResetSoft reset for external MDIO interface0: no1: yes

RW 0

30:4 reserved Reserved RO 0

3 hstldcmdThis bit indicates to the XGMII block that an MIIM sequence command has been loaded and to start the operation specified by the contents of hstmiimcmd[2:0].

RW 0

2:0 hstmiimcmd

This is the command that specifies which operation will be performed by XGMII block.000b: Idle, no operation001b: Conventional (10/100/1000 MBS PHY) Write010b: Conventional (10/100/1000 MBS PHY) Read011b: Single Phy Monitor Operation100b: Multiple PHY Monitor Operation101b: 10G PHY Operation110b: Clear Link Fail

RW 0


MB87Q3141
Name: External XGMII Field Register
Address: 0204h

Purpose: This register defines the operation of the external MDIO Interface.

Field Description:

Note:

Table 4-68. External XGMII Field Register


Reset Value

31:30 hststfieldThis field represents the 2-bit ST field of the Management frame format specified by IEEE standard 802.3 Clause 22. For 10G PHY operation, this bit must be set to 00b.

RW 01b

29:28 hstopfield

This field represents the 2-bit OP field of the Management frame format specified by IEEE standard 802.3 Clause 22. For 10G PHY operation, this field is defined for the fol-lowing settings:00b: Address Operation for indirect access01b: Write Access11b: Read Access10b: Post Read Increment Address

RW 10b

27:23 hstphyadxThis field represents the 5-bit PHY Address field of the Management frame format spec-ified by IEEE standard 802.3 Clause 22.

RW 00001b

22:18 hstregadx

This field represents the 5-bit Register Address field of the Management frame format specified by IEEE standard 802.3 Clause 22. Up to 32 registers can be addressed. For 10G operation, this field is used to define the PHY device type for the following settings:00000b: Reserved00001b: PMA/PMD device00010b: WIS00011b: PCS00100b: XGXS PHY00101b: XGXS DTEothers: Undefined

RW 00001b

17:16 hsttafieldThis field represents the 2-bit ST field of the Management frame format specified by IEEE standard 802.3 Clause 22. For 10G PHY operation, this bit must be set to 10b.

RW 10b

15:0 hstmiimwrdatThis field represents the 16-bit Data field of the Management frame format specified by IEEE standard 802.3 Clause 22.

RW 0


Chip Specification
Name: External XGMII Configuration Register
Address: 0208h

Purpose: This register defines the configuration of the external MDIO Interface.

Field Description:

Note:

Table 4-69. External XGMII Configuration Register


Reset Value


7 hstnopramSetting this bit to a one will cause the XGMII block to bypass the preamble portion of the management frame format.

RW 0

6:0 hstclkdivThese 7 bits specify the half clock duration of the MDC output in number of MAC Transmit clock ticks.

RW 3eh


MB87Q3141
Name: External XGMII Link Fail Vector Register
Address: 020ch

Purpose: This register reports the link fail condition in the external PHY device.

Field Description:

Note:

Table 4-70. External XGMII Link Fail Vector Register


Reset Value

31:0 miimlfvecThis vector reports a link fail condition in the PHY device who’s address is that which matches the vector’s index number.

RO 0


Chip Specification
Name: External XGMII Indicator Register
Address: 0210h

Purpose: This register indicates the operation of the external MDIO Interface.

Field Description:

Note:

Table 4-71. External XGMII Indicator Register


Reset Value


4 miimphylf This Link Fail bit is set when the XGMII is doing a single PHY monitor operation. RO 0

3 miimmoncplt This bit will be set when the XGMII is doing a multiple PHY monitor operation. RO 0

2 miimmonvldThis bit will be set on a single PHY monitor operation after one read operation into the PHY’s status register has resulted in acquiring the Link Status bit value.

RO 0

1 miimmonThis bit will always be active from the beginning of and during the complete operation of a single PHY monitor command or a multiple PHY monitor command.

RO 0

0 miimbusyThis busy bit signals the operational time for the XGMII to execute a command. For any single sequence operation this signal will go active at the time the command is written into the XGMII command register and stay active until the conclusion of the operation.

RO 0


MB87Q3141
Name: VLAN Monitor Register

Purpose: Specify VLAN Id to monitor.

Field Description:

Note:

Table 4-72. VLAN Monitor Register


Reset Value


11:0 MonitoredVLANId VLAN Id to monitor RW 0


Chip Specification
Name: Carry Register 1
Address: 0800h

Purpose: Shows carry status of VLANunicastPkts counters.

Field Description:

Note:

Table 4-73. Carry Register 1


Reset Value

31:0 Carry Carry of VLANunicastPkts counters. bit[n] corresponds to VLANunicastPkts[31-n] RW 0


MB87Q3141
Address: 0804h

Purpose: Shows carry status of VLANunicastBytes counters.

Field Description:

Note:



Reset Value

31:0 Carry Carry of VLANunicastBytes counters. bit[n] corresponds to VLANunicastBytes[31-n] RW 0


Chip Specification
Address: 0808h

Purpose: Shows carry status of VLANMulticastPkts counters.

Field Description:

Note:



Reset Value

31:0 Carry Carry of VLANMulticastPkts counters. bit[n] corresponds to VLANMulticastPkts[31-n] RW 0


MB87Q3141
Address: 080ch

Purpose: Shows carry status of VLANMulticastBytes counters.

Field Description:

Note:



Reset Value

31:0 Carry Carry of VLANMulticastBytes counters. bit[n] corresponds to VLANMulticastBytes[31-n] RW 0


Chip Specification
Address: 0810h

Purpose: Shows carry status of Host counters.

Field Description:

Note:



Reset Value


2 CarryInpkts Carry of Hostinpkts counter. RW 0

1 CarryOutpkts Carry of Hostoutpkts counter. RW 0

0 CarryOuteErrors Carry of HostoutErrors counter. RW 0


MB87Q3141
Name: Carry Mask Register 1
Address: 0814h

Purpose: Specifies carry masks of VLANunicastPkts counters.

Field Description:

Note:

Table 4-78. Carry Mask Register 1


Reset Value

31:0 CarryMask Carry Mask of VLANunicastPkts counters. bit[n] corresponds to VLANunicastPkts[31-n] RW ffff ffffh


Chip Specification
Address: 0818h

Purpose: Specifies carry masks of VLANunicastBytes counters.

Field Description:

Note:



31:0 CarryMask Carry Mask of VLANunicastBytes counters. bit[n] corresponds to VLANunicastBytes[31-n] RW ffff ffffh


MB87Q3141
Address: 081ch

Purpose: Specifies carry masks of VLANMulticastPkts counters.

Field Description:

Note:



Reset Value

31:0 CarryMaskCarry mask f VLANMulticastPkts counters. bit[n] corresponds to VLANMulticastPkts[31-n]

RW ffff ffffh


Chip Specification
Address: 0820h

Purpose: Specifies carry mask of VLANMulticastBytes counters.

Field Description:

Note:



Reset Value

31:0 CarryMaskCarry mask of VLANMulticastBytes counters. bit[n] corresponds to VLANMulticastBytes[31-n]

RW ffff ffffh


MB87Q3141
Address: 0824h

Purpose: Specifies carry masks of Host counters.

Field Description:

Note:



Reset Value


2 CarryMaskInpkts Carry mask of Hostinpkts counter. RW 1

1 CarryMaskOutpkts Carry mask of Hostoutpkts counter. RW 1

0 CarryMaskOuteErrors Carry mask of HostoutErrors counter. RW 1


Chip Specification
Name: Debug Port Selection Register
Address: 0840h

Purpose: This register selects RSV/TSV for XO_TEST_OUT

Field Description:

Note:

RSV/TSV (with RSVP/TSVP) is internally 9bits x 6 cycles @312.5MHz. XO_TEST_OUT is 9 bits x 6 cycles @156.25MHz. If two RSV/TSV events are generated within 12 cycles, the second one is dropped.

Table 4-83. Debug Port Selection Register


Reset Value

31 OutputEnOutput Enable.0:no (XO_TEST_OUT is always zero)1:yes

RW 0


7:4 PortNum Port Number (0-11) RW 0


1:0 OutputSel

Output Select.00b: MAC RX01b: MAC TX1xb: XAUI Monitor

RW 0


MB87Q3141
4.4 Processor Buffer Registers
Name: Inbound Buffer Registers


Purpose: Management Packet Registers.

Field Description:

Note:

The first octet is at MSB side. Thus, DA is in Buf[0], Buf[1][31:16], SA is Buf[1][15:0], Buf[2]

Table 4-84. Inbound Buffer Register


Reset Value

31:0 Management Pkt RW 0

Octet[0] Octet[1] Octet[2] Octet[3]

Octet[4N] Octet[4N+1] Octet[4N+2] Octet[4N+3]

Octet[4] Octet[5] Octet[6] Octet[7]

7 0 7 0 7 0 7 0

31(MSB) 0(LSB)

Buf[0]

Buf[1]

Buf[N]

...


Chip Specification

Name: Outbound Buffer Registers

Address: 2800h-2ffch

Purpose: Management Packet Registers.

Field Description:

Note:

Table 4-85. Outbound Buffer Register


ResetValue

31:0 Management Pkt RW 0


MB87Q3141

4.5 Per Port Registers

Name: Port Configuration Register

Address: [3-f]000h

Purpose: This register defines the port configuration of 10G Ethernet port.

Field Description:

Table 4-86. Port Configuration Register

Bit(s) Field Name DescriptionAccessType

Reset Value

31 PortSoftResetPort Soft Reset0: no1: yes

RW 0

30 AUTOZStatistics Counter Auto Zero. If set, the counter is cleared when it is read.0: no1: yes

RW 0

29 CLRCNTStatistics Counter Clear.0: no1: yes

RW 0

28 STENStatistics Counter Enable.0: no1: yes

RW 0

27 StoreForwardEnableStore and Forward Enable. This bit is valid when StoreForwardEnable=1 in Switch Configuration Register.0: no1: yes

RW 0

26 StormControlEnableStorm Control Enable. This bit is valid when StormControlEnable=1 in Switch Configuration Register.0: no1: yes

RW 0

25:24 MulticastFwdMode

Multicast packet forwarding mode.00b: Filter Unregistered Groups01b: Forward Unregisterd Groups10b: Forward All Groups11b: (reserved)

RW 0

23 EDEnable

Early Detection Enable. This bit enables Early Detection Control for COngestion avoidance using thresh-olds set in the Early Detection Control Register.0: no1: yes

RW 0

22 UplinkUplink. If this bit is set, this link is operates as an uplink.0: no1: yes

RW 0

21 AdmitOnlyVLANTagged

Admit only VLAN-Tagged Frame. If this bit is set, the switch drops all untagged and Priority-tagged pack-ets.0: no1: yes

RW 0

20 DropTagDrop Tagged Frame. If this bit is set, the switch drops all tagged packets.0: no1: yes

RW 0


Chip Specification

Note:

AUTOZ, CLRCNT, STEN applied to following counters:- Transmit and Receive Counters- Receive Statistics Counters- Transmit Statistics Counters- Priority Statistics Counters- FLow Control Statistics Counters

When Multiple Spanning Tree is enabled, PortStateControl should be set to Forwarding.

19 VLANIngressChkVLAN Ingress Checking Enable.0: no1: yes

RW 0

18 LearningDisableLearning Disable0: no1: yes

RW 0

17:16 PortStateControl

Port State Control.00b: Disable. All incoming frames will be discarded. All outgoing frames will be masked.

01b: Blocking and Listening. All incoming frames except BPDUs will be discarded. All outgoing frames except BPDUs will be masked.

10b: Learning. All incoming frames will be learned if possible. And all incoming frames will be discarded after being learned except BPDUs. All outgoing frames except BPDUs will be masked.

11b: Forwarding. All incoming frames will be learned if possible. And all incoming frames will be for-warded based on the routing decision. All outgoing frames will be transmitted.

RW 0

15 LoopbackLoopback. If this bit is set, the switch allows the incoming packet to be routed back out of 10G port.0: no1: yes

RW 0

14:12 DefaultPriorityDefault User Priority. value: 0 to 7

RW 0

11:0 DefaultVLANIdDefault Port VLAN IDvalue: 1 to 4094, note 0 and 4096 are reserved

RW 1

Table 4-86. Port Configuration Register (Continued)


Reset Value


MB87Q3141

Name: Port Status Register

Address: [3-f]004h

Purpose: This register shows the port status of 10G Ethernet port.

Field Description:

Table 4-87. Port Status Register


Reset Value

31 PortResetAccept

Port Reset Accepted. This bit is reset when PortConfigReg.PortSoftReset is set and set when the reset is accepted.0: no1: yes

RO 0


23:16 IbPktc Packet count in IBUF RW 0


14 RxDropRxDrop event.0: Not observed.1: Observed.

RC 0

13 VLANFilterHitVLAN Filter Hit and Drop.0: Not observed.1: Observed.

RC 0

12 EarlyDropEarly Drop event.0: Not observed.1: Observed.

RC 0

11 PortSecViolationPort Security Violation0: Not observed.1: Observed.

RC 0

10 LoopbackAlertFlagLookback Alert Flag.0: Not observed.1: Observed.

RC 0

9 StormDropStorm Drop event.0: Not observed.1: Observed.

RC 0

8 LookupBackPressureLookup Back Pressure.0: Not observed.1: Observed.

RC 0

7 InPAUSEPAUSE Status of TX.0: not in Pause1: in Pause

RO 0

6 IBUFUnderflowIBUF Underflow0: Not detected1: Detected

RC 0

5 SrcVLANViolationSource VLAN Boundary Violation0: Normal1: Violation

RC 0

4 DstVLANViolationDestination VLAN Boundary Violation0: Normal1: Violation

RC 0


Chip Specification

Note:

3 IBufFullInput Buffer Full Detected0: Not detected1: Detected

RC 0

2 TableUnavailableTable Entry Unavailable Detected for MAC Learning0: Not detected1: Detected

RC 0

1 FrameTimeoutFrame Timeout Detected0: Not detected1: Detected

RC 0

0 LinkFailPort Link Status0: Normal1: Fail

RO 1

Table 4-87. Port Status Register


Reset Value


MB87Q3141

Name: Uplink Multicast Filter Register

Address: [3-f]008h

Purpose: Filter out broadcast and multicast packets to the Uplink and remove duplication to the same end.

Field Description:

Note:

In a cluster configuration, packet duplication to the same end would occur because there are multiple paths for higher bandwidth.

Drop by this filter is not counted by any counter because this is normal.

If Uplink Filter is all zero, this port is not treated as an uplink even when PortConfig.Uplink=1.

Table 4-88. Uplink Multicast Filter Register


Reset Value


12:0 UplinkFilterUplink filter. Bit n corresponds to input port n. Bit value is defined as follows:0: Forward1: Filter (drop)

RW 0


Chip Specification

Name: PAUSE Control Register

Address: [3-f]00ch

Purpose: This register defines the following parameters for the transmit of PAUSE flow control frame.

Watermark for PAUSE command Issue Watermark for PAUSE command cancel The Watermark value is described in the unit of a credit which corresponds to 192B. The Watermark value corresponds to the total of the Input Buffer(16KB) and Port-dedicated Buffer Force PAUSE generation for debug. Write 1 to bit 31 to generate PAUSE ON then write 0 to bit 31 to generate PAUSE OFF Force XOFF for debug. MB87Q3141 chip holds transmission while bit 30 is 1. Add additional IPG after each packet transmission.When the value of the ThrottleControl field is N, the length of the IPG is N/8 of

the transmitted frame.

Field Description:

Note:

Flow control works up to 12KB Jumbo frame in Cut-through mode, 1.5KB frame in Store-and-forward mode1. Hence Cut-through mode is recommended when Jumbo frame is used.

Table 4-89. PAUSE Control Register


Reset Value

31 ForcePAUSEgenerationForce generating PAUSE for debug.0 to 1 transition of this bit: generate PAUSE ON1 to 0 transition of this bit: generate PAUSE OFF

RW 0

30 ForceXOFFForce Transmission Off for debug.0: no1: yes

RW 0

29 StopIBUFRead Stop reading IBUF (for debug). This field should be zero in normal operation. RW 0

28 ShortPauseShort Pause Timer (for debug)0: no (pause timer value is ffffh)1: yes (pause timer value is 00ffh)

RW 0

27:24 ThrottleControl

Throttle Control.0: No additional IPG (throughput = 100%)2: throughput = 80%4: throughput = 66%8: throughput = 50%12: throughput = 40%15: throughput = 35%

RW 0

23:16 XcdtTotal Shared Buffer Credit RO 85

15:8 WmPauseIssueWatermark for PAUSE Command Issue in the unit of a credit. If the port-dedicated credit becomes less than this watermark, the switch issues PAUSE command

RW 0

7:0 WmPauseCancelWatermark for PAUSE Command Cancel in the unit of a credit. If the port-dedicated credit exceeds this watermark, the switch cancels PAUSE command.

RW 0

1. Theoretically the flow control works up to 4.5KB in Cut-and-forward mode.


MB87Q3141
WMPauseIssue depends on the distance and packet size.
Ex. For 100m distance,Frame size WmPauseIssue (Cut-through)1.5KB 519KB 17612KB 224

WmPauseCancelWmPauseIssue < WmPauseCancel < Port Dedicatedhere, Port Dedicated = Port-dedicated credit (see Buffer Management Register) + Input Buffer credit (85)

Figure 4-15. Pause Control Threshold

Name: Early Detection Control Register

Address: [3-f]010h

Purpose: This register defines Early detection thresholds for congestion avoidance.

The Threshold value for dropping the packet The Threshold value is described in the unit of a credit which corresponds to 192B. The Threshold value corresponds to the total of the Input Buffer(16KB) and Port-dedicated Buffer

Field Description:

Note:

The Threshold value should be equal or less than WMPauseIssue in PAUSE Control Register.

Table 4-90. Early Detection Control Register


Reset Value

31:24 EDTh3 Threshold value for Priority 3 RW 0




Input Port Output Port

Port dedicated Shared

WmPauseIssue WmPauseCancel


Chip Specification
Name: User VLAN Tag Register
Address: [3-f]014h

Purpose: This register defines User-programmable VLAN Tag Protocol Type.

Field Description:

Note:

Statistics counter excludes UserVLAN tag for Byte count.

Table 4-91. User VLAN Tag Register


Reset Value

31:16 UserVPIDVLAN Protocol Identifier for User VLAN Tag. User VPID > 1500

RW 8100h



MB87Q3141
Name: Port Configuration Register 2
Address: [3-f]018h

Purpose: This register defines additional port configurations of 10G Ethernet port.

Field Description:

Table 4-92. Port Configuration Register 2


Reset Value

31:29 DefaultQueueID Default Queue ID for Management Frame. RW 111b

28 ForceSFforManagementFrame force Store & Forward for Management frames. RW 0

27 DropInboundTagFrame drop Inbound-Tagged frames at reception/transmission. RW 0

26 EnableInboundTagFrameHandling enable Inbound-Tagged frame handling. RW 0

25 DropOutboundTagFrame drop Outbound-Tagged frame for transmission RW 0

24 EnableOutboundTagFrameHandling enable Outbound-Tagged frame handling RW 0

23:16 JumboCredit Jumbo Frame Credits. RW 50

15 ForceInboundTagged force Inbound-Tagged, unless it is already Inbound-Tagged. RW 0

14 DisableVLANtagHandlingdisable VLAN-tag Handling.0: no1: yes

RW 0

13 VLANStateFilterEnableVLAN State Filter Enable.0: no1: yes

RW 0

12 PortSecurityMode

Port Security Mode.0: shutdown (While PortSecurityViolation is detected (PortIRQStatus[11]==1), ALL the frames from the port are dropped.The first frame which causes the violation is trapped to the CPU.When PortIRQStatus[11] is cleared by CPU, the shutdown condition is released)

1: filtering (Once PortSecurityViolation is detected, only frames which causes PortSecuri-tyViolation are dropped. The first frame which causes the violation is trapped to the CPU. Even after the PortSecurityViolation, frames with pre-registered MAC addresses are for-warded as usual. When PortIRQStatus[11] is cleared by CPU, the filtering condition is released.

RW 0

11 PortSecurityEnablePort Security Enable.0: no1: yes

RW 0

10 IPv6DiffservEnableIPv6 Diffserv Enable.0: no1: yes

RW 0

9 MLDSnoopingEnableMLD Snooping Enable.0: no1: yes

RW 0

8 IGMPSnoopingEnableIGMP Snooping Enable.0: no1: yes

RW 0

7 DRR DisableDRR Disable.0: no1: yes

RW 0


Chip Specification

Note:

Recommended value for typical application is: 00XX_0032h(no Jumbo), 00XX_0036h(Jumbo). Here XX is an appropriate Jumbo Credit value.

Jumbo Credit value should maintain the relationships of the following registers as 1<2<3.1. MAC Maximum Frame Length Register. Frame Size Limit (bytes)

2. Port Config 2 Register. Jumbo Frame Credit (credits)

3. Buffer Management Register. Port Dedicated Size (credits)

Jumbo frame with Type 0800 passes only when SwitchConf.JumboEnable = 1 & PortConf2.TruncationDisable = 1. DRR for the port is determined by the combination of DRR Disable bit in this register and DRR Enable bit in the Switch

Configuration Register.• DRR Enable in Switch Configuration Register 0 1 1• DRR Disable in Port Configuration Register 2 x 0 1• Action Disable Enable Disable

When Port Security is enabled, both source address and port vector are compared with MAC Table entries.

6 DRR Mode

DRR Mode.0: fine DRR, DRR is precise but wire-speed is not achieved (MB87Q3141-E compatible mode).1: Coarse DRR, Performance is best but DRR may not be exact in a short period of time.

RW 0

5 JumboFrameOptJumbo Frame Optimization Enable.0: no1: yes

RW 0

4 PostIBufEDPost IBUF Early Detection Enable.0: no1: yes

RW 0

3 DelayedWriteEnable Delayed Write Enable (removed definition but keep this bit for compatibility). RW 0

2 TruncationDisableTruncationDisable.0: no1: yes

RW 0

1:0 OMCFifoControl

OMC FIFO Control.00: compatible to MB87Q314101: reserved1x: advanced FIFO control enable

RW 0

Table 4-92. Port Configuration Register 2 (Continued)


Reset Value


MB87Q3141
Name: IBUF/SM Error Injection Register
Address: [3-f]01ch

Purpose: Inject Single Bit Error/Multi Bit Error to IBUF/SM.

Field Description:

Note:

Table 4-93. IBUF/SM Error Injection Register


Reset Value

31 IBUFErrInjEnableIBUF Error Injection Enable.0: no1: yes

RW 0

30 SMErrInjEnableSM Error Injection Enable.0: no1: yes

RW 0


18:16 BytePosition Data Error Injection Byte Position (0-7) RW 0

15:8 ECCErrPattern ECC Error Injection Pattern. RW 0

7:0 DataErrPattern Data Error Injection Pattern. RW 0


Chip Specification
Name: Output Queue Error Injection Register
Address: [3-f]020h

Purpose: Inject Single Bit Error/Multi Bit Error to Output Queue (OQ).

Field Description:

Note:

Table 4-94. Output Queue Error Injection Register


Reset Value


23:0 ErrorInjPattern Error Injection Pattern. RW 0


MB87Q3141
Name: Output Queue Purge Status Register
Address: [3-f]024h

Purpose: accelerate sending Marker frame by draining Output Queues in the 10G port.

Field Description:

Note:

Output port moves to Purge in progress state when ForcePurge is set and go back to not in progress when output queue becomes empty.

When Purge in progress, all frames other than BPDU are dropped.

Table 4-95. Output Queue Purge Status Register


Reset Value


28:16 ForcePurge

Force Purge on output queue corresponds to input port. Bit[28] is for input port 12. Bit[16] is for input port 0.0: not force purge (default) 1: force purge

RW 0


12:0 PurgeInProgress

Purge In Progress on output queue corresponds to input port. Bit[28] is for input port 12. Bit[16] is for input port 0.0: not in progress (default) 1: in progress

RO 0


Chip Specification
Name: Port Output Queue Status Register
Address: [3-f]028h

Purpose: This register shows Output Queue (OQ) status and mask in the 10G port.

Field Description:

Note:

Empty bit corresponds to ORed result for all priorities.

Table 4-96. Port Output Queue Status Register


Reset Value


28:16 Mask Mask for output queue empty event. Bit[28] is for input port 12. Bit[16] is for input port 0. RW 0


12:0 Empty

Empty status of Output Queue for corresponding input port. Bit[28] is for input port 12. Bit[16] is for input port 0.0: not empty1: empty (reset value)

RO 1ffh


MB87Q3141
Name: BPDU Control Register
Address: [3-f]02ch

Purpose: This register controls handling of BPDU frames for 802.1ad support.

Field Description:

Note:

Table 4-97. BPDU Control Register


Reset Value

31 ForceRedirectForce Redirect. 1: redirect all the frames other than the terminated BPDU, to the port specified in the field [30:18]

RW 0

30:18 RedirectVector Redirect Vector. Bit [30]: processor port; [29]: port-11; .., [18]: port-0 RW 0

17 ControlGARP Control GARP. 1: transfer GARP PDU (01-80-c2-00-00-20/21/22/../2F) transparently. RW 0

16 Control10 1: transfer 01-80-c2-00-00-10 transparently. RW 0

15 Control0F 1: transfer 01-80-c2-00-00-0F transparently. RW 0

14 Control0E 1: transfer 01-80-c2-00-00-0E transparently. RW 0

13 Control0D 1: transfer 01-80-c2-00-00-0D transparently. RW 0

12 Control0C 1: transfer 01-80-c2-00-00-0C transparently. RW 0

11 Control0B 1: transfer 01-80-c2-00-00-0B transparently. RW 0

10 Control0A 1: transfer 01-80-c2-00-00-0A transparently. RW 0












Chip Specification
Name: Port IRQ Status Register
Address: [3-f]030h

Purpose: Keep track of events detected at the port.

Field Description:

Note:

Bit[13:0] corresponds to Bit[13:0] of Port Status Register. Bit[13:0] is RW1C for basic operation. If writing value of TestWrite != 10b, writing 1 to bit[n] clears bit[n] if bit[n]=1, otherwise no change. If writing value of TestWrite == 10b, writing 1 to bit[n] clears bit[n] if bit[n]=1, and sets bit[n] if bit[n]=0 (for firmware tests).

Table 4-98. Port IRQ Status Register


Reset Value


30:29 TestWriteTest Write. 10b: Test Write, else not for firmware tests.

RW 0


14 RxDropRx Drop1: Rx Drop event was observed.

RW 0

13 VLANFilterHitVLAN Filter Hit1: Frame dropped by VLAN Filter

RW 0

12 EarlyDropEarly Drop1. Early Drop event was observed.

RW 0

11 PortSecurityViolationPort Security Violation1: Port Security Violation was observed.

RW 0

10 LoopbackAlertLoopback Alert1: A loopback frame was detected.

RW 0

9 StromDropStorm Drop1: Storm Drop event was observed.

RW 0

8 LookupBackpressureLookup Backpressure observed.1: Lookup Backpressure was observed.

RW 0

7 InXOFFState 1: TX went into XOFF state. RW 0

6 IBUFUnderflowIBUF Underflow.1: Detected.

RW 0

5 SrcVLANViolation Source VLAN Boundary Violation was detected. RW 0

4 DestVLANViolation Destination VLAN Boundary Violation was detected. RW 0

3 IBUFFull Input Buffer Full condition was detected. RW 0

2 TableUnavailable Table Entry is unavailable for MAC learning. RW 0

1 FrameTimeout Frame Timeout was detected. RW 0

0 Port Link Fault Port Link fault was detected. RW 0


MB87Q3141
Name: Port IRQ Enable Register
Address: [3-f]034h

Purpose: Based on the value of Port Interrupt Status Register [13:0], MAC Configuration Register[25:24] and PHY register, Interrupt Request is generated.

Field Description:

Note:

Bit[30:28] does not affect the behavior of Port Status[0], nor XO_STS_OUT output.

Table 4-99. Port IRQ Enable Register


Reset Value


30 PHYLinkFaultEnable PHY Link Fault Enable.1: if bit[0]=1 then PHY Link Fault updates the bit[0] of Port IRQ Status Register. RW 0

29 RemoteLinkFaultEnableRemote Link Fault Enable.1: if bit[0]=1 then Remote Link Fault updates the bit[0] of Port IRQ Status Register.See also MAC Configuration Register 2, bit[25].

RW 0

28 LocalLinkFaultEnableLocal Link Fault Enable.1: if bit[0]=1 then Local Link Fault updates the bit[0] of Port IRQ Status Register. See also MAC Configuration Register 2, bit[24].

RW 0


14 RxDrop Rx Drop interrupt enable. RW 0

13 VLANFilterHit VLAN Filter Interrupt is enable. RW 0

12 EarlyDrop Early Drop interrupt enable. RW 0

11 PortSecurityViolation Port Security Violation interrupt is enable. RW 0

10 LoopbackAlert Loopback Alert Interrupt is enabled. RW 0

9 StormDrop Storm Drop interrupt enable. RW 0

8 LookupBackpressure Lookup Backpressure interrupt is enabled. RW 0

7 InXOFFState TX XOFF Interrupt is enable. RW 0

6 IBUFUnderflow IBUF Underflow Interrupt is enable. RW 0

5 SrcVLANViolation Source VLAN Boundary Violation Interrupt is enabled. RW 0

4 DestVLANViolation Destination VLAN Boundary Violation Interrupt is enabled. RW 0

3 IBUFFull Input Buffer Full Interrupt is enabled. RW 0

2 TableUnavailable Table Entry Unavailable Interrupt is enabled. RW 0

1 FrameTimeout Frame Timeout Interrupt is enabled. RW 0

0 Port Link Fault Port Link fault Interrupt is enabled. RW 0


Chip Specification
Name: VLAN Filter State 1/0 Register
Address: [3-f]038h

Purpose: This register shows VLAN filtering state.

Field Description:

Note:

When VLAN State Filter Enable = 0 in the Port Configuration Register 2, then entries are invalid.

Table 4-100. VLAN Filter State 1/0 Register


Reset Value

31 Valid1 Valid bit for Entry 1. RO 0


29:28 PortState1 Port State of Entry 1. RO 0

27:16 VLAN_ID1 VLAN ID of Entry 1. RO 0






MB87Q3141
Name: VLAN Filter State 3/2 Register
Address: [3-f]03ch

Purpose: This register shows VLAN filtering state.

Field Description:

Note:

When VLAN State Filter Enable=0 in the Port Configuration Register 2, then entries are invalid.

Table 4-101. VLAN Filter State 3/2 Register


Reset Value










Chip Specification
Name: Meter Control Register
Address: [3-f]040h

Purpose: Support meter function for incoming traffic.

Field Description:

Note:

Table 4-102. Meter Control Register


Reset Value

31 EnableEnable.1: meter enabled.

RW 0

30 ShortTimeUnitShort time unit1: PIR interval is ~25us 0: PIR interval is ~100us

RW 0


25:24 Trimming

Trimming.00b: no trimming01b: add 8 byte per frame for counting 10b: add 16 byte per frame11b: add 24 byte per frame

RW 0

23:16 DataRatioData Ratio. maximum rate of valid data (quantity = 1/256).0: 1/256, 1: 2/256, .. , 255: 256/256

RW 0

15:0 DataCounter Data Counter. signed 16-bit integer for internal use. RW 0


MB87Q3141
Name: CIR Control Register
Address: [3-f]044h

Purpose: This register controls Committed Information Rate (CIR) per port specifying DRR quantum for each port.

Field Description:

Note:

When CIR is enabled at the output port, only one priority is used. In other ports with CIR Disabled, 4 priorities are used.

Table 4-103. CIR Control Register


Reset Value

31 EnableEnable.1: CIR control enabled.

RW 0


25:24 QunatumSel12

Quantum Selection for input port 12.00b: DRR Quantum 0 in DRR Control Register01b: DRR Quantum 110b DRR Quantum 211b: DRR Quantum 3

RW 0

23:22 QunatumSel11 Quantum Selection for input port 11. RW 0













Chip Specification
Name: Port Carry Register
Address: [3-f]440h

Purpose: This register shows carry status of port statistics counters.

Field Description:

Note:

Table 4-104. Port Carry Register


Reset Value


21 CarryFWpkts Carry of FWpkts counter. RW 0

20 CarryFLDpkts Carry of FLDpkts counter. RW 0

19 CarryVLANDrops Carry of VLANDrops counter. RW 0

18 CarryFULLDrops Carry of FULLDrops counter. RW 0

17 CarrySTMDrops Carry of STMDrops counter. RW 0

16 CarryEDDrops Carry of EDpkts counter. RW 0

15 CarryPri0Pkts Carry of Priority0Pkts counter RW 0

14 CarryPri0Bytes Carry of Priority0Bytes counter RW 0
















MB87Q3141
Name: Port Carry Mask Register
Address: [3-f]444h

Purpose: This register specifies carry masks of port statistics counters.

Field Description:

Note:

Table 4-105. Port Carry Mask Register


Reset Value


21 CarryMaskFWpkts Carry Mask of FWpkts counter. RW 1

20 CarryMaskFLDpkts Carry Mask of FLDpkts counter. RW 1

19 CarryMaskVLANDrops Carry Mask of VLANDrops counter. RW 1

18 CarryMaskFULLDrops Carry Mask of FULLDrops counter. RW 1

17 CarryMaskSTMDrops Carry Mask of STMDrops counter. RW 1

16 CarryMaskEDDrops Carry Mask of EDpkts counter. RW 1

15 CarryMaskPri0Pkts Carry Mask of Priority0Pkts counter RW 1

14 CarryMaskPri0Bytes Carry Mask of Priority0Bytes counter RW 1
















Chip Specification
Name: MAC Configuration Register 0
Address: [3-f]800h

Purpose: This register defines the MAC configuration.

Soft Reset of the all sub-modules in the MAC Soft Resets of the Transmit Control and Transmit Function sub-modules Soft Resets of the Receive Control and/or Receive Function sub-modules

Field Description:

Note:

Table 4-106. MAC Configuration Register 0


Reset Value

31 hstmacrstMAC Reset.0: no1: yes

RW 0


22 hstrstrctlReset Receive Control Module within MAC.0: no1: yes

RW 0

21 hstrstrfnReset Receive Function Module within MAC.0: no1: yes

RW 0


18 hstrsttctlReset Transmit Control Module within MAC.0: no1: yes

RW 0

17 hstrsttfnReset Transmit Function Module within MAC.0: no1: yes

RW 0

16 hstrstmiimReset MII Management Module within MAC.0: no1: yes

RW 0


8 Reserved Reserved RW 0



MB87Q3141
Address: [3-f]804h


Frame Transmit Frame Receive PAUSE Control Frame

Field Description:



Reset Value

31 hsttctlenSetting this bit will allow the Transmit Control module to send PAUSE Control frames.0: no PAUSE transmit1: PAUSE transmit

RW 0

30 hsttfenSetting this bit will allow the MAC to transmit frames.0: no frame transmit1: frame transmit

RW 0

29 hstrctlen

Setting this bit will cause the Receive Control module to detect and act on PAUSE Control frames.0: no PAUSE detect1: PAUSE detect

RW 0

28 hstrfnenSetting this bit will allow the MAC to receive frames from PHY.0: no frame receive1: frame receive

RW 0

27 reserved Reserved RO 0

26 tfen This bit reflects the current enable state of the Transmit Function module. RO 0

25 reserved Reserved RO 0

24 rfen This bit reflects the current enable state of the Receive Function module. RO 0


12 hstrctlshrtp

Setting this bit causes the reception of XOFF PAUSE Control frames to pause the Trans-mit module for only 4096 byte times, thereby shortening the pause time. (for debug)0: normal pause time1: short pause time

RW 0

11:10 hstdlyfcstx

The setting of these two bits determines the number 0f 4-byte words to delay the Transmit module’s FCS calculation on the transmit frames.00b: no delay01b: 1 4-byte word10b: 2 4-byte word11b: 3 4-byte word.

RW 0

9:8 hstdlyfcsrx

The setting of these two bits determines the number 0f 4-byte words to delay the Receive module’s FCS calculation on the receive frames.00b: no delay01b: 1 4-byte word10b: 2 4-byte word11b: 3 4-byte word.

RW 0


Chip Specification

Note:

7 hstppen

Setting this bit allows for the use of the per-packet settings on transmit frames by the MAC.0: no per-packet setting1: per-packet setting

RW 0

6 hstbigend

Setting this bit causes the data bytes to be swapped. For example bits 31:24 of the trans-mit data will be displaced to bits 7:0 of the transmit data.0: little endian1: big endian

RW 0

5 hstdrplt64Setting this bit will detect a receive frame that is less than 64 bytes in length.0: no1: yes

RW 1

4 hstprmscrx

Setting this bit will allow the MAC Receive module to accept all receive frames that are greater than 8 bytes in length. If this bit is not set, the MAC strictly follow IEEE 802.3ae.0: no1: yes

RW 0

3 hstlenchk

Setting this bit causes the MAC to check the frame’s length field to ensure it matches the actual data field length.0: no1: yes

RW 1

2 hstgenfcsSetting this bit causes the MAC to generate and append a FCS on all frames.0: no1: yes

RW 1

1:0 hstpadmode

The setting of these two bits determines the pad mode for the MAC Transmit Function as follows:00b: Does not pad the transmit frame01b: Conditionally pads frames to 64 bytes. Appends an FCS on all frames.10b: Detects VLAN frames and conditionally pads them to 68 bytes. Detects non-VLAN frames and conditionally pads to 64 bytes. Appends an FCS to all frames.11b: Conditionally pads frames to 68 byte. Appends an FCS to all frames.

RW 01b

Table 4-107. MAC Configuration Register 1 (Continued)


Reset Value


MB87Q3141
Address: [3-f]808h


Link Fault Detection Inter Packet Gap WAN PHY Support Short IPG Support

Field Description:



Reset Value

31 hsttctlfrcpSetting this bit forces the MAC to transmit a single PAUSE Control frame. (for debug)0: no1: yes

RW 0


27 hstmlnkflthManual link fault handler which forces local fault sequences.0: no1: yes

RW 0

26 hstalnkflth

Steady state configuration bit which outputs local or remote fault sequences based on rflnkflt.0: no1: yes

RW 1

25:24 rflnkflt

Asserted when link fault detected as per 802.3ae clause 46.3.400b: no fault detect01b: local fault detect10b: remote fault detect11b: reserved

RO 0


20:16 hstipgextmodThese configuration bits represent the denominator in the Inter Packet Gap (IPG) extension algorithm required for optional SONET OC-192 data rate control.(not used)

RW 01101b

15 hstrctlfrcp

Setting this bit forces the ransmit module to pause. If the MAC is currently transmitting a frame, it will wait until the end of that frame before pausing. Clearing this bit un-pause the Transmit module.0: no1: yes

RW 0


5 hstipgexten

Setting this bit enables the IPG extension algorithm required for optional SONET OC-192 data rate control. 0: no1: yes

RW 0


Chip Specification

Note:

Set hstipgexten to 1, in order to enable OC-192 Data Rate Control. When hstipgexten = 1, the following constraints exist in the MAC module.- hstmipgext should be zero.- The transmitting frame size should be less than 1664 byte.- OC-192 Data Rate Control is only for standard frames. - MAC Maximum Frame Length Register should be 0180_0600h.

PauseControl.ThrottleControl field is ignored, when hstipgexten = 1. hstmipgext is always considered to extend IPG, even for negative values.

-It is recommended to set always PortConfig2.OMCFifoControl as 1xb.

4:0 hstmipgext

These configuration bits represent the additional minimum average IPG byte count above the default 12 bytes for transmitting back-to-back frames. With MB87Q3141-F chip, shorter IPG is allowed. hstmipgext[4:0] is interpreted as follows:00000b - 11011b (0 - 27): addtional IPG (positive value) 0-27, No change from the current definition. 11100b (28):average min IPG is 8 byte (28-32 = -4)11101b (29):average min IPG is 9 byte (29-32 = -3) 11110b (30):average min IPG is 10 byte (30-32 = -2) 11111b (31):average min IPG is 11 byte (31-32 = - 1)

RW 0

Table 4-108. MAC Configuration Register 2 (Continued)


Reset Value


MB87Q3141
Address: [3-f]80ch


Packet Filtering Condition based on the Receive Statistics Vector

Field Description:

Note:



Reset Value

31:16 hstfltrfrm

These configuration bis are used to signal the drop frame conditions. These bits correspond to the Receive Statistics Vector on a one per port basis.The setting of this bits along with their don’t care values in the hstfltrfrmdc configuration registers, create the packet filter.

RW 0

15:0 hstfltrfrmdcThese configuration bits indicate which Receive Statistics Vectors are don’t cares. Setting of the bit will indicate a don’t care for the corresponding bit to the Receive Statistics Vector.

RW ffffh


Chip Specification
Name: MAC Station Address LS Word Register
Address: [3-f]810h

Purpose: This register defines the lower 4 byte of the MAC station address.

Field Description:

Note:

Table 4-110. MAC Station Address LS Word Register


Reset Value

31:0 hstmacadr[31:0] These filed holds the lower 4 byte of the MAC station address. RW 0


MB87Q3141
Name: MAC Station Address MS Word Register
Address: [3-f]814h

Purpose: This register defines the higher 2 byte of the MAC station address.

Field Description:

Note:

Table 4-111. MAC Station Address MS Word Register


Reset Value

31:16 hstmacadr[47:32] These filed holds the higher 2 byte of the MAC station address. RW 0



Chip Specification
Name: MAC Maximum Frame Length Register
Address: [3-f]820h

Purpose: This register defines the maximum frame length.

Field Description:

Note:

Table 4-112. MAC Maximum Frame Length Register


Reset Value


29:16 hstmxfrmwctxThis field represents the word count (4 bytes) of the maximum allowable frame size in the transmit direction.

RW180h

(=384)

15:0 hstmxfrmbcrxThis field represents the byte count of the maximum allowable frame size in the receive direction.

RW600h

(=1536)


MB87Q3141
Name: MAC Revision Level Register
Address: [3-f]82ch

Purpose: This register shows the revision level of the MAC.

Field Description:

Note:

Table 4-113. MAC Revision Level Register


ResetValue


15:0 revlvl This field represents the revision level of the MAC. RO 607h


Chip Specification
Name: XGMII Command Register
Address: [3-f]840h

Purpose: This register defines the operation of the XGMII Management.

Field Description:

Note:

Table 4-114. XGMII Command Register


ResetValue


3 hstldcmdThis bit indicates to the XGMII block that an MIIM sequence command has been loaded and to start the operation specified by the contents of hstmiimcmd[2:0].

RW 0

2:0 hstmiimcmd

This is the command that specifies which operation will be performed by XGMII block.000b: Idle, no operation001b: Conventional (10/100/1000 MBS PHY) Write010b: Conventional (10/100/1000 MBS PHY) Read011b: Single Phy Monitor Operation100b: Multiple PHY Monitor Operation101b: 10G PHY Operation110b: Clear Link Fail

RW 0


MB87Q3141
Name: XGMII Field Register
Address: [3-f]844h

Purpose: This register defines the operation of the XGMII Management.

Field Description:

Note:

Reading value of hstmiimwrdat is the read data in the last MDIO operation.

Table 4-115. XGMII Field Register


Reset Value

31:30 hststfieldThis field represents the 2-bit ST field of the Management frame format specified by IEEE standard 802.3 Clause 22. For 10G PHY operation, this bit must be set to 00b.

RW 01b

29:28 hstopfield

This field represents the 2-bit OP field of the Management frame format specified by IEEE standard 802.3 Clause 22. For 10G PHY operation, this field is defined for the fol-lowing settings:00b: Address Operation for indirect access01b: Write Access11b: Read Access10b: Post Read Increment Address

RW 10b

27:23 hstphyadxThis field represents the 5-bit PHY Address field of the Management frame format spec-ified by IEEE standard 802.3 Clause 22.

RW 00001b

22:18 hstregadx

This field represents the 5-bit Register Address field of the Management frame format specified by IEEE standard 802.3 Clause 22. Up to 32 registers can be addressed. For 10G operation, this field is used to define the PHY device type for the following settings:00000b: Reserved00001b: PMA/PMD device00010b: WIS00011b: PCS00100b: XGXS PHY00101b: XGXS DTEothers: Undefined

RW 00001b

17:16 hsttafieldThis field represents the 2-bit TA field of the Management frame format specified by IEEE standard 802.3 Clause 22. For 10G PHY operation, this bit must be set to 10b.

RW 10b

15:0 hstmiimwrdatThis field represents the 16-bit Data field of the Management frame format specified by IEEE standard 802.3 Clause 22.

RW 0


Chip Specification
Name: XGMII Configuration Register
Address: [3-f]848h

Purpose: This register defines the configuration of the XGMII Management.

Field Description:

Note:

Table 4-116. XGMII Configuration Register


Reset Value


7 hstnopramSetting this bit to a one will cause the XGMII block to bypass the preamble portion of the management frame format.

RW 0

6:0 hstclkdivThese 7 bits specify the half clock duration of the MDC output in number of MAC Transmit clock ticks.

RW 3eh


MB87Q3141
Name: XGMII Link Fail Vector Register
Address: [3-f]84ch

Purpose: This register reports the link fail condition in the PHY device.

Field Description:

Note:

Table 4-117. XGMII Link Fail Vector Register


Reset Value

31:0 miimlfvecThis vector reports a link fail condition in the PHY device who’s address is that which matches the vector’s index number.

RO 0


Chip Specification
Name: XGMII Indicator Register
Address: [3-f]850h

Purpose: This register indicates the operation of the XGMII Management.

Field Description:

Note:

Table 4-118. XGMII Indicator Register


Reset Value


4 miimphylf This Link Fail bit is set when the XGMII is doing a single PHY monitor operation. RO 0

3 miimmoncplt This bit will be set when the XGMII is doing a multiple PHY monitor operation. RO 0

2 miimmonvldThis bit will be set on a single PHY monitor operation after one read operation into the PHY’s status register has resulted in acquiring the Link Status bit value.

RO 0

1 miimmonThis bit will always be active from the beginning of and during the complete operation of a single PHY monitor command or a multiple PHY monitor command.

RO 0

0 miimbusyThis busy bit signals the operational time for the XGMII to execute a command. For any single sequence operation this signal will go active at the time the command is written into the XGMII command register and stay active until the conclusion of the operation.

RO 0


MB87Q3141
Name: XAUI Device ID Register
Address: [3-f]870h

Purpose: This register shows Device ID for XAUI registers.

Field Description:

Note:

Table 4-119. XAUI Device ID Register


Reset Value

31:0 Device ID Device ID for XAUI registers. RW 0


Chip Specification
Name: XAUI Device Type Port Address Register
Address: [3-f]874h

Purpose: This register shows Device Type and Port address for XAUI registers.

Field Description:

Note:

Table 4-120. XAUI Device Type Port Address Register


Reset Value


8 Device TypeDevice Type.0: XGXS DTE1: XGXS PHY

RW 0


4:0 Port Address Port Address. RW 1


MB87Q3141
4.6 PHY Registers4.6.1 Overview
Table 4-121 shows the PHY register overview of High Speed IO block (XAUI logic block). The registers after LPCTL are added for the enhanced XAUI macro. These PHY registers are accessed through PHY access registers defined in MB87Q3141 address space (See Figure 4-14, “Address Space Map,” on page 28).

Table 4-121. PHY Register overview.

Address Name R/W Description

00h PHY/DTE XS Control 1 R/W Reset, loopback control.

01h PHY/DTE XS Status 1 R/O Link up status.

02h, 03h Device Identifier R/O Manufacturer and device unique ID.

04h PHY/DTE XS Speed Ability R/O Indicates 10G capability.

08h PHY/DTE XS Status 2 R/O Fault status.

18h 10G PHY/DTE XGXS Lane Status R/O Alignment, synchronization status.

19h 10G PHY/DTE XGXS Test Control R/W Test function control.

C000h Vender Specific Control 1 R/W Synchronization, deskew control options.

C001h Vender Specific Control 2 R/W Lane synchronization control override.

C002h Vender Specific Control 3 R/W Deskew control override.

C003h Vender Specific Control 4 R/W Test function control (each lane).

C004h Vender Specific Control 5 R/W Lane/polarity swap function control.

C005h Vender Specific Control 6 R/W PRBS generator/checker control.

C010h Vender Specific Status 1 R/O Speed-matching FIFO synchronization status.

C011h Vender Specific Status 2 R/O Illegal code, disparity error status.

C012h Vender Specific Status 3 R/O Lane synchronization (comma align) position status of each lanes.

C013h Vender Specific Status 4 R/O Synchronization FSM monitor.

C014h Vender Specific Status 5 R/O Deskew position status.

C015h Vender Specific Status 6 R/O Deskew FSM monitor.

C016h Vender Specific Status 7 R/O Test pattern receiving status.

C017h Vender Specific Status 8 R/O PRBS error status.

C020h Vender Specific Control 7 R/W Transceiver macro power down.

C021h Vender Specific Control 8 R/W Transmitter level control.

C030h Vender Specific Status 9 R/O PRBS checker timer for lane 0.








C038h Vender Specific Status 17 R/O PRBS checker error counter for lane 0.

C039h Vender Specific Status 18 R/O PRBS checker error counter for lane 0.

C03Ah Vender Specific Status 19 R/O PRBS checker error counter for lane 1.

C03Bh Vender Specific Status 20 R/O PRBS checker error counter for lane 1.

C03Ch Vender Specific Status 21 R/O PRBS checker error counter for lane 2.


Chip Specification

C03Dh Vender Specific Status 22 R/O PRBS checker error counter for lane 2.

C03Eh Vender Specific Status 23 R/O PRBS checker error counter for lane 3.

C03Fh Vender Specific Status 24 R/O PRBS checker error counter for lane 3.

C040h Vender Specific Control 9 R/W Register access test.

C041h Vender Specific Status 25 R/O Register access test

C070h LPCTL R/W LPGEN control

C074h LPCH R/W LPGEN channel select

C078h LPCFG R/W LPGEN configuration data

C102h TXSTS R/O Tx status

C104h TXCH R/W Tx channel select

C108h TXCFG_0 R/W Tx configuration data 0

C109h TXCFG_1 R/W Tx configuration data 1

C10Ah TXCFG_2 R/W Tx configuration data 2

C10Bh TXCFG_3 R/W Tx configuration data 3

C10Ch TXCFG_4 R/W Tx configuration data 4

C110h RXCTL R/W Rx control

C114h RXCH R/W Rx channel select

C118h RXCFG_0 R/W Rx configuration data 0

C119h RXCFG_1 R/W Rx configuration data 1

C11Ah RXCFG_2 R/W Rx configuration data 2

C11Bh RXCFG_3 R/W Rx configuration data 3

C11Ch RXCFG_4 R/W Rx configuration data 4

C11Dh RXCFG_5 R/W Rx configuration data 5

C122h IMSTS R/O ISI monitor status

C128h IMCFG_0 R/W ISI monitor configuration 0

C129h IMCFG_1 R/W ISI monitor configuration 1

C12Ah IMCFG_2 R/W ISI monitor configuration 2

C132h MCRCTL_0 R/W Macro control signals 0




C140h RACTL_0 R/W Rx adaptation control 0


C142h RASTS_0 R/O Rx adaptation status 0

C143h RASTS_1 R/O Rx adaptation status 1

C144h RAMSEL R/W Rx adaptation measurement select

C148h RAMDAT R/O Rx adaptation measurement data


C14Ah RACTL_3 R/W Rx adaptation control 3

C14Bh RACTL_4 R/W Rx adaptation control 4

C14Ch RACTL_5 R/W Rx adaptation control 5

C14Dh RACTL_6 R/W Rx adaptation control 6

Table 4-121. PHY Register overview. (Continued)

Address Name R/W Description


MB87Q3141
4.6.2 PHY/DTE XS Control 1 register
Table 4-122 shows the bit assignment of PHY/DTE XS Control 1 register.

4.6.3 PHY/DTE XS Status 1 register

Table 4-123 shows the bit assignment of PHY/DTE XS Status 1 register.

4.6.4 Device Identifier register

Address 02h and 03h (Registers 4.2, 4.3) provide a 32-bit value, which shall constitute a unique identifier for a PHY XS (Table 4-124).

Table 4-122. PHY/DTE XS Control 1 (Register 4/5.0).

Bit Name R/W Default Description

15 ResetR/W

SCa

a. Self Clearing.

0write: 0 = nothing happens / 1 = reset performedread: 0 = reset done / 1 = reset in progressThis reset clears internal state of XAUI Logic Block, but not affects Transceiver macro.

14 Loopback R/W 0 0 = disable loop-back / 1 = enable loop-back

13 Speed selection R/W 1 written value is ignored.

6 Speed selection R/W 1 written value is ignored.

5:2 Speed selection R/W 0 written value is ignored.

Table 4-123. PHY/DTE XS Status 1 (Register 4/5.1).


7 Fault R/O -0 = No fault condition detected1 = Fault condition detectedThis bit is logical-or of the fault bits (4/5.8.11, 4/5.8.10)

2PHY XS transmit link status

R/O

LLa

a. Latching Low. When the condition to be low has occurred, the bit shall remain low until after it has been read via MDIO.

-0 = The PHY XS transmit link us down (not aligned)1 = The PHY XS transmit link is up (aligned)This bit is a LL version of bit 4/5.24.12

1 Low power ability R/O 0always 0(PHY/DTE XS does not support low power mode)

Table 4-124. Device Identifier register (Register 4/5.2, 4/5.3).


2.15:0 Device Identifier R/O -returns I_DEVID[31:16] input value, which represents bit 3 through 18 of OUI (Organizationally Unique Identifier). Bit 2.15 corresponds to bit 3 of OUI, and bit 2.0 corresponds to bit 18 of OUI.

3.15:10 Device Identifier R/O -returns I_DEVID[15:10] input value, which represents bit 19 through 24 of OUI (Organizationally Unique Identifier). Bit 3.15 corresponds to bit 19 of OUI, and bit 3.10 corresponds to bit 24 of OUI.

3.9:4 Device Identifier R/Oreturns I_DEVID[9:4] input value, which represents 6-bit wide Manufacturer’s Model Number. Bit 3.9 is MSB, and bit 3.4 is LSB.

3.3:0 Device Identifier R/O -returns I_DEVID[9:4] input value, which represents 4-bit wide Revision Number. Bit 3.3 is MSB, and bit 3.0 is LSB.


Chip Specification
4.6.5 PHY/DTE XS Speed Ability register
Table 4-125 shows the bit assignment of PHY/DTE XS Speed Ability register.

4.6.6 PHY/DTE XS Status 2 register

Table 4-126 shows the bit assignment of PHY/DTE XS Speed Ability register.

4.6.7 10G PHY/DTE XGXS Lane Status register

Table 4-127 shows the bit assignment of 10G PHY/DTE XGXS Lane Status register.

Table 4-125. PHY/DTE XS Speed Ability (Register 4/5.4).


0 10G capable R/O 1 always 1 (PHY/DTE XS is capable of operating at 10G)

Table 4-126. PHY/DTE XS Status 2 (Register 4/5.8).


15:14 Device Present R/O 10always 10 (Device responding at this address)(11,01,00 = No device responding at this address)

11 Transmit faultR/O

LHa

a. Latching High.When the condition to be high has occurred, the bit shall remain high until after it has been read via MDIO.

-0 = No fault condition on transmit path1 = Fault condition on transmit path

10 Receive faultR/O

LH-

0 = No fault condition on receive path1 = Fault condition on receive path

Table 4-127. 10G PHY/DTE XGXS Lane Status (Register 4/5.24).


12PHY/DTE XGXS lane alignment status

R/O -0 = PHY/DTE XGXS transmit lanes not aligned1 = PHY/DTE XGXS transmit lanes aligned

11 Pattern testing ability R/O 1 always 1 (PHY/DTE XGXS is able to generate test patterns)

10 PHY/DTE XGXS loopback ability R/O 1 always 1 (PHY/DTE XGXS has the ability to perform a loopback function)

3 Lane 3 sync R/O -0 = Lane 3 is not synchronized1 = Lane 3 is synchronized





MB87Q3141
4.6.8 10G PHY/DTE XGXS Test Control register
Table 4-128 shows the bit assignment of 10G PHY/DTE XGXS Test Control register.

4.6.9 Vender Specific Control 1 register

Table 4-129 shows the bit assignment of Vender Specific Control 1 register.

Table 4-128. 10G PHY XGXS Test Control (Register 4/5.25).


2 Transmit test pattern enable R/W 00 = Transmit test pattern not enabled1 = Transmit test pattern enabled

1:0 Test pattern select R/W 00

00 = High frequency test pattern (D21.5)01 = Low frequency test pattern (K28.7)10 = Mixed frequency test pattern (K28.5)11 = Middle frequency test pattern (D24.3)

Table 4-129. Vender Specific Control 1 (Register 4/5.49152).


9Transmitter FIFO synchronizer hold mode(I_TXFIFO_SYNC_HOLD_MODE)

R/W 00 = automatically re-synchronizes Tx speed-matching FIFO when it loses synchronization.1 = holds synchronization, once gets it. only re-synchronizes when I_RE_TXFIFO_SYNC becomes 1.

8Transmitter FIFO re-synchronization(I_RE_TXFIFO_SYNC)

R/W 00 = normal.1 = reset Tx speed-matching FIFO. re-start FIFO synchronization when this is de-asserted. holds until O_TXFIFO_SYNC_STATUS becomes 0, then de-asserts.

5Receiver FIFO synchronizer hold mode(I_RXFIFO_SYNC_HOLD_MODE)

R/W 00 = automatically re-synchronizes Receiver speed-matching FIFO when it loses synchronization.1 = holds synchronization, once gets it. only re-synchronizes when I_RE_RXFIFO_SYNC becomes 1.

4Receiver FIFO re-synchronization(I_RE_RXFIFO_SYNC)

R/W 00 = normal.1 = reset Receiver speed-matching FIFO. re-start FIFO synchronization when this is de-asserted. holds until O_RXFIFO_SYNC_STATUS becomes 0, then de-asserts.

3Restart Receiver lane synchronization(I_RE_LANE_SYNC)

R/W 00 = normal.1 = reset code-group aligner. restart PCS synchronization state machine when I_RE_LANE_SYNC goes to 0.

2Restart deskew(I_RE_DESKEW)

R/W 00 = normal.1 = reset deskew. restart PCS deskew state machine when I_RE_DESKEW goes to 0.

1Lane synchronizer override enable(I_LANE_SYNC_OVRD)

R/W 00 = normal.1 = override aligner enable. I_LANE_SYNC_SHIFT[15:0] is used for comma align.

0Deskew override enable(I_DESKEW_OVRD)

R/W 00 = normal.1 = override deskew enable. I_DESKEW_SHIFT[15:0] is used for lane-to-lane deskew.


Chip Specification







15:12 Lane 3 synchronizer override value R/W 0 Lane 3 synchronizer shift value when I_LANE_SYNC_OVRD = 1.






15:12 Lane 3 deskew override value R/W 0 Lane 3 deskew shift value when I_DESKEW_OVRD = 1.




Table 4-132. Vender Specific Control 4 (Register 4/5.49155) .


11Transmit test pattern enable for lane 3(I_TP_ENABLE_3)

R/W 00 = normal / 1 = enable test pattern for lane 3.Transmit test pattern enable (4/5.25.2) is prior to this control.

10:9Test pattern select for lane 3(I_TPSLCT_3)

R/W 0

Test pattern select for lane 3.00 = High frequency test pattern (D21.5).01 = Low frequency test pattern (K28.7).10 = Mixed frequency test pattern (K28.5).11 = Middle frequency test pattern (D24.3 or D6.1 or D25.6).Test pattern select (4/5.25.1:0) is prior to this control.




R/W 0





MB87Q3141




R/W 0





R/W 0




3Transmitter lane swap control(I_SWAP_TXLANE_ENABLE)

R/W 0

0: normal.1: swap lanes.

lane 0 TXFIFO data goes to lane3 HSIO input.lane 1 TXFIFO data goes to lane2 HSIO input.lane 2 TXFIFO data goes to lane1 HSIO input.lane 3 TXFIFO data goes to lane0 HSIO input.

2Transmitter polarity swap control(I_SWAP_TXPOLA_ENABLE)

R/W 00: normal.1: Tx differential output polarity is swapped.

1Receiver lane swap control(I_SWAP_RXLANE_ENABLE)

R/W 0

0: normal.1: swap lanes.

lane 0 data/clock from HSIO goes to lane 3 RXFIFO input.lane 1 data/clock from HSIO goes to lane2 RXFIFO input.lane 2 data/clock from HSIO goes to lane1 RXFIFO input.lane 3 data/clock from HSIO goes to lane0 RXFIFO input.

0Receiver polarity swap control(I_SWAP_RXPOLA_ENABLE)

R/W 00: normal.1: Rx differential input polarity is swapped.

Table 4-132. Vender Specific Control 4 (Register 4/5.49155) (Continued).



Chip Specification

4.6.15 Vender Specific Status 1 register

Table 4-135 shows the bit assignment of Vender Specific Status 1 register.





7PRBS checker timer/error-counter clear(I_PNC_CLR)

R/W 00 = normal.1 = PRBS checker timer/error-counter clear.

6PRBS data select to transmitter macro lane 3(I_PNG_SEL[3])

R/W 0select 195.3125MHz 16bit data to transmitter lane 3. 0 = normal / 1 = select PRBS.







2PRBS generator enable mode(I_PNG_ENABLE_MODE)

R/W 00: PRBS generator enable is asserted at the different timing in each lane.1: PRBS generator enable is asserted at the same timing in all lanes.

1PRBS generator enable(I_PNG_ENABLE)

R/W 00 = normal.1 = PRBS generator enable.

0PRBS checker enable(I_PNC_ENABLE)

R/W 00 = normal.1 = PRBS checker enable. (PRBS checker timer/error-counter count up)

Table 4-135. Vender Specific Status 1 (Register 4/5.49168).


8Transmitter FIFO synchronization status(O_TXFIFO_SYNC_STATUS)

R/O -0 = Transmitter FIFO is not synchronized yet.1 = Transmitter FIFO got synchronized.

3:0Receiver FIFO synchronization status(O_RXFIFO_SYNC_STATUS[3:0])

R/O -0 = Receiver FIFO is not synchronized yet.1 = Receiver FIFO got synchronized.(bit 3: Lane 3, bit 0: Lane0)



15:8Illegal 8B10B code error(O_ERR_IVCODE)

R/O -0 = receiving valid 8B10B code.1 = receiving invalid 8B10B code.(bit 15: O_RD[63:56], bit 8: O_RD[7:0])

7:08B10B code running disparity error(O_ERR_DISPAR)

R/O -0 = 8B10B code running disparity is correct.1 = detecting 8B10B code running disparity error.(bit 15: O_RD[63:56], bit 8: O_RD[7:0])


MB87Q3141









15:12 Lane 3 synchronizer value R/O - Indicates current lane 3 synchronizer shift value.






15:12 Lane 3 PCS synchronization FSM R/O - Indicates state variable of lane 3 PCS synchronization FSM.






15:12 Lane 3 deskew shift value R/O - Indicates current lane 3 deskew shift value.






2:0 Deskew FSM R/O - Indicates the state variable of PCS deskew FSM.


Chip Specification



15Lane 3 test pattern detect (Latching low)(O_TP_DETECT[11])

R/O

LL-

0 = test pattern code is not detected.1 = test pattern code is detected.(Latching low version of bit 14)

14Lane 3 test pattern detect(O_TP_DETECT[11])

R/O -0 = test pattern code is not detected.1 = test pattern code is detected.(continuous status)

13:12Lane 3 test pattern code(O_TP_DETECT[10:9])

R/O -

00 = high frequency test pattern is detected.01 = low frequency test pattern is detected.10 = mixed frequency test pattern is detected.11 = middle frequency test pattern is detected.


R/O

LL-





R/O -



R/O

LL-





R/O -



R/O

LL-





R/O -



MB87Q3141

Table 4-142. Vender Specific status 8 (Register 4/5.49175).


7Lane 3 PRBS error detect (Latching high)(O_PNERR[3])

R/O

LH-

0: error not detected.1: error detect.(Latching high version of bit 6)

6Lane 3 PRBS error detect(O_PNERR[3])

R/O -0: error not detected.1: error detected.(continuous status)


R/O

LH-

0: error not detected.1: error detected.(Latching high version of bit 4)




R/O

LH-





R/O

LH-





Chip Specification



4.6.25 Vender Specific Status 9,10 register

Table 4-145 shows the bit assignment of Vender Specific Status 9 to Status 10 register. Read values are not guaranteed if the PRBS checker is enabled.



15 Transceiver macro power down R/W 00: normal1: power down. (except reference clock input buffer)

7Transmitter macro lane 3 power down

R/W 0 0 = normal / 1 = power down.







3Receiver macro lane 3 power down










4:2 Transmitter level control R/W 100 This field has no effect on enhanced XAUI macro. It remains for compatibility.

1:0 Pre-Emphasis level control R/W 10 This field has no effect on enhanced XAUI macro. It remains for compatibility.

Table 4-145. Vender Specific Status 9,10 (Register 4/5.49200,4/5.49201).


49201.15:0 PRBS checker timer R/O - return timer count of PRBS checker enable period for lane 0 bit [31:16].



MB87Q3141





















49209.15:0 PRBS checker error counter R/O - return error count of PRBS checker enable period for lane 0 bit [31:16].



Chip Specification























15:0 Register access test R/W 0 Any value can be written for MDIO register read/write test.



15:0 Register access test R/O 584Ch always return 584Ch, which is “XL” in ASCII code.


MB87Q3141
4.6.35 LPCTL (Link Pattern Generator Control) register
Table 4-155 shows the bit assignment of LPCTL register.

4.6.36 LPCH (Link Pattern Generator Channel) register

Table 4-156 shows the bit assignment of LPCH register.

Table 4-155. LPCTL (Register 4/5.49264).


7 LPGEN pattern select for lane 3 R/W 00: 16 bit generic pattern.1: square wave.




3 LPGEN enable for lane 3 R/W 00: disable link pattern generation.1: enable link pattern generation.




Table 4-156. LPCH (Register 4/5.49268).


15 Write accessR/W

SC0

0: read configuration of specified lane to LPCFG.1: write LPCFG to configuration of specified lane.

1:0 Lane select R/W 0

00: lane 0.01: lane 1.10: lane 2.11: lane 3.


Chip Specification
4.6.37 LPCFG (Link Pattern Configuration) register
Table 4-157 shows the bit assignment of LPCFG register.

4.6.38 TXSTS (Tx Status) register

Table 4-158 shows the bit assignment of TXSTS register.

4.6.39 TXCH (Tx Channel) register

Table 4-159 shows the bit assignment of TXCH register.

Table 4-157. LPCFG (Register 4/5.49272).


16 bit generic pattern (pattern select = 0)

15:0 pattern R/W 0 Generic 16-bit pattern sent continuously.

square wave (pattern select = 1)

15:10 reserved R/W 0

9:8 period R/W 0

00: 62 UI (31 0s, 31 1s).01: 64 UI (32 0s, 32 1s).10: 124 UI (62 0s, 62 1s).11: 128 UI (64 0s, 64 1s).

7 reserved R/W 0

6:0 phase R/W 0

00h: base square wave.01h: 1 UI earlier than base square wave.02h: 2 UI earlier than base square wave. :7Fh: 127 UI earlier than base square wave.

Table 4-158. TXSTS (Register 4/5.49410).


0 Tx data synchronizer lock status R/O -0: unlock.1: locked.

Table 4-159. TXCH (Register 4/5.49412).


15 Write accessR/W

SC0

0: read configuration of specified lane to TXCFG.1: write TXCFG to configuration of specified lane.




MB87Q3141
4.6.40 TXCFG_0,...,4 (Tx Configuration) register
Table 4-160 shows the bit assignment of TXCFG_0 to 4 register.

Table 4-160. TXCFG_0,...,4 (Register 4/5.49416,...,4/5.49420) .


49420.15:14 reserved R/W 0

49420.13 only for internal use R/W0

(0)aSet 0 for normal use.

49420.12 coefficient polarity of Tx FIR filter tap 4 R/W0

(1)a

0: positive.1: negative.

49420.11:10 reserved R/W 0

49420.9:8 delay control for Tx FIR filter tap 4 R/W0

(0)a

00: delay is 4 UI.01: delay is 5 UI.10: delay is 6 UI.11: delay is 7 UI.

49420.7:0 coefficient magnitude of Tx FIR filter tap 4 R/W0

(0)a

0: minimum. :ffh: maximum.

49419.15:14 reserved R/W 0




(0)a


49419.11:10 reserved R/W 0


(0)a



(0)a


49418.15:14 reserved R/W 0




(1)a


49418.11:10 reserved R/W 0


(10)a



(50h)a


49417.15:14 reserved R/W 0




Chip Specification

4.6.41 RXCTL (Rx Control) register

Table 4-161 shows the bit assignment of RXCTL register.

(*) Note: To bypass Rx equalizer, bit 7:2 must be set to 000000.


(0)a


49417.11:10 reserved R/W 0


(10)a



(c8h)a


49416.15:14 reserved R/W 0




(0)a


49416.11:10 reserved R/W 0


(0)a



(0)a


a. The value in parentheses is the default value of the indirect register for each lane.

Table 4-161. RXCTL (Register 4/5.49424).


7:6 Scale of Rx 2nd-order path gain R/W 11

00: bypass Rx equalizer.(*)01: x 1/16.10: x 1/4.11: x 1/1.

5:4 Scale of Rx 1st-order path gain R/W 11


3:2 Scale of Rx DC path gain R/W 11


Table 4-160. TXCFG_0,...,4 (Register 4/5.49416,...,4/5.49420) (Continued).



MB87Q3141
4.6.42 RXCH (Rx Channel) register
Table 4-162 shows the bit assignment of RXCH register.

4.6.43 RXCFG_0,...,5 (Rx Configuration) register

Table 4-163 shows the bit assignment of RXCFG_0 to 5 register.

Table 4-162. RXCH (Register 4/5.49428).


15 Write accessR/W

SC0

0: read configuration of specified lane to RXCFG.1: write RXCFG to configuration of specified lane.



Table 4-163. RXCFG_0,...,5 (Register 4/5.49432,...,4/5.49437) .


49437.15:8 reserved R/W 0

49437.7:0 only for internal useR/W

(R/O)a

0

(80h)b


(R/O)a

0

(80h)b


(R/O)a

0

(80h)b

49435.15 reserved R/W 0

49435.14 only for internal useR/W

(R/O)c0


(R/O)c0


(R/O)c0



(R/O)a

0

(3)b



(R/O)a

0

(3)b



(R/O)a

0

(3)b



(R/O)a

0

(4Fh)b


Chip Specification

4.6.44 IMSTS (ISI Monitor Status) register

This register is only for internal use.

4.6.45 IMCFG_0,1,2 (ISI Monitor Configuration) register


4.6.46 MCRCTL_0,...,3 (Macro Control) register



49434.6:0 gain control for 2nd-order path R/W0

(1)b

01h - 7Fh : higher number gives higher gain.00h : reserved.



(R/O)a

0

(4Fh)b


49433.6:0 gain control for 1st-order path R/W0

(46h)b




(R/O)a

0

(4Fh)b


49432.6:0 gain control for DC path R/W0

(3Ch)b


a. The indirect registers are read only under normal use.b. The value in parentheses is the defalut value of the indirect register for each lane.c. The indirect registers are always read only.

Table 4-163. RXCFG_0,...,5 (Register 4/5.49432,...,4/5.49437) (Continued).



MB87Q3141
4.6.47 RACTL_0,....,6 (Rx Adaptation Control) register
Table 4-164 shows the bit assignment of RACTL_0 to 6 register.

Table 4-164. RACTL_0,....,6 (Register 4/5.49472,...,4/5.49473,4/5.49481,...,4/5.49485; C140h,...,C141h,C149h,...,C14Dh).


49485.9:0 only for internal use R/W 96h Set 96h for normal use.

49484.14:10 only for internal use R/W 11111 Set 11111 for normal use.














SC0 Set 0 for normal use.

49481.0 only for internal use R/W 1 Set 1 for normal use.


SC0 Set 0 for normal use.



49472.15Signal detected in physical layer.

R/W 11 : Enable received comma detection (signal is detected and Rx equalizer has been tuned).0 : Disable received comma detection (signal is not detected or Rx equalizer has not been tuned).

49472.14 Rx VGLA half-gain mode. R/W 10 : VGLA full gain1 : VGLA half gain










Chip Specification
4.6.48 RASTS_0,1 (Rx Adaptation Status) register
These registers are only for internal use.

4.6.49 RAMSEL (Rx Adaptation Measurement Selection) register


4.6.50 RAMDAT (Rx Adaptation Measurement Data) register



MB87Q3141
4.6.51 XAUI Logic Signal to Register Value Mapping
Figure 4-16 illustrates XAUI logic signals to register value mapping.

Figure 4-16. XAUI logic signal to register value mapping.

XGMII

XGMII

MMD (DTE XS)

Rec

eive

faul

t (5.

8.10

)

Test pattern

Fault Detect

FIFO

Fault Detect

txfif

o_sy

nc_s

tatu

s (

loca

l fau

lt)

Deskew

Comma Detect

align_status

lane

_syn

c_st

atus

[3:0

]

sync

_sta

tus

AN

D

OR

XAUI Rx XAUI Tx

LLD

TE

XS

rec

eive

link

sta

tus

(5.1

.2)

DT

E X

GX

S la

ne a

lignm

ent

sta

tus

(5.2

4.12

)

Lane

3 s

ync

(5.2

4.3)

Lane

2 s

ync

(5.2

4.2)

Lane

1 s

ync

(5.2

4.1)

Lane

0 s

ync

(5.2

4.0)

Test

pat

tern

sel

ect (

5.25

.1:0

)Tr

ansm

it te

st p

atte

rn e

nabl

e (5

.25.

2)

Pat

tern

test

ing

abili

ty (

5.24

.11)

LH

Tran

smit

faul

t (

5.8.

11)

LH

Faul

t (5.

1.7)

Loop

back

(5.

0.14

)

MMD (PHY XS)

Rec

eive

faul

t (4.

8.10

)Test pattern

Fault Detect

FIFO

Fault Detect

txfif

o_sy

nc_s

tatu

s (

loca

l fau

lt)

Deskew

Comma Detect

align_status

lane

_syn

c_st

atus

[3:0

]

sync

_sta

tusA

ND

OR

XAUI RxXAUI Tx

LLP

HY

XS

tran

smit

link

stat

us (

4.1.

2)

PH

Y X

GX

S la

ne a

lignm

ent

sta

tus

(4.2

4.12

)

Lane

3 s

ync

(4.2

4.3)

Lane

2 s

ync

(4.2

4.2)

Lane

1 s

ync

(4.2

4.1)

Lane

0 s

ync

(4.2

4.0)

Test

pat

tern

sel

ect (

4.25

.1:0

)R

ecei

ve te

st p

atte

rn e

nabl

e (4

.25.

2)

Pat

tern

test

ing

abili

ty (

4.24

.11)

LH

Tran

smit

faul

t (

4.8.

11)

LH

Faul

t (4.

1.7)

Loop

back

(4.

0.14

)

PH

Y X

GX

S L

oopb

ack

abili

ty (

4.24

.10)

XAUI

FIFO

FIFO

Upstream MMD TransmitReceive

Downstream MMD


Chip Specification


MB87Q3141
Chapter 5: Error Handling
5.1 Introduction

This chapter describes how the MB87Q3141 chip handles errors. There are five categories of errors:

Input errors Bridge errors Output errors Hardware errors Software errors

These error groups are described in the following sections.

The error level is defined as follows:

F: FatalNFC: Non Fatal CorrectableNFU: Non Fatal Uncorrectable

5.2 Input Errors

Table 5-1 shows Input errors, levels and switch actions.

Table 5-1. Input Errors

Error Type Level Switch Action Note

Local Link Fault NFU Report the status

Remote Link Fault NFU Report the status

Symbol Error NFU Count and drop the packet

Alignment Error NFU Count and drop the packet

Length Error NFU Count and drop the packet

FCS Error NFU Count and drop the packet or abort the transmission of the packet.

Input buffer Full NFU Drop incoming packet

Acceptable Frame Filter NFU Count and drop the packet

Storm Control NFU Drop the packet

VLAN Ingress Check NFU Drop the packet

VLAN Filter Hit NFU Drop the packet and report the event VLAN setting may not be correct.

Port Security Violation NFU Forward the packet to CPU and report the event Firmware needs to check SA in the frame.

Loopback Alert NFU Report the event

Lookup Backpressure NFU Report the event Max. Pending Lookup may not be appropriate.

Input buffer Underflow NFU Truncate the packet and report the event


Chip Specification
5.3 Bridge Errors
Table 5-2 shows Bridge errors, levels and switch actions.

5.4 Output Errors

Table 5-3 shows Output errors, levels and switch actions.

5.5 Hardware Errors

Table 5-4 shows Hardware errors, levels and switch actions.

Table 5-2. Bridge Errors


Life Timeout NFU Count and drop the packet

Table 5-3. Output Errors


VLAN Egress Filter NFU Drop the packet

Local Link Fault NFU Report the status and signalling

Remote Link Fault NFU Report the status

Tx XOFF State NFU Report the event

Table 5-4. Hardware Errors


Lookup Queue Overflow F Report the event need chip reset

Tag Memory MBE F Log and report the event need chip reset

Output Queue MBE F Report the event need chip reset

IBUF Tag MBE NFU Report the event need port reset

MST Error NFU Log, count and report the event if error count becomes large, need chip reset

Stream Memory Tag MBE NFU Report the event

MAC Address Table Error NFU Log and report the event need to delete the entry

VLAN Table Error(MBE/SBE) NFU Log and report the event. Writeback when SBE. need to delete the entry when MBE.

Tag Memory SBE NFC Log and report the event

Output Queue SBE NFC Report the event

IBUF Tag SBE NFC Report the event

Stream Memory Tag SBE NFC Report the event

Processor Bus Error F Log and report the event


MB87Q3141
5.6 Software Errors
Table 5-5 shows Software errors, levels and switch actions.

Table 5-5. Software Errors



Chip Specification


MB87Q3141
Chapter 6: IO Signals
6.1 External Pins

Table 6-6 shows the external pin definition of the Ethernet Switch Chip. The external pins consist of the following groups.

XAUI Ports (192 pins) External Processor Port (66 pins) Auxiliary Register Port (2 pins) EEPROM Interface (2 pins) MDC/MDIO Interface (2 pins) JTAG Port (5 pins) Configuration and Miscellaneous (33 pins) XAUI Test Pins (21 pins) Clock, Reset and Test (18 pins)

Table 6-6. Ethernet Switch Chip External Pins

Signal IO Type Descriptions

XAUI Ports (192 pins)

XI_P00_RXP[3:0]XI_P00_RXN[3:0]

I High Freq. analogXAUI port (Port 00) receiver signals.RXP[n] is the plus of a pair, and RXN[n] is the minus of the pair.

XO_P00_TXP[3:0]XO_P00_TXN[3:0]

O High Freq. analogXAUI port (Port 00) transmitter signals.TXP[n] is the plus of a pair, and TXN[n] is the minus of the pair.




O High Freq. analogXAUI port (Port 01) transmitter signals.TXP[n] is the plus of a pair, and TXN[n] is the minus of the pair






















Chip Specification





















External Processor Port (66 pins)

XI_PER_CLK I2.5VCMOS(3.3V Tol.)

Peripheral clock input for processor interface

XI_PER_CS_N I2.5VCMOS (3.3V Tol.)

Chip select input for processor interface

XI_PER_RESET_N I2.5VCMOS (3.3V Tol.)

Peripheral reset input.

XB_PER_DATA[31:0] IO2.5VCMOS (3.3V Tol.)

Peripheral data bus.

SCAN mode (XI_SMODE=1): [2,0] Scan Out (SO[8:7])

XB_PER_DP[3:0] IO2.5VCMOS (3.3V Tol.)

Peripheral data bus parity.

XI_PER_ADDR[15:2] I2.5VCMOS (3.3V Tol.)

Peripheral address input.

XI_PER_TSIZ[1:0] I2.5VCMOS (3.3V Tol.)

Peripheral transfer size input

Table 6-6. Ethernet Switch Chip External Pins (Continued)



MB87Q3141

XI_PER_ICTRL[4:0] I2.5VCMOS (3.3V Tol.)

Peripheral bus control signals from the processor.For MPC860, [4:3] reserved (Pull up) [2] TS_N (Transaction start, active low), [1] RD/WR_N (Read/write) [0] TEA_N (Transaction Error Acknowledge, active low)For MPC82xx, [4] CSy (Chip select for burst transfer, active low) [3] PGPL2 (Read/write) [2] reserved (Pull up) [1] reserved (Pull up) [0] reserved (Pull up)

XO_PER_OCTRL[2:0] O2.5VCMOS (3.3V Tol.)

Peripheral bus control signal to the processor.For MPC860, [2] reserved (Open) [1] BI_N (Burst Inhibit, active low) [0] TA_N (Transaction Acknowledge, active low)For MPC82xx, [2] reserved (Open) [1] reserved (Open) [0] reserved (Open)

XO_PER_IRQ_N[2:0] O2.5VCMOS (3.3V Tol.)

Peripheral interrupt request to the processor. [2] fatal errors. [1] correctable errors. [0] service required for non-error operations.

SCAN mode (XI_SMODE=1): [2:0] Scan Out (SO[6:4])

Auxiliary Register Port. (2 pins)

XI_REG_CK I2.5VCMOS (3.3V Tol.)

Register port clock input.

XB_REG_DIO IO2.5VCMOS (3.3V Tol.)

Register port data.

EEPROM Interface (2 pins)

XB_EECLK O2.5VCMOS (3.3V Tol.)

EEPROM clock (for devices such as 24C32)

XB_EEDIO IO2.5VCMOS (3.3V Tol.)

EEPROM data. (for devices such as 24C32)

MDC/MDIO Interface (2 pins)

XO_MDC O2.5VCMOS (3.3V Tol.)

MDC/MDIO interface clock.

XB_MDIO IO2.5VCMOS (3.3V Tol.)

MDC/MDIO interface data.




Chip Specification

Chip Configuration and Miscellaneous Signals (33 pins)

XI_PIF_MODE[3:0] I 2.5VCMOS

Configuration signals for processor interface [3:2] 11: External processor port is connected to MPC82xx. UPM is used. 10: This mode is not supported. 01: This mode is not supported. 00: External processor port is connected to MPC860. Burst transfer is not supported [1] 1: Odd Parity 0: Even Parity [0] 1: disable parity check on the bus. 0: enable parity check on the bus.

SCAN mode (XI_SMODE=1) : [0] Scan In (SI[8])

XI_CONFIG[7:0] I 2.5VCMOS

Configuration signals for switch core. [7] 1: disable chattering filter 0: enable chattering filer [6:4] Lower 3 bits of slave address. The slave address is represented by 4’b1010, XI_CONFIG[6:4]. [3] Buffer Configuration(1:by CPU, 0: use Default) [2] EEPROM speed (1:400KHz, 0:100KHz) [1] EEPROM presence (1: with EEPROM) [0] Processor presense.(1: with Processor)

SCAN mode (XI_SMODE=1) : [7:0] Scan In (SI[7:0])

XO_TEST_OUT[8:0] O 2.5VCMOS

Debug bus of core logic and XAUI observation.*Core logic debug mode: [8:0] Status from a port (156MHz). Frame format is TBD.*XAUI observation mode: [8] Reserved [7:4] Observation pins for XAUI port (6-11) [3:0] Observation pins for XAUI port (0-5)

SCAN mode (XI_SMODE=1): [8] Core PLL output when XI_CORE_PLL_BP = 0. [7] Core PLL lock status when XI_CORE_PLL_BP = 0.

XO_STS_OUT[11:0] O 2.5VCMOS

Link Status [11]: Port 11 (0: active 1:link down) . . . . . . [1]: Port 1 (0: active 1:link down) [0]: Port 0 (0: active 1:link down)

SCAN mode (XI_SMODE=1) : [3:0] Scan Out (SO[3:0])

JTAG Port (5 pins)

XI_TCK I 2.5VCMOS JTAG test clock input.

XI_TMS I 2.5VCMOS JTAG test mode select input.

XI_TDI I 2.5VCMOS JTAG test data input.

XI_TRST I 2.5VCMOS JTAG test reset input.




MB87Q3141

XO_TDO O 2.5VCMOS JTAG test data output.

XAUI Test Pins (21 pins)

XI_HTSI I 2.5VCMOS Serial Data input

XI_HTRSTX I 2.5VCMOS Test Register Reset

XI_HTMODE I 2.5VCMOS Test Mode Select (1: Test mode 0: Normal)

XI_HTCLK I 2.5VCMOS Test Data Clock for Test Register

XI_HTSCP I 2.5VCMOSTest Data Capture(1: Capture mode 0: Data Shift mode)

XI_HTSUP I 2.5VCMOS Status Update

XI_HTSCK I 2.5VCMOS Scan Clock

XO_HTSO O 2.5VCMOS Serial Data output

XO_HTCLKO O 2.5VCMOS Monitor clock output

XO_HTPRO[7:0] O 2.5VCMOS Monitor data output

XI_IBCNT[2:0] I 2.5VCMOS Current Bias Configuration.

XI_BSTEST I 2.5VCMOS BSR control. (0: normal 1: test)

Clock, Reset and Test(18 pins)

XI_PLL_CLK_P0 ILVDS(156MHz)

External clock input for core logic and XAUI SerDes Port 0, 1, and 2. (differential, pos)

XI_PLL_CLK_N0 ILVDS(156MHz)

External clock input for XAUI SerDes Port 0, 1, and 2. (differential, neg)


External clock input for XAUI SerDes Port 3, 4, and 5. (differential, pos)











XI_RESET_N I 2.5VCMOS Reset input for hardware reset. (active low)

XI_RESET_PLL_N I 2.5VCMOS Reset input for core and XAUI SerDes PLLs (active low)

XI_CORE_TCK I 2.5VCMOS Auxiliary core clock input for test mode.

XI_XAUI_TCK[1:0] I 2.5VCMOSAuxiliary clock input for test mode.[1] alternate source synchronous clock for XAUI ports.[0] alternate recovered clock for XAUI ports.

XI_SMODE I 2.5VCMOS SCAN mode0: normal operation1: test mode

XI_CORE_PLL_BP I 2.5VCMOS 0: normal operation1: bypass core PLL for test operation

XI_XAUI_PLL_BP I 2.5VCMOS 0: normal operation1: bypass XAUI PLL for test operation




Chip Specification

XI_VPD1 I 2.5VCMOS 0: normal operation1: test mode

XI_VPD2 I 2.5VCMOS 0: normal operation1: test mode

Power Pins

VDE +2.5V 2.5V power supply for IO.

VDD +1.2V 1.2V power supply for core logic.

VSS GND Common ground.

VDP +2.5V 2.5V power supply for XAUI SerDes

VDN +1.2V 1.2V power supply for XAUI SerDes

VDR+1.67Vanalog

1.67V termination for XAUI SerDes

VSN GND Ground for XAUI SerDes

VDI1 +1.2V 1.2V power supply for core PLL

VSI1 GND Ground.for core PLL




MB87Q3141
Chapter 7: Mechanical DescriptionThis chapter describes the pin assignments and the mechanical specifications.
7.1 Dimensions

The mechanical specifications are shown in Table 7-7.

Table 7-7. Package information

Parameter Value

Package type FC-BGA (Flip Chip Ball Grid Array)

Total pin count 728

Package size 35 x 35 sq mm

Ball pitch 1.27 mm

Thermal Resistance(deg.C/W)

θjc = 0.40θja = 8.58 (0m/s air), 5.34 (1m/s air), 3.80 (3m/s air)

Preliminary & Confidential

Drawing Details for CBGA 728

Dimensions in millimeters

35.00 ±0.20 SQ.

4–C3.0

3–C0.5 1.27

0.99

0.99

A

B

1.27

33.02 Ref.

33.0

2 R

ef.

2.45

728–

Ø0.

75 ±

0.15

Ø0.

30S

AB

1.60

0.60

±0.

10

0.65

±0.

30

B–C0.25

0.20

S

S

AISIC LID

C1.5 INDEX Mark Area

30.00 ±0.40 SQ.


Chip Specification
7.2 Pin Organization
MB87Q3141 package pins [version 1.2b 4/6/04]

BOTTOM VIEW FCBGA728index A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG

123456789

101112131415161718192021222324252627

NC

VSS (Gnd)VDD (1.2V) outer sideVDE (2.5V, IO)VSN (Gnd fo r HSIO) Chip Area

VDP (2.5V fo r HSIO)VDN (1.2V fo r HSIO)VDR (1.67V, Termination for HSIO)different ial (HSIO)different ial (c lock)single-ended XAUI Port

inner side

RX3-

RX3+

RX1-

RX1+

RX2-

RX2+

RX0-

RX0+

TX3-

TX3+

TX1-

TX1+

TX2-

TX2+

TX0-

TX0+


MB87Q3141
7.3 Pin Listing
Table 7-8. Package Pin List (1)

pi n nam e pin na m e pi n nam e pin na m e pi n nam e pin na m e

B1 XI_P 00_RXP [ 0] T2 V SS C4 V DR U5 XI_C ONF IG[ 3] D7 XO_P01_TXN[ 1] V 8 V SSC1 V SN U2 XI_C ONF IG[ 0] D4 XO_P00_TXP [ 3 ] V 5 XI_C ONFIG[ 7] E7 XO _P01_TXP [ 2 ] W8 V DDD1 V DP V 2 XI_C ONFIG [ 4] E4 XO_P00_TXN[ 2] W5 XI_P IF _M ODE[ 3] F7 V DP Y8 V SSE1 XO_P00_TXP [ 0 ] W2 XI_P IF_M ODE[ 0] F4 V SN Y5 XI_T DI G7 XI_P LL _C LK_P0 A A 8 V DDF1 VD N Y2 XI_HT SI G4 XO_HTP RO [ 3 ] AA5 VS S H7 V DE AB8 V DPG1 XO_HTP RO [ 0 ] A A 2 XO_TEST _O UT[ 5] H4 XO _HTC LKO A B5 V SN J 7 XO_HT SO A C8 XO_P 07 _TXP [ 2 ]H1 XO_HTP RO [ 4 ] A B2 V DN J 4 XO_TEST_O UT [ 2] A C5 XO _P06_TXN[ 0] K7 V DE A D8 XO_P 07 _TXN[1 ]J 1 XO_TEST_O UT[ 8] A C2 V SN K4 XO_STS_OUT [ 2 ] A D5 XO _P06_TXP [ 1 ] L7 X I_HT SC K AE 8 V SNK1 XI_HT SUP A D2 XO_P06_TXN[ 3] L4 XO_STS_OUT [ 6 ] A E5 V DN M7 V DE A F8 XI_P 07_R XP [ 2]L1 XI_HT CL K A E2 V SN M4 XO_STS_OUT [ 10] A F5 XI_P 06_RXN[ 0 ] N7 XI_RESET _PL L_N A G8 XI_P07 _RXN[ 1 ]M1 XI_HT MO DE A F2 V DP N4 V SI1 A G5 XI_P 06_RXP [ 1] P7 V DE A 9 XI_P 01_RXN[ 3 ]N1 XI_SMO DE A G2 XI_P06_RX N[ 3] P4 V DD A 6 XI_P0 1_RX P[ 1] R7 XI_RESET_N B 9 XI_P0 2_RXP[ 0]P1 X I_V PD 2 A 3 XI_P00_RX N[ 1] R4 V SS B 6 XI_P0 1_RX N[ 0] T7 V DE C9 V SNR1 VD D B 3 XI_P00_RXP[ 2] T4 VD I1 C6 VD N U7 XI_TC K D9 XO_P01_TXN[ 3]T1 XI_V P D1 C3 V SN U4 XI_C ONFIG[ 2] D6 XO _P01_TXP [ 1 ] V 7 V DE E9 XO _P02_TXP [ 0 ]U1 XI_XA UI_TC K[ 1 ] D3 XO_P00_TXN[ 1] V 4 XI_C ONF IG[ 6] E6 XO_P01_TXN[ 0] W7 X I_T RST F9 V DNV 1 XI_IB C NT[ 1] E3 XO_P00_TXP [ 2 ] W4 XI_PIF_MOD E[ 2] F6 V SN Y7 V DE G9 V SSW1 XI_B ST EST F3 V DP Y4 XO _TDO G6 XI_P LL _C LK_N0 A A 7 XI_P LL _C LK_N2 H9 V DDY1 XI_HT RST X G3 XO_HTP RO [ 2 ] A A 4 XO _TEST _O UT[ 7] H6 V DD A B7 V SN J 9 V SSAA1 XO_TEST_O UT[ 4] H3 XO_HTP RO [ 7 ] A B4 VDP J 6 V SS AC 7 XO_P07_TXN[ 2] K9 VD DA B 1 V SN J 3 XO _TEST _O UT[ 1] A C4 XO_P06_TXP [ 2 ] K6 XI_HT SCP A D7 XO_P07_TXP [ 3 ]L 9 V SSA C1 V DN K3 XO_STS_OUT [ 1 ] A D4 XO_P06 _TXN[ 1] L6 V SS A E7 V DR M9 V DDAD 1 V SN L3 XO_STS_OUT[ 5 ] A E4 VS N M6 NC2 AF7 XI_P 07_RXN[ 2 ] N9 VS SA E1 V DP M3 XO _STS_OUT[ 9 ] A F4 XI_P 06_RXP [ 2] N6 V SS A G7 XI_P 07_RXP[ 3] P9 V DDA F1 V DN N3 V SS A G4 XI_P 06_RXN[ 1 ] P6 V DD A 8 XI_P 01_RXP [ 3] R9 V SSA G1 V SN P3 XI_CORE_T CK A 5 XI_P0 0_RX N[ 3] R6 V SS B 8 XI_P0 1_RX N[ 2] T9 V DDA 2 XI_P 00_RXP [ 1] R3 V DD B5 XI_P 01_RXP [ 0] T6 X I_IBC NT[ 0] C8 V DR U9 V SSB 2 XI_P00 _RXN[ 0 ] T3 X I_CORE_PLL _BP C5 V SN U6 V SS D8 XO_P01_TXP [ 3 ] V 9 V DDC2 V DN U3 XI_CONF IG[ 1] D5 XO_P00_TXN[ 3] V 6 XI _IBC NT [ 2] E8 XO_P01_TXN[ 2] W9 VSSD2 XO _P00_TXP [ 1 ] V 3 XI_CONF IG[ 5] E5 XO_P01_TXP [ 0 ] W6 V SS F8 V SN Y9 V DDE2 XO_P00_TXN[ 0] W3 XI_PIF_M ODE[ 1] F5 V DN Y6 VD D G8 V DD AA9 VSSF2 V SN Y3 XI_TMS G5 V SS A A 6 XI_P LL _C LK_P2 H8 V SS A B 9 V SNG2 XO_HTP RO [ 1 ] AA3 XO_TEST_O UT[ 6] H5 XO_HTP RO [ 5 ] A B6 VD N J 8 V DD AC 9 XO_P07_TXN[ 0]H2 XO _HTP RO [ 6 ] A B3 V SN J 5 XO_TEST _O UT [ 3] A C6 XO _P06_TXP [ 0 ] K8 V SS A D9 XO_P 07 _TXP [ 1 ]J 2 XO_TEST _OU T[ 0] A C3 XO_P06_TXN[ 2] K5 XO_STS_OUT [ 3 ] A D6 XO_P07 _TXN[ 3] L8 VD D A E9 VD NK2 XO_STS_OUT [ 0 ] A D3 XO _P06_TXP [ 3 ] L5 XO_ST S_OUT [ 7 ] A E6 V SN M8 V SS A F9 XI_P0 7_RX N[ 0]L2 XO_STS_OUT [ 4 ] A E3 V DR M5 XO_ST S_OUT [ 11] A F6 XI_P 06_RXP [ 0] N8 V DD A G9 XI_P07 _RXP[ 1]M2 XO_STS_OUT [ 8 ] A F3 XI_P 06_RXN[ 2 ] N5 V DD A G6 XI_P 07_RXN[ 3 ] P8 V SS A 10 XI_P0 2_RXP[ 1]N2 XI_XA UI_PL L_B P A G3 XI_P 06_RXP[ 3] P5 NC0P A 7 XI_P 01 _RXN[1 ] R8 V DD B 10 XI_P02 _RXN[ 0 ]P2 V SS A 4 XI_P 00_RXP[ 3] R5 NC 0N B7 XI_P 01_RXP [ 2] T8 V SS C10 V DNR2 XI_XA UI_TC K[ 0 ] B4 XI_P 00_RXN[ 2 ] T5 V SS C7 V SN U8 V DD D10 XO_P02_TXP [ 1 ]


Chip Specification

E1 0 XO_P02_TXN[ 0] W11 V SS F13 V DN Y14 V SS G1 6 V DD A A 17 VSSF1 0 V SN Y11 V DD G13 V SS AA14 V DD H16 V SS AB1 7 VDPG10 V DD AA11 V SS H13 V DD AB14 VD P J 16 VD D A C17 XO_P09_TXP [ 2 ]H10 V SS AB11 VSN J 13 VSS A C14 XO_P08_TXP [ 0 ] K1 6 V SS AD 17 XO_P09_TXN[ 1]J 10 V DD AC 11 XO_P08_TXN[ 2] K13 VDD A D14 V SN L16 V DD AE 17 VSNK1 0 V SS A D11 XO _P08_TXP [ 3 ] L13 V SS A E1 4 V DR M16 V SS A F17 XI_P 09_RXP [ 2]L10 V DD AE 11 VD R M13 VDD A F1 4 X I_P 08_RXP[ 0] N16 V DD AG 17 XI_P 09_RXN[ 1 ]M10 V SS A F11 XI_P 08_RXN[ 2 ] N13 V SS A G1 4 V DN P16 V SS A 18 XI_P 03_RXN[ 3 ]N10 V DD A G11 XI_P08 _RXP[ 3] P13 V DD A 15 XI_P03 _RXP[ 1] R16 V DD B 18 XI_P04 _RX P[ 0]P10 VSS A 12 XI_P 02_RXP[ 3] R13 VSS B 15 XI_P 03_RXN[ 0 ] T16 V SS C18 V SNR10 V DD B 12 XI_P 02_RXN[ 2 ] T13 V DD C15 V DN U16 V DD D1 8 XO_P03_TXN[ 3]T10 V SS C12 V DR U13 VSS D15 XO _P03_TXP [ 1 ] V 16 VSS E18 XO_P04_TXP [ 0 ]U10 V DD D1 2 XO_P02_TXP [ 3 ] V 13 V DD E1 5 XO_P03_TXN[ 0] W16 V DD F18 VDNV 10 V SS E1 2 XO_P02_TXN[ 2] W13 V SS F15 V SN Y16 V SS G1 8 VDDW10 V DD F12 V SN Y13 V DD G15 V SS A A 16 V DD H18 VSSY10 V SS G12 V DD AA13 V SS H15 V DD AB16 VSN J 18 VDDAA10 V DD H12 V SS AB13 VS N J 15 VSS A C16 XO_P09_TXN[ 2] K1 8 VSSAB10 VDN J 12 VDD A C13 XO_P08_TXN[ 0] K1 5 V DD AD16 XO_P09_TXP [ 3 ] L18 VDDAC10 XO_P07_TXP [ 0 ] K12 VSS A D13 XO_P08_TXP [ 1 ] L15 V SS AE 16 VD R M18 VSSAD10 XO _P08_TXN[ 3] L12 V DD A E1 3 V DN M15 V DD A F16 XI_P 09_RXN[ 2 ] N18 VDDAE10 VS M12 VSS A F13 XI_P 08_RXN[ 0 ] N15 V SS AG 16 XI_P 09_RXP[ 3] P18 VSSAF10 XI_P07 _RXP[ 0] N12 V DD A G13 XI_P 08_RXP[ 1] P1 5 V DD A 17 XI_P 03_RXP[ 3] R18 VDDAG10 XI_P08 _RXN[3 ] P12 V SS A 14 V DN R15 V SS B 17 XI_P03 _RXN[2 ] T18 VSSA 11 XI_P 02_RXN[ 1 ] R12 VD D B 14 XI_P 03_RXP[ 0] T15 V DD C17 V DR U18 VDDB 11 XI_P 02_RXP[ 2] T12 V SS C14 V DR U15 VS S D17 XO _P03_TXP [ 3 ] V 18 VSSC11 V SN U12 V DD D1 4 V SN V 15 V DD E1 7 XO_P03_TXN[ 2] W18 VDDD11 XO_P02_TXN[ 1] V 12 V SS E1 4 XO_P03_TXP [ 0 ] W15 V SS F17 V SN Y18 VSSE1 1 XO_P02_TXP [ 2 ] W12 V DD F14 V DP Y15 V DD G17 V SS A A 18 VDDF1 1 V DP Y12 V SS G14 V DD AA15 V SS H17 V DD AB18 VSNG11 V SS AA12 V DD H14 V SS AB15 VDN J 17 VS S A C18 XO_P09_TXN[ 0]H11 V DD AB12 VDP J 14 VD D A C15 V DN K1 7 V DD AD18 XO_P09_TXP [ 1 ]J 11 V SS A C12 XO _P08_TXP [ 2 ] K14 V SS A D15 XO_P09_TXN[ 3] L17 V SS A E18 V DNK1 1 V DD A D12 XO _P08_TXN[ 1] L14 V DD A E1 5 V SN M17 V DD A F18 XI_P 09_RXN[ 0 ]L11 V SS A E12 V SN M14 V SS A F15 V SN N1 7 V SS A G18 XI_P 09_RXP [ 1]M1 1 V DD A F12 XI_P08 _RXP[ 2] N14 V DD A G15 XI_P 09_RXN[ 3 ] P1 7 V DD A 19 XI_P 04_R XP [ 1]N1 1 V SS A G12 XI_P 08_RXN[ 1 ] P14 V SS A 16 XI_P 03_RXN[ 1 ] R17 V SS B 19 XI_P 04_RX N[ 0 ]P11 VDD A 13 XI_P 02_RXN[ 3 ] R14 VD D B 16 XI_P 03_RXP[ 2] T17 V DD C19 V DNR11 V SS B13 V SN T14 V SS C16 V SN U1 7 V SS D19 XO_P04_TXP [ 1 ]T11 V DD C13 V SN U14 V DD D1 6 XO_P03_TXN[ 1] V 17 V DD E1 9 XO_P04_TXN[ 0]U1 1 V SS D13 XO_P02_TXN[ 3] V 14 V SS E1 6 XO_P03_TXP [ 2 ] W17 V SS F19 V SNV 11 V DD E13 V DN W14 V DD F16 V DP Y17 V DD G19 V SS


MB87Q3141

H19 V DD AB20 VS N J 22 VS S A C23 XO_P10_TXP [ 0 ] K2 5 XB_P ER_DA TA [ 17 ] AD26 XO_P1 1_TXP [ 1 ]J 19 VSS A C20 XO _P10_TXN[ 2] K22 NC 8 A D23 XO_P11_TXN[ 3] L25 XB_P ER_DA TA [ 12 ] AE26 V DNK1 9 V DD A D20 XO _P10_TXP [ 3 ] L22 V SS A E2 3 V SN M25 XB_P ER_DA TA [ 7] A F26 XI_P 11 _RXN[ 0 ]L1 9 VSS A E20 V DR M22 NC10 A F23 XI_P10 _RXP[ 0] N25 V DD A G26 XI_P 11_RXP[ 1]M1 9 V DD A F20 XI_P10 _RXN[2 ] N22 V SS A G23 XI_P 11_RXN[ 3 ] P2 5 XB _P ER_DA TA [ 2] A27 V SNN19 VSS A G20 XI_P 10_RXP[3 ] P22 NC11 A 24 XI_P0 5_RX N[ 1] R25 XB _PE R_DP[2 ] B 27 VDNP19 VD D A 21 XI_P 04_RXP[ 3] R22 VSS B 24 XI_P 05_RXP[ 2] T25 XI_P ER_ICT RL [ 4 ] C 27 V DPR19 VSS B 21 XI_P0 4_RX N[ 2] T22 NC12 C24 V SN U25 XI_P ER_ICT RL [ 0 ] D27 V SNT19 V DD C21 V DR U22 V SS D2 4 XO_P05_TXN[ 1] V 25 XI_P ER_A DDR [ 3] E27 V DNU19 VSS D21 XO _P04_TXP [ 3 ] V 22 XB_ EEDIO E24 XO_P05_TXP [ 2 ] W25 XI_P ER_A DDR[8 ] F27 V SNV 19 V DD E2 1 XO_P04_TXN[ 2] W22 V SS F24 V DP Y25 XI_P ER_A DDR [ 12 ] G27 XB _P ER_D AT A[ 30 ]W19 VSS F21 V SN Y22 V DD G2 4 XO_PER_IR Q_N[ 2 ] A A 25 XB_M DIO H2 7 XB_P ER_DA TA [ 25]Y19 V DD G21 XI_P LL _C LK_N1 AA22 XI_P LL _C LK_N3 H24 XB_P ER_DA TA [ 28 ] AB25 VD P J 27 XB _P ER_DAT A[ 20 ]AA19 VSS H21 V DE AB22 VS N J 24 XB _P ER_DAT A[ 23 ] A C25 XO_P11_TXP [ 2 ] K2 7 XB_P ER_DA TA [ 15 ]AB19 VDN J 21 XB _P ER_DAT A[ 29 ] A C22 XO_P10_TXN[ 0] K2 4 XB_P ER_DA TA [ 18 ] AD25 XO_P1 1_TXN[ 1] L2 7 XB _P ER_DA TA [ 10 ]A C19 XO_P09 _TXP [ 0 ] K21 V DE A D22 XO_P10_TXP[ 1] L24 XB _PE R_DA TA [1 3] A E25 V SN M27 XB_P ER_DA TA [ 5]A D19 XO_P10 _TXN[3 ] L21 NC9 A E22 V DN M24 XB _PE R_DA TA [8 ] A F25 XI_P1 1_RX P[ 2] N27 V DDAE 19 VSN M21 VD E A F2 2 XI_P 10_RXN[ 0 ] N24 VSS AG25 XI_P 11_RXN[ 1 ] P27 XB _P ER_DA TA [ 0]A F19 XI_P 09_RXP [ 0] N21 XI_P ER _CL K A G22 XI_P 10_RXP [ 1] P24 XB_ P ER _DA TA [ 3 ] A 26 XI_P 05_RXN[ 3 ] R27 XO_PER_O CT RL [ 2 ]A G19 XI_P 10_RXN[ 3 ] P21 V DE A 23 XI_P 05_RXP [ 1] R24 XB_ P ER _DP[ 1] B2 6 V DP T27 XO_PER_O CT RL [ 0 ]A 20 XI_P 04_RXN[ 1 ] R21 XI_P ER_RESET _N B 23 XI_P 05_RXN[ 0 ] T24 XI_P ER _ICT RL [ 2 ] C26 V SN U27 XI_P ER_TSIZ[ 0]B 20 XI_P 04_RXP[ 2] T21 V DE C23 V DN U24 XI_P ER_IC T RL [ 1 ] D2 6 XO_P05_TXN[ 3] V 27 XI_P ER _A DDR [ 5]C20 VSN U2 1 NC13 D23 XO _P05_TXP [ 1 ] V 24 XI_P ER _A DDR[ 2] E26 V SN W27 XI_P ER _A DDR [ 10 ]D20 XO_P0 4_TXN[ 1] V 21 V DE E23 XO_P0 5_TXN[ 0] W2 4 XI_P ER_A DDR[ 7] F26 V DN Y2 7 XI_P ER_A DDR [ 14 ]E20 XO_P04_TXP[ 2] W21 XB _EEC LK F23 V SN Y24 XI_PE R_A DDR[1 1] G26 XB _PE R_DA TA [ 31 ] AA27 XI_P ER_AD DR[ 15 ]F2 0 V DP Y21 V DE G23 V SS AA24 XO_MDC H26 XB _P ER_DAT A[ 26 ] A B27 V DNG20 V DD AA21 XI_P LL _C LK_P3 H23 NC7 AB24 VSN J 26 XB _P ER_DAT A[ 21 ] A C27 XO_P1 1_TXP [ 0 ]H20 V SS AB21 VD P J 23 XB _P ER_DAT A[ 24 ] A C24 XO_P11_TXN[ 2] K2 6 XB_P ER_DA TA [ 16 ] A D27 V DPJ 20 V DD A C21 XO_P10_TXP [ 2 ] K23 XB_ P ER _DA TA [ 19 ] A D24 XO_P11_TXP [ 3 ] L26 XB _P ER_DAT A[ 11 ] A E27 V SNK2 0 V SS A D21 XO_P10_TXN[ 1] L23 XB_ P ER _DA TA [ 14 ] A E2 4 V DR M26 XB_P ER_DA TA [ 6] A F27 XI_P11 _RXP[ 0]L20 V DD AE 21 VS N M23 XB _P ER_DAT A[ 9] AF24 XI_P 11_RXN[ 2 ] N26 VS S A G27 V SNM2 0 V SS A F21 XI_P10 _RXP[ 2] N23 V DD A G24 XI_P 11_RXP[ 3] P2 6 XB _P ER_DA TA [ 1]N20 V DD AG21 XI_P 10_RXN[ 1 ] P23 XB _P ER_DAT A[ 4] A25 XI_P 05_RXP[ 3] R26 XB_P ER _DP[ 3]P20 V SS A 22 XI_P 04_RXN[ 3 ] R23 XB_P ER_DP[ 0] B 25 XI_P 05_RXN[ 2 ] T26 XO _PER _OC TR L [ 1 ]R20 VDD B 22 XI _P 05_RXP[ 0] T23 XO_PER_IRQ_N[ 0 C25 V DR U26 XI_P ER_CS_NT20 VSS C22 V SN U23 XI_P ER_ICT RL [ 3 ] D25 XO _P05_TXP [ 3 ] V 26 XI_P ER_A DDR[ 4]U20 VDD D22 XO _P04_TXN[ 3] V 23 XI_P ER_TSIZ [ 1] E25 XO_P05_TXN[ 2] W26 XI_P ER_A DDR [ 9]V 20 VSS E2 2 XO_P05_TXP [ 0 ] W23 XI_P ER_A DDR [ 6] F25 V SN Y26 XI_P ER _A DDR [ 13 ]W20 VDD F22 V DN Y23 XI_RE G_CK G25 XO_PER_IRQ_N[ 1] A A 26 XB _RE G_DIOY20 VSS G22 XI_P LL _C LK_P1 AA23 V SS H25 XB_P ER_DA TA [ 27 ] AB26 VS NAA2 0 VDD H22 V DD AB23 VD N J 25 XB _P ER_DAT A[ 22 ] A C26 XO_P11_TXN[ 0]


Chip Specification


MB87Q3141
Chapter 8: Electrical Description
8.1 Absolute Maximum Ratings

8.2 Recommended Operating Conditions

Table 8-11. Absolute Maximum Ratings

Parameter Symbol Ratings Units Notes

Power supply voltage

1.2VVDDVDNVDI1

-0.5 to 1.8 V

1.67V VDR -0.5 to 3.6 V

2.5VVDEVDP

-0.5 to 3.6 V

Input Voltage

2.5V IO

VI

-0.5 to VDE + 0.5 V apply to LVDS and eXAUI

3.3V Tol.2.5V IO

-0.5 to 4.0 V

Storage temperature Tj -40 to 125 oC

Table 8-12. Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Units Notes

Power supply voltage

1.2VVDDVDNVDI1

1.14 1.2 1.26 V 1.2V ±5%

2.5VVDEVDP

2.37 2.5 2.63 V 2.5V ±5%

1.67V VDR 1.53 1.67 1.75 VeXAUI input termination voltage, 2/3 of VDP

H level input voltage

2.5V IO

VIH

1.7 - VDE+0.3 V

3.3V Tol.2.5V IO

1.7 - 3.9 V

L level input voltage

2.5V IO

VIL

-0.3 - 0.7 V

3.3V Tol.2.5V IO

-0.3 - 0.7 V

Operating temperature(Ambient)

TA 0 70 oC


Chip Specification
8.3 3.3V Tolerant 2.5V CMOS Electrical Specifications
AC specification for I2C interface follows “THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000.AC specification for MDIO interface follows “IEEE P802.3ae”.

8.4 Reference Clock Input (LVDS) Electrical Specifications

Table 8-13. DC specification

Parameter Symbol Minimum Typical Maximum Unit Notes

Supply current IDDS V

H-level output voltage VOH VDE-0.2 - VDE V IOH=-100µA

L-level output voltage VOL 0 - 0.2 V IOL=100µA

Input leakage current IIN 10 µA

Input capacitance CIN 20 pF

Table 8-14. AC specification for Processor Interface

Parameter Symbol Minimum Maximum Unit Notes

Processor Bus Frequency CLKCPU 33 50MHz

XI_PER_CLK

Clock to Output Data Valid tDVALID 2.3 10.4 ns maximum CLOAD = 50pF

Clock to Output Tri-State tDTS 1.4 ns CLOAD = 0pF

Input Setup Time tISETUP 2.3 ns

Input Hold Time tIHOLD 0.1 ns



Differential Voltage VAMP 100 mV

Common Voltage VCOM 0.85 1.55 V

Table 8-16. AC specification


Operation frequency CLKOSC156.25MHz- 100ppm

156.25MHz+ 100ppm

MHz


MB87Q3141
8.5 Non-XAUI (2.5V CMOS) Electrical Specifications
8.6 Enhanced-XAUI Electrical Specifications



Supply current IDDS V

H-level output voltage VOH VDE-0.2 - VDE V IOH=-100µA

L-level output voltage VOL 0 - 0.2 V IOL=100µA

Input leakage current IIN 10 µA

Input capacitance CIN 20 pF

Pull up/Pull downresistance

RP 33 kΩ

Table 8-18. DC Specification

Parameter Symbol Min Typ Max Unit Notes

TX common mode voltage Vocm 1 1.3 1.6 V Vocm=VDP*1.3/2.5

TX differential peak-to-peak output voltage

Vo 800 1600 mV

RX input sensitivity Vrsense 25 800 mV Defined as single-ended

Table 8-19. AC Specification

Parameter Symbol Min Typ Max Unit Notes

TX transmission data rate ftxd 3.125 Gbps ±100ppm

TX differential output return loss RLtxd dB≥10 (100MHz≤f<625MHz)≥10-10*log(f/625) (625MHz≤f≤2GHz)

TX transition time Trise/fall 60 130 ps

TX output total jitter Tjt 0.35 UI

TX output deterministic jitter Tjd 0.17 UI

Receiving data rate frxd 3.125 Gbps ±100ppm

RX differential return loss RLrxd dB≥10 (100MHz≤f<625MHz)≥10-10*log(f/625) (625MHz≤f≤2GHz)

RX input jitter tolerance Rjt 0.65 UI


Chip Specification
8.7 Power Dissipation
Tx: default Rx: Rx Equalizer bypass (RXCTL[7:2] = 000000b)

8.8 Reset Sequence

The reset sequence is defined for the following external pins.

XI_RESET_N XI_RESET_PLL_N XI_CORE_PLL_BP XI_XAUI_PLL_BP XI_SMODE

Figure 8-1 shows the reset sequence using these external pins and Table 8-21 shows AC specification for the reset sequence.

Figure 8-1. Reset Sequence

Note that MPC should not issue bus transaction to MB87Q3141 while XI_RESET_N is 0 and within 32ns after the rising edge of XI_RESET_N.

Table 8-20. Power Dissipation


Power Dissipation PD 16.0 W Total power dissipation

1.2V for core PVDD 6.6 W 100% traffic

2.5V for I/O PVDE 0.1 W

1.2V for eXAUI SerDes PVDN 4.6 W

2.5V for eXAUI SerDes PVDP 4.7 W

1.2V for PLL PVDI1 0.0 W

Table 8-21. AC Specification for Reset Sequence

Parameter Min. Value Max. Value Description

Tpll_res 1 us N/A PLL reset time.

Tm_res 100 us N/A Master reset time.

Tsetup_bp 5 ns N/A Setup. Bypass PLL to PLL reset rising edge.

Power Stable

VDD, VDE, VDRVDN, VDP, VDI1

Tpll_res Tm_res

Tsetup_bp

XI_RESET_N

XI_RESET_PLL_N

XI_*_BPXI_SMODE


MB87Q3141
Chapter 9: Appendix
9.1 Supported Frame Formats

Figure 9-2 and Figure 9-3 show the supported frame formats.

Figure 9-2. Supported Frame Formats (1/2)

DA SA Type

6 6 2

“Ethernet”

DA SA Length

6 6 2 1 1

DS

AP

SS

AP

Ctr

l TypeSNAP OUI

1 3 2

AA AA 03 00 00 00

0800 (IPv4)

<=05DC

DA SA Type

6 6 2

0800 (IPv4)

VLAN

2 2

8100

VLANprotocol control

“Ethernet”

“RFC_1042”

w/o VLAN tag

w/o VLAN tag

w VLAN tag

User VLANDA SA

6 6

Tagged FrameVLAN

2 2


VLAN

2 2

8100


(UserVPID)

DA SA Length

6 6 2 1 1

DS

AP

SS

AP

Ctr

l TypeSNAP OUI

1 3 2

AA AA 03 00 00 00<=05DC

“RFC_1042”w VLAN tag VLAN

2 2

8100


86DD (IPv6)

IP header

IP header

IP header

86DD (IPv6)

IP header


Chip Specification

Figure 9-3. Supported Frame Formats (2/2)

Note: 802.3 LLC encapsulated frames other than above are supported but DiffServ can not be used

“BPDU” DA SA Length

6 6 2 1 1

DS

AP

SS

AP

Ctr

l

1

“GVRP”

“GMRP”

01-80-C2-00-00-00

01-80-C2-00-00-21

01-80-C2-00-00-20

DA SA Length

6 6 2 1 1D

SA

P

SS

AP

Ctr

l

1

DA SA Length

6 6 2 1 1

DS

AP

SS

AP

Ctr

l

1

2

BPDU

42 42 03

Protocol Id

0001

Messages

2

Protocol Id

0001

Messages

2

Protocol Id

0000

“PAUSE” DA SA Type

6 6 2

8808 01-80-C2-00-00-01

2

Opcode Parameters

0001

“GMRP”

01-80-C2-00-00-20

DA SA Length

6 6 2 1 1

DS

AP

SS

AP

Ctr

l

1

42 42 03

2

Protocol Id

0001

Messages

w/o VLAN tag

w VLAN tagVLAN

2 2

8100


42 42 03

42 42 03


MB87Q3141

9.2 VLAN ID Routing

9.2.1 Key Idea

Each station has a unique VLAN ID; thus, VLAN ID specifies only one unique destination in the network.

Supporting up to 4094 nodes including broadcast addresses.

9.2.2 Switch Configuration

VLAN enabled.

Ingress check off.

Learning disabled.

Aging disabled.

MAC address table is all invalid.

VLAN address table:- Tagging on for outputs.- USE: output port (one hot vector) to reach the corresponding destination station.

9.2.3 How does it work ?

Because ingress check is off, an incoming frame is allowed to egress.

Because the MAC table is all invalid, the switch broadcast the frame to the destination VLAN member. Consequently, the frame is for-warded toward the destination node.

Based on the network topology, the forwarding route can be pre-programmed.

9.2.4 How is it used ?

The source station specifies the destination station ID in the VLAN ID field.

The priority field can be used as it is for QoS purpose.

9.2.5 Benefits

Static destination routing

Static load balancing

Efficient broadcast (based on the network topology).


Chip Specification

9.2.6 Example of VLAN ID Table setup

Figure 9-4. Example of VLAN ID Table Setup

9.2.7 Source-Port_Based Fixed Routing

Configure the switch for VLAN ID Routing- Set Tagging Off for the output ports

Set the Default VLAN ID field as the destination port ID.

Send untagged frame, or tagged frames with VLAN ID being null or default.- Default VLAN ID and Default Priority is picked up and used.

0

1

2

3

2

2

3

3

1000

1001

1002

1003

1004

1005

1006

1007

0

1

2

3

0

0

1

1

2

3

0

1

1000

1001

1002

1003

1004

1005

1006

1007

0

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3

2

3

0

1

2

2

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3

1000

1001

1002

1003

1004

1005

1006

1007

0

1

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0

0

1

1

0

1

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1000

1001

1002

1003

1004

1005

1006

1007

0

1

2

3

Node- 1000

Node- 1001

Node- 1002

Node- 1003

Node- 1004

Node- 1005

Node- 1006

Node- 1007


Revision History

Revision Date Description

1.0 5/23/06 Release 1.0

FUJITSU MICROELECTRONICS AMERICA, INC.Corporate Headquarters1250 East Arques Avenue, M/S 333, Sunnyvale, California 94088-3470Tel: (800) 866-8608 Fax: (408) 737-5999E-mail: [email protected] Web Site: http://www.fma.fujitsu.com Confidential

©2006 Fujitsu Microelectronics America, Inc. All rights reserved.

All company and product names are trademarks or registered trademarks of their respective owners.

Printed in U.S.A.

10GE-DS-21179-3/2006

Documents

Ethernet Switch Chip Specification - fujitsu.com€¦ · Confidential MB87Q3141 Chip Speciﬁcation Overview This speciﬁcation describes the 3rd generation Fujitsu 10Gbps Ethernet