ESE 570 Chip Input and Output (I/O) Circuitsese570/spring2015/ESE570_IO... · 2015-04-16 · Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 2 OVERVIEW 1. INPUT PADS

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15

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ESE 570 Chip Input and Output (I/O) Circuits


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OVERVIEW 1. INPUT PADS – ESD PROTECTION

2. TTL-TO-CMOS LOGIC LEVEL SHIFTING

3. DIFFERENTIAL SIGNALING

4. OUTPUT PADS – L di/dt NOISE

5. BIDIRECTIONAL I/O PADS

6. ON-CHIP CLOCK GENERATION AND DISTRIBUTION

7. LATCH-UP PROTECTION IN OUTPUT PADS


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ESD PROTECTION

DUTV

esd

1 MΩCharged-Device Model (CDM)

Bulk or Ground

Pin

Blow resistance, low inductance probe

Simulates ESD phenomena of packaged ICs during manufacturing and assembly.

Machine Model (MM)Human Body Model (HBM)

Electrostatic charge builds up on a chip due to improper grounding and then dischargeswhen a low-resistance path becomes available.


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time (ns)

curre

nt I

(A)

1.4

00 100 200

SPICE-generated short-circuit HBM output current waveformspecified by MIL-STD 883.C/3015.7 for C

c

charged to 2kV

After exposure to the ESD waveform, a failed IC exhibits latch-up or fails one or more data sheet specifications.

ATE HBM ESD and MM ESD TEST SETUP


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TYPICAL ESD PROTECTED INPUT PAD

or 8A ≥ I ≥ 2.6 A.

VDD

I

200 Ω ≤ R ≤ 3 k Ω

R


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INPUT PAD WITH SERIES TRANSMISSION GATE


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INVERTING INPUT PAD WITH TTL-TO-CMOS LEVEL SHIFT

TTL

CMOS

VDD

= 5 V

= 0.8VDD

= 0.3VDD


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8xVARIATIONS IN LEVEL-SHIFT VTC DUE TO PROCESS VARIATIONS


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WORST CASE SIMULATION METHOD


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TransmitterReceiverTwo-wire pair

Terminator

Differential Signaling System

I = +i

I = -i

Input PulseOutput Pulse

Noise Noise Reduction


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DIFFERENTIAL SIGNALING (LOGIC LEVELS) FOR GBPS SYSTEMS

VOL 1.000 V

1.400 V0.400 V

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1.400 V

1.100 V

1.220 V


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OUTPUT PADS

CK or ST

0 x 1 0 High Z

MN1

MN2

MP2

MP1

CK = 0 => MN2 & MP2 OFF => Z = HIGH ZCK = 1 => MN2 & MP2 ON => Z = D

CK D P N Z1 1 0 0 1 = D1 0 1 1 0 = D0 x 1 0 HIGH Z


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OUTPUT PADS – L di/dt NOISE

I maxt s /2

assume C

load

charged to V

DD

Cload


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OUTPUT PADS – L di/dt NOISE

REDUCE NOISE => lower VDD

or increase ts -> limits speed


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OUTPUT PADS – REDUCE L di/dt NOISE


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DIFFERENTIAL DRIVER OUTPUT PAD

tD Delay Element

tD

A = IN (t - tD)

VDD

/2

“1” “1”

“0”

“1”“1”“0”

Much reduced [di/dt]

max


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BIDIRECTIONAL I/O PAD WITH TTL INPUT CAPABILITY

E = 1 => Z = DE = 0 => X = high ZE = 0 => DI = Z

XE = 1D

D

E = 0

1

0


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Clock System Architecture

● Chip receives external clock through I/O pad or an internal clock is included in the Clock Generator.

● Clock generator adjusts the global clock to the external clock.

● Global clock is distributed across the chip.

● Local drivers and “clock gaters” drive the physical clocks to clocked elements.

Global Clock


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ON-CHIP CLOCK GENERATION AND DISTRIBUTION


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TWO-PHASE CLOCK GENERATION


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Clock Skew and Jitter

• Clock should theoretically arrive simultaneously to all sequential circuits.

• Practically it arrives in different times. The differences are called clock skews.

• Most systems distribute a global clock and then use local “clock gaters” located near clocked elements.

• Skews result from paths mismatches, process variations and ambient conditions, resulting in physical clocks ≠ global clock.


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Clock Skew Components

Ideal Edge Location

Unit Interval

Edge Location Shifted

ReferenceEdge

Systematic is the portion of clock skew existing under nominal conditions. It can be minimized by appropriate design.

Random is variable portion of clock skew caused by random process variations like devices’ channel length, oxide thickness, threshold voltage, wire thickness, width and space. It can be measured on silicon and adjusted by DLL components.

Drift is time-dependent portion of clock skew caused by time-dependent environmental variations, occurring relatively slowly. Compensation of those must takes place periodically.

Jitter is rapid clock edge changes (deterministic and random components), occurring by power noise and clock generator jitter. It cannot be compensated.


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Input Clock

Output Clock

PD LF

VCO

Frequency/Phase Control

Input Clock Output

Clock

Clock Distribution & Buffers

PD LF Delay Control

Variable DelayLine

PLL

DLL

Clock Distribution & Buffers


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Some Representative Clock Distribution Networks


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H-TREE CLOCK DISTRIBUTION NET FOR UNIFORM CLOCK DISTRIBUTION

CAD Techniques automate the generation of hierarchical clock distribution networks.


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LATCH-UP IN CMOS CIRCUITSI S=

AE q Dnni2

N AWBJT saturation current

1NSUB

x * 1nMOS− pMOS spacing

+2


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IB1

IB2 I

C1 = β

1I

B1

IC2

= β2β

1I

B1

IB2

= IC1

IB1

= IC2

Rwell

= Rsub.=∞

time = t1 > 0:I

B1 = x => I

C1 = β

1 x

time = t2 > t1I

B2 = I

C1 = β

1 x => I

C2 = β

2β

1 x

LATCH-UP – POSITIVE FEEDBACK

β1β

2 ≤ 1

positive feedback! if β2β

1 ≥ 1

Latch-up Analysis with

Rwell

= Rsub

-=I CI B

)1 0(,=I CI E

(1

Bipolar Current Gains

-=,

1−,

-1-1=,1

1−,1

,2

1−,2≤1⇒,1',2≤1

.=∞

Prevent latch-up by reducing positive feedback


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LATCH-UP PREVENTION

VBE

,1',2≥ 1'

RTRwell

,1'RTRsub

,2

V DD

V BE−2

≤make small

Latch-up occurs if NOT satisfied

Reduce α1, α

2

Latch-up prevention with parasitic resistances R

well

and Rsub

; Decrease VDD


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OUTPUT BUFFER CELL LAYOUT WITH LATCH-UP PREVENTION

Documents

ESE 570 Chip Input and Output (I/O) Circuitsese570/spring2015/ESE570_IO... · 2015-04-16 · Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 2 OVERVIEW 1. INPUT PADS