Errata Lm3s9790

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S T E L L A R I S E R R A T A

Stellaris

LM3S9790 RevB1 Errata

This document contains known errata at the time of publication for the Stellaris

LM3S9790

microcontroller. The table below summarizes the errata and lists the affected revisions. See the

data sheet for more details.

See also the ARM Cortex-M3 errata, ARM publication number PR326-PRDC-009450 v2.0.

Revision(s) AffectedErratum TitleErratum

Number

B1JTAG INTEST instruction does not work1.1

B1The Recover Locked Device sequence does not work1.2

B1Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3Debug Access Port (DAP) is enabled

2.1

B1Sleep and Deep-Sleep mode not usable at higher speeds when ISRs reside in Flashmemory

2.2

B1Device Capabilities registers may not accurately reflect available signals2.3

B1Hibernation module may have higher current draw than specified in data sheet undercertain conditions

3.1

B1Hibernate POR may not reset the Hibernation module until VDD is applied3.2

B1Power consumption increases if VDD is not restored after wake from hibernation3.3

B1ESD protection on the VBAT pin does not meet specifications3.4

B1Use of the VDD3ON mode to initiate hibernation damages the part3.5

B1Hibernate module power consumption higher than expected in event wakeup configuration3.6

B1The Real-Time Clock gains or loses time going in and out of hibernation when using acrystal

3.7

B1Low-battery detect circuit is powered down during hibernate3.8

B1Cumulative page erases may introduce bit errors in Flash memory4.1

B1Flash Write Buffer does not function above 50 MHz4.2

B1Ethernet fails to connect when using the Boot loader software in ROM5.1

B1Some ROM functions are unsupported5.2

B1ROM mapping check for the Boot loader does not function properly5.3

B1Port B [1:0] pins require external pull-up resistors6.1

B1EPI dual-chip select function does not work7.1

B1EPI Host-Bus 16 mode does not work7.2

B1Clock signal in EPI General-Purpose mode is inverted7.3

B1UART Smart Card (ISO 7816) mode does not function8.1

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Revision(s) AffectedErratum TitleErratum

Number

B1When in IrDA mode, the UnRx signal requires configuration even if not used8.2

B1An interrupt is not generated when using DMA with the SSI module if the EOT bit is set9.1

B1Some bits in the I2SMCLKCFG register do not function10.1

B1I2S SCLK signal is inverted in certain modes10.2

B1Ethernet receive packet corruption may occur when using optional auto-clock gating11.1

B1Ethernet packet count decremented before the FCS is read11.2

B1Ethernet packet loss with cables longer than 50 meters11.3

B1Ethernet PHY interrupts do not function correctly11.4

B1USB0ID and USB0VBUS signals are required to be connected regardless of mode12.1

B1Latch up may occur if power is applied to the VBUS pin but not to VDD12.2

B1Power-on event may disrupt operation13.1

B1Momentarily exceeding VIN ratings on any pin can cause latch-up13.2

1 JTAG

1.1 JTAG INTEST instruction does not work

Description:

The JTAG INTEST (Boundary Scan) instruction does not properly capture data.

Workaround:

None.

Silicon Revision Affected:

B1

Fixed:

Fixed in Rev C.

1.2 The Recover Locked Device sequence does not work

Description:

If software configures any of the JTAG/SWD pins as GPIO or loses the ability to communicate with

the debugger, there is a debug sequence that can be used to recover the microcontroller, calledthe Recover Locked Device sequence. After reconfiguring the JTAG/SWD pins, using the Recover

Locked Device sequence does not recover the device.

Workaround:

To get the device unlocked, follow these steps:

1. Power cycle the board and run the debug port unlock procedure in LM Flash Programmer. DO

NOT power cycle when LM Flash Programmer tells you to.

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2. Go to the Flash Utilities tab in LM Flash Programmer and do a mass erase operation (check

"Entire Flash" and then click the Erase button). This erase appears to have failed, but that is

ok.

3. Power cycle the board.

4. Go to the Flash Utilities tab in LM Flash Programmer and do another mass erase operation

(check "Entire Flash" and then click the Erase button).


B1

Fixed:

Not fixed in Rev C.

2 System Control

2.1 Hard Fault possible when waking from Sleep or Deep-Sleep modes

and Cortex-M3 Debug Access Port (DAP) is enabledDescription:

If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low

power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals

have been restored to their run mode configuration. The DAP is usually enabled by software tools

accessing the JTAG or SWD interface when debugging or flash programming. If this condition

occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock.

Workaround:

A software delay loop can be used at the beginning of the interrupt routine that is used to wake up

a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that

accesses a peripheral register that might cause a fault. This loop can be removed for productionsoftware since the DAP is most likely not enabled during normal execution.

Since the DAP is disabled by default (power on reset), the user can also power cycle the device.

The DAP will not be enabled unless it is enabled through the JTAG or SWD interface.


B1

Fixed:

Will not be fixed.

2.2 Sleep and Deep-Sleep mode not usable at higher speeds whenISRs reside in Flash memory

Description:

Sleep and Deep-Sleep modes cannot be used when running the processor at 66 or 80 MHz when

the ISRs and vector table reside in Flash memory. If Sleep or Deep-Sleep mode is used at those

speeds, an invalid PC is sometimes returned for the interrupt vector address when exiting sleep

mode.

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Workaround:

There are two possible workarounds for this issue:

1. Store the ISRs and vector table in the on-chip SRAM when running the processor at 66 or 80

MHz.

2. Run the processor at 50 MHz.


B1

Fixed:

Fixed in Rev C.

2.3 Device Capabilities registers may not accurately reflect available

signals

Description:

Some of the Device Capabilities register bits reflect the presence of specific pins on the

microcontroller. These bits do not always properly reflect the available signals. Bits affected include

DC3 [31:0], DC4 [15:14], DC5 [27:24] and [7:0], and DC8 [31:0]. Do not rely on the value of these

bits in system design.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

3 Hibernation Module

3.1 Hibernation module may have higher current draw than specified

in data sheet under certain conditions

Description:

If a battery voltage is applied to the VBAT power pin prior to power being applied to the VDD power

pins of the device, the current draw from the VBAT pin is greater than expected. The current may

be as high as 1.6 mA instead of the data sheet specified 17 A. The condition exists until power isapplied to the VDD pin. Once the VDD pin has been powered, the VBAT current draw functions as

expected. The VDD pin can then be powered up and down as required and the VBAT pin current

specification is maintained.

Workaround:

The VBAT pin higher-than-specified current draw condition can be avoided if the microcontroller's

VDD power pins are powered on prior to the time a battery voltage is initially applied to the VBAT

pin.

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B1

Fixed:

Fixed in Rev C.

3.2 Hibernate POR may not reset the Hibernation module until VDD isapplied

Description:

If VDD is not powered when voltage is first applied to VBAT, the state of the Hibernation module is

indeterminate and the HIB signal may be asserted. In this indeterminate state, a lock condition can

occur in which the Hibernation module waits for a power-on-reset, but that reset cannot occur until

the module deasserts HIB. This issue is related to the errata Hibernation module may have higher

current draw than specified in data sheet under certain conditions on page 4.

Workaround:

The workaround implementation depends on the system-level power supply configuration. Forsystems that use a battery as the primary power source, an external voltage supervisor

(TPS383J25DBV or similar) circuit can be added to force the VDD power supply to start when the

battery voltage is first applied (see Figure 1). The voltage supervisor requires only 220 nA and

generates a 200-ms positive pulse to turn on the VDD regulator and activate the microcontoller's

internal POR circuit.

Figure 1. Workaround Circuit to Ensure Initial Power Up

*

* Additional Parts for Workaround

TPS3837J25

Voltage Supervisor*

RST

VBATVBAT

CTVDD

MR

Voltage

Regulator

or Switch

VOUTVIN

EN

10 K*

3.3 M(typ.)

VDD tosystem

HIB

Stellaris

Device

VBATVBAT

Low

Vf

Diode

VDD

VDD

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B1

Fixed:

Fixed in Rev C.

3.3 Power consumption increases if VDD is not restored after wakefrom hibernation

Description:

If a wake event occurs and VDD does not rise to specified levels, then the wake event is held off

until VDD is within specified levels. If a large delay occurs between the wake event and VDD reaching

specified levels, the VBAT current increases substantially to a typical value of 255 A until VDDreaches the specified levels, at which point the microcontroller comes out of hibernation and power

consumption returns to expected levels.

Workaround:

Ensure that VDD reaches specified levels within 250 s after the wake event occurs.


B1

Fixed:

Fixed in Rev C.

3.4 ESD protection on the VBAT pin does not meet specifications

Description:

The ESD protection on the VBAT pin fails when tested at 2 kV.Workaround:

Extra precaution should be taken to protect the part from ESD events. Some applications may

require system-level ESD protection on this pin.


B1

Fixed:

Fixed in Rev C.

3.5 Use of the VDD3ON mode to initiate hibernation damages the partDescription:

The VDD3ON mode is enabled by setting the VDD3ON bit in the Hibernation Control (HIBCTL)

register. Permanent damage can occur to the device if this mode is used.

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Workaround:

Do not use the VDD3ON mode to enter hibernation, instead use an external switch or regulator to

manage VDD power to the device.


B1

Fixed:

Fixed in Rev C.

3.6 Hibernate module power consumption higher than expected in

event wakeup configuration

Description:

With the Hibernation module configured for an external event wakeup, the current consumption of

the device is higher than expected. The Hibernation module clock does not shut down properly

during the hibernate asynchronous external wake mode resulting in extra current consumption.

Some devices properly shut down the clock the first time entering this mode and others do not.When waking from a hibernate event, the Hibernation module clock is always enabled. In subsequent

hibernate cycles, the oscillator is not shut down properly and remains active. Hibernate module

current consumption averages 21A with the clock disabled. The current consumption averages

31A with the Hibernation module clock enabled.

Workaround:

When the Hibernation module clock is not required during hibernation, software can disable it by

clearing theCLK32EN bit in the Hibernation Control (HIBCTL) register before going into hibernation

mode.


B1

Fixed:

Fixed in Rev C.

3.7 The Real-Time Clock gains or loses time going in and out of

hibernation when using a crystal

Description:

When using a 4.194304-MHz crystal, the Real-Time clock in the Hibernation module gains or loses

a small amount of time (on the order of one second over a 24-hour period when cycling hibernate

mode 4 times a minute) when going in and out of hibernation.

Workaround:

Use an external 32.768-kHz oscillator as the source for the Hibernation module clock.


B1

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Fixed:

Fixed in Rev C.

3.8 Low-battery detect circuit is powered down during hibernate

Description:

The low-battery detect feature on the VBAT input is only valid when VDD power is present. As a result:

Because the battery is not electrically loaded when VDD is present, the low-battery detect circuit

may not reflect the actual battery status.

In Hibernate mode, a low-battery condition may prevent wake until the battery is completely

depleted.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

4 Internal Memory

4.1 Cumulative page erases may introduce bit errors in Flash memory

Description:

Cumulative page erases anywhere in the Flash memory array may introduce bit errors. The bit error

is not confined to the page being erased or the 4-KB block but could be in any page in the Flashmemory. A page erase is used to erase a 1-KB page so it can be rewritten. A mass erase erases

the entire Flash memory array (all pages). A bit error means that a bit may change from 0 to 1 or 1

to 0.

Workaround:


1. Minimize total page erases to less than 3000 between mass erases for the lifetime of the product.

After each mass erase, an additional 3000 page erase operations are allowed before bit errors

may be introduced. At the rate of one page erase per week, this issue would not be seen over

at least 17 years.

2. Perform CRC checks on all Flash memory after page erases to increase the chances of detecting

the issue. The two CRC functions built into ROM can assist in this.


B1

Fixed:

Fixed in Rev C.

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4.2 Flash Write Buffer does not function above 50 MHz

Description:

The Flash Write Buffer does not successfully program the Flash memory at speeds above 50 MHz.

Workaround:

Lower the speed of the system clock to 50 MHz or less while programming the Flash memory.


B1

Fixed:

Fixed in Rev C.

5 ROM

5.1 Ethernet fails to connect when using the Boot loader software in

ROM

Description:

The Ethernet controller takes longer to connect than the Boot loader software in ROM allows.

Workaround:

Download the Boot loader software in the on-chip Flash memory and ensure that the Ethernet

connection uses MDI mode only.


B1

Fixed:

Fixed in Rev C.

5.2 Some ROM functions are unsupported

Description:

The following functions are unsupported in ROM:

CANBitRateSet

GPIOPinConfigure

GPIOPinTypeI2S

I2CSlaveIntClearEx I2CSlaveIntDisableEx

I2CSlaveIntEnableEx

I2CSlaveIntStatusEx

I2SIntClear

I2SIntDisable

I2SIntEnable

I2SIntStatus

I2SMasterClockSelect

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I2SRxConfigSet

I2SRxDataGet

I2SRxDataGetNonBlocking

I2SRxDisable

I2SRxEnable

I2SRxFIFOLevelGet

I2SRxFIFOLimitGet

I2SRxFIFOLimitSet I2STxConfigSet

I2STxDataPut

I2STxDataPutNonBlocking

I2STxDisable

I2STxEnable

I2STxFIFOLevelGet

I2STxFIFOLimitGet

I2STxFIFOLimitSet

I2STxRxConfigSet

I2STxRxDisable

I2SRxDataGet

I2STxRxEnable

SysCtlDelay

SysCtlI2SMClkSet

UARTBusy

UARTFIFODisable

UARTFIFOEnable

UARTRxErrorClear

UARTRxErrorGet

UARTTxIntModeGet

UARTTxIntModeSet

uDMAChannelSelectDefault

uDMAChannelSelectSecondary

uDMAIntClear

uDMAIntStatus USBDevEndpointConfigGet

USBEndpointDataAvail

USBEndpointDMAChannel

USBEndpointDMADisable

USBEndpointDMAEnable

USBModeGet

USBOTGHostRequest

Workaround:

Code for these functions is included in the current version of StellarisWare, which can be downloaded

from the website at http://www.luminarymicro.com/products/software_updates.html.


B1

Fixed:

Fixed in Rev C.

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5.3 ROM mapping check for the Boot loader does not function properly

Description:

Before the processor is released from the reset state, the System Control module is supposed to

check address 0x0000.0004 of Flash memory looking for a reset vector that is not 0xFFFF.FFFF.

If an initialized reset vector is found, Flash memory is mapped to address 0x0000.0000, otherwise

ROM is mapped to address 0x0000.0000. Currently, the System Control module errantly checksaddress 0x0000.0008, which is the NMI vector. So, in situations where a valid reset vector (address

0x0000.0004) has been programmed, but the NMI vector has not been programmed, the ROM is

errantly mapped to zero preventing the application that is stored in Flash memory from being executed

out of reset.

Workaround:

Ensure that the NMI vector is always programmed.


B1

Fixed:

Not fixed in Rev C.

6 GPIO

6.1 Port B [1:0] pins require external pull-up resistors

Description:

The internal pull-up resistors are not effective for the Port B0 and B1 pins.

Workaround:

External pull-up resistors must be used on these two pins.


B1

Fixed:

Fixed in Rev C.

7 EPI

7.1 EPI dual-chip select function does not work

Description:

The Dual CSn Configuration mode (CSCFG=0x2) and the ALE with Dual CSn Configuration mode

(CSCFG=-x3) controlled by the EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) register do not

function. System designs should use ALE Configuration mode (CSCFG=0x0) or CSn Configuration

mode (CSCFG=0x1).

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Workaround:

None.


B1

Fixed:

Fixed in Rev C.

7.2 EPI Host-Bus 16 mode does not work

Description:

The Host-Bus 16 mode (MODE=0x3) controlled by the EPI Configuration (EPICFG) register do not

function.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

7.3 Clock signal in EPI General-Purpose mode is inverted

Description:

The clock signal that is output on the EPI0S31 signal in General-Purpose mode is inverted.

Workaround:

Use the opposite edge for timing when designing with this interface.


B1

Fixed:

Fixed in Rev C.

8 UART

8.1 UART Smart Card (ISO 7816) mode does not function

Description:

The UnTX signal does not function correctly as the bit clock in Smart Card mode.

Workaround:

None.

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B1

Fixed:

Fixed in Rev C.

8.2 When in IrDA mode, the UnRx signal requires configuration evenif not used

Description:

When in IrDA mode, the transmitter may not function correctly if the UnRx signal is not used.

Workaround:

When in IrDA mode, if the application does not require the use of the UnRx signal, the GPIO pin

that has the UnRx signal as an alternate function must be configured as the UnRx signal and pulled

High.


B1

Fixed:

Fixed in Rev C.

9 SSI

9.1 An interrupt is not generated when using DMA with the SSI module

if the EOT bit is set

Description:

When using the primary DMA channels with the SSI module, an interrupt is not generated on

transmit DMA completion if the EOT bit (bit 4 of the SSICR1 register) is enabled.

Workaround:

Use the alternate DMA channels for the SSI module.


B1

Fixed:

Fixed in Rev C.

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10 I2S

10.1 Some bits in the I2SMCLKCFG register do not function

Description:

The top 2 bits of theRXI and TXI bit fields in the I2SMCLKCFG register do not function (bits [29:28]

ofRXI and bits [13:12] ofTXI). The RXI and TXI fields contain the 10-bit integer input for the

receive and transmit clock generator, respectively. The remaining 8 bits in each field function

correctly, so most of the possible integer input choices can be used in system design.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

10.2 I2S SCLK signal is inverted in certain modes

Description:

When the I2S controller is operating as a receiver in SCLK Master mode, the WS signal is latched

on the rising edge of SCLK, not the falling edge. In addition, when the controller is operating as a

transmitter in SCLK Slave mode, the data is launched on the rising edge of SCLK, not the falling

edge.

Workaround:

For the transmitter, there are two possible workarounds for this issue:

1. Ensure that the I2S0TXSCK signal leads the I2S0TXWS signal by at least 4 ns.

2. Configure as I2S mode with DAC in Left-Justified audio format.

For the receiver, ensure that the CODEC is configured as the SCLK master, and the I 2S receive

module is configured as the SCLK slave.


B1

Fixed:

Fixed in Rev C.

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11 Ethernet Controller

11.1 Ethernet receive packet corruption may occur when using optional

auto-clock gating

Description:

Ethernet receive packets may be corrupted if the ACG bit in the Run-Mode Clock Configuration

(RCC) register is set.

Workaround:

Do not set the ACG bit in the RCC register.


B1

Fixed:

Fixed in Rev C.

11.2 Ethernet packet count decremented before the FCS is read

Description:

The Number of Packets Register (NPR) decrements in the cycle before the Frame Check Sequence

(FCS) is read from the Receive FIFO. As a result, software may incorrectly believe the entire packet

has been received when it has not.

Workaround:

Use either the DriverLib routine or compare the number of bytes received to the Length field from

the Frame to determine when the FIFO is empty.


B1

Fixed:

Will not be fixed.

11.3 Ethernet packet loss with cables longer than 50 meters

Description:

The microcontroller experiences some packet loss with Ethernet cables longer than 50 meters in

normal operating conditions.

Workaround:


1. Add 10 resistor to the center-tap of the transformer as shown in the figure. These resistors

should be replaced by a direct connection for silicon that has this item fixed.

2. Continue using the recommended circuit, but limit cable lengths to 50 meters.

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Workaround:

Connect the USB0VBUS input to VBUS in all modes. In addition, connect the USB0ID pin to ground

for Host mode operation and to VDD for Device mode operation using the DEVMOD bit in the USB

General-Purpose Control and Status (USBGPCS) register.


B1

Fixed:

Fixed in Rev C.

12.2 Latch up may occur if power is applied to the VBUS pin but not to

VDD

Description:

If power is applied to the VBUS pin but not to VDD, the microcontroller may latch up and or draw

excessive current. This condition can occur if the microcontroller is unpowered and is connected

as a USB device or OTG B.

Workaround:

Power up the microcontroller before attaching the USB cable. Also, the USB cable must be detached

before powering down the microcontroller.


B1

Fixed:

Fixed in Rev C.

13 Electrical Characteristics

13.1 Power-on event may disrupt operation

Description:

Incorrect power sequencing during power up can disrupt operation and potentially cause device

failure.

Workaround:

VDDC must be applied approximately 50 s before VDD. Normally VDDC is controlled by the parts

internal LDO voltage regulator. The workaround requires the addition of an external regulator (see

Figure 3) to ensure that VDDC sequencing requirements are met (see Figure 4). Recommendedregulators include FAN1112SX (SOT223) and FAN2558S12X (SOT23-5).

This fix mitigates the on-chip power issue, but does not solve it completely. During development,

the Flash memory should also be reprogrammed (using LMflash or another programming tool) at

least once a week.

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Figure 3. Configuration of External Regulator

Existing

3.3 V

Regulator

1.2 VNew

1.2 V

Regulator

VDD

VDD

VDD

VDD

LDO

VDDC

VDDC

3.3 V+5 V

Figure 4. VDDC Sequencing Requirements

VDDC

VDD

VDDC

VDD

Default Power

Sequence

Modified Power

Sequence

Detailed characterization is ongoing. Contact the Applications Support Team for the latest information.


B1

Fixed:

Fixed in Rev C.

13.2 Momentarily exceeding VIN ratings on any pin can cause latch-up

Description:

To avoid latch-up, the maximum DC ratings of the part must be strictly enforced. The most common

violation of the VIN electrical specification can occur when a mechanical switch or contact is connected

directly to a GPIO or special function (RST, WAKE, ...) pin. The circuit shown in Figure 5 on page 19

typically has stray inductance and capacitance that can cause a voltage glitch when the switch

transitions, as shown in Figure 6 on page 19. The magnitude of the glich may exceed the VIN in the

maximum DC ratings table in the Electrical Characteristics chapter. Figure 7 on page 19 shows an

improved circuit that eliminates the glitch.

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Figure 5. Incorrect Reset Circuitry

PU

RST

Stellaris

R

VDD

Figure 6. Excessive Undershoot Voltage on Reset

Voltage

Time

0 V

Workaround:

Use a circuit as shown in Figure 7 on page 19. In this circuit, RS should be less than or equal to

RPU/10. C1 should be matched to RPU to achieve a suitable tRC for the application. Typical values

are:

RPU = 10 k

RS = 470

C1 = 0.01 F

Figure 7. Recommended Reset Circuitry

PU

C1

RS

RST

Stellaris

R

VDD

After implementing the circuit shown in Figure 7 on page 19, confirm that the voltage on the RST

input has a curve similar to the one in Figure 8 on page 20, and that the VIN specification is not

exceeded.

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Figure 8. Recommended Voltage on Reset

Voltage

Time

0 V


B1

Fixed:

Fixed in Rev C.

Copyright 2008-2009 Texas Instruments Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of

Texas Instruments. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names

and brands may be claimed as the property of others.

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August 19, 2009/Rev. 1.6

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Stellaris

LM3S9790 B1 Errata

8/2/2019 Errata Lm3s9790

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I M P O R T A N T N O T I C E

T e x a s I n s t r u m e n t s I n c o r p o r a t e d a n d i t s s u b s i d i a r i e s ( T I ) r e s e r v e t h e r i g h t t o m a k e c o r r e c t i o n s , m o d i f i c a t i o n s , e n h a n c e m e n t s , i m p r o v e m e n t s , a n d o t h e r c h a n g e s t o i t s p r o d u c t s a n d s e r v i c e s a t a n y t i m e a n d t o d i s c o n t i n u e a n y p r o d u c t o r s e r v i c e w i t h o u t n o t i c e . C u s t o m e r s s h o u l do b t a i n t h e l a t e s t r e l e v a n t i n f o r m a t i o n b e f o r e p l a c i n g o r d e r s a n d s h o u l d v e r i f y t h a t s u c h i n f o r m a t i o n i s c u r r e n t a n d c o m p l e t e . A l l p r o d u c t s a r e s o l d s u b j e c t t o T I s t e r m s a n d c o n d i t i o n s o f s a l e s u p p l i e d a t t h e t i m e o f o r d e r a c k n o w l e d g m e n t .

T I w a r r a n t s p e r f o r m a n c e o f i t s h a r d w a r e p r o d u c t s t o t h e s p e c i f i c a t i o n s a p p l i c a b l e a t t h e t i m e o f s a l e i n a c c o r d a n c e w i t h T I s s t a n d a r d

w a r r a n t y . T e s t i n g a n d o t h e r q u a l i t y c o n t r o l t e c h n i q u e s a r e u s e d t o t h e e x t e n t T I d e e m s n e c e s s a r y t o s u p p o r t t h i s w a r r a n t y . E x c e p t w h e r e m a n d a t e d b y g o v e r n m e n t r e q u i r e m e n t s , t e s t i n g o f a l l p a r a m e t e r s o f e a c h p r o d u c t i s n o t n e c e s s a r i l y p e r f o r m e d .

T I a s s u m e s n o l i a b i l i t y f o r a p p l i c a t i o n s a s s i s t a n c e o r c u s t o m e r p r o d u c t d e s i g n . C u s t o m e r s a r e r e s p o n s i b l e f o r t h e i r p r o d u c t s a n d a p p l i c a t i o n s u s i n g T I c o m p o n e n t s . T o m i n i m i z e t h e r i s k s a s s o c i a t e d w i t h c u s t o m e r p r o d u c t s a n d a p p l i c a t i o n s , c u s t o m e r s s h o u l d p r o v i d e a d e q u a t e d e s i g n a n d o p e r a t i n g s a f e g u a r d s .

T I d o e s n o t w a r r a n t o r r e p r e s e n t t h a t a n y l i c e n s e , e i t h e r e x p r e s s o r i m p l i e d , i s g r a n t e d u n d e r a n y T I p a t e n t r i g h t , c o p y r i g h t , m a s k w o r k r i g h t , o r o t h e r T I i n t e l l e c t u a l p r o p e r t y r i g h t r e l a t i n g t o a n y c o m b i n a t i o n , m a c h i n e , o r p r o c e s s i n w h i c h T I p r o d u c t s o r s e r v i c e s a r e u s e d . I n f o r m a t i o np u b l i s h e d b y T I r e g a r d i n g t h i r d - p a r t y p r o d u c t s o r s e r v i c e s d o e s n o t c o n s t i t u t e a l i c e n s e f r o m T I t o u s e s u c h p r o d u c t s o r s e r v i c e s o r a w a r r a n t y o r e n d o r s e m e n t t h e r e o f . U s e o f s u c h i n f o r m a t i o n m a y r e q u i r e a l i c e n s e f r o m a t h i r d p a r t y u n d e r t h e p a t e n t s o r o t h e r i n t e l l e c t u a l p r o p e r t y o f t h e t h i r d p a r t y , o r a l i c e n s e f r o m T I u n d e r t h e p a t e n t s o r o t h e r i n t e l l e c t u a l p r o p e r t y o f T I .

R e p r o d u c t i o n o f T I i n f o r m a t i o n i n T I d a t a b o o k s o r d a t a s h e e t s i s p e r m i s s i b l e o n l y i f r e p r o d u c t i o n i s w i t h o u t a l t e r a t i o n a n d i s a c c o m p a n i e d b y a l l a s s o c i a t e d w a r r a n t i e s , c o n d i t i o n s , l i m i t a t i o n s , a n d n o t i c e s . R e p r o d u c t i o n o f t h i s i n f o r m a t i o n w i t h a l t e r a t i o n i s a n u n f a i r a n d d e c e p t i v e b u s i n e s s p r a c t i c e . T I i s n o t r e s p o n s i b l e o r l i a b l e f o r s u c h a l t e r e d d o c u m e n t a t i o n . I n f o r m a t i o n o f t h i r d p a r t i e s m a y b e s u b j e c t t o a d d i t i o n a l r e s t r i c t i o n s .

R e s a l e o f T I p r o d u c t s o r s e r v i c e s w i t h s t a t e m e n t s d i f f e r e n t f r o m o r b e y o n d t h e p a r a m e t e r s s t a t e d b y T I f o r t h a t p r o d u c t o r s e r v i c e v o i d s a l l

e x p r e s s a n d a n y i m p l i e d w a r r a n t i e s f o r t h e a s s o c i a t e d T I p r o d u c t o r s e r v i c e a n d i s a n u n f a i r a n d d e c e p t i v e b u s i n e s s p r a c t i c e . T I i s n o t r e s p o n s i b l e o r l i a b l e f o r a n y s u c h s t a t e m e n t s .

T I p r o d u c t s a r e n o t a u t h o r i z e d f o r u s e i n s a f e t y - c r i t i c a l a p p l i c a t i o n s ( s u c h a s l i f e s u p p o r t ) w h e r e a f a i l u r e o f t h e T I p r o d u c t w o u l d r e a s o n a b l y b e e x p e c t e d t o c a u s e s e v e r e p e r s o n a l i n j u r y o r d e a t h , u n l e s s o f f i c e r s o f t h e p a r t i e s h a v e e x e c u t e d a n a g r e e m e n t s p e c i f i c a l l y g o v e r n i n g s u c h u s e . B u y e r s r e p r e s e n t t h a t t h e y h a v e a l l n e c e s s a r y e x p e r t i s e i n t h e s a f e t y a n d r e g u l a t o r y r a m i f i c a t i o n s o f t h e i r a p p l i c a t i o n s , a n d a c k n o w l e d g e a n d a g r e e t h a t t h e y a r e s o l e l y r e s p o n s i b l e f o r a l l l e g a l , r e g u l a t o r y a n d s a f e t y - r e l a t e d r e q u i r e m e n t s c o n c e r n i n g t h e i r p r o d u c t s a n d a n y u s e o f T I p r o d u c t s i n s u c h s a f e t y - c r i t i c a l a p p l i c a t i o n s , n o t w i t h s t a n d i n g a n y a p p l i c a t i o n s - r e l a t e d i n f o r m a t i o n o r s u p p o r t t h a t m a y b e p r o v i d e d b y T I . F u r t h e r , B u y e r s m u s t f u l l y i n d e m n i f y T I a n d i t s r e p r e s e n t a t i v e s a g a i n s t a n y d a m a g e s a r i s i n g o u t o f t h e u s e o f T I p r o d u c t s i n s u c h s a f e t y - c r i t i c a l a p p l i c a t i o n s .

T I p r o d u c t s a r e n e i t h e r d e s i g n e d n o r i n t e n d e d f o r u s e i n m i l i t a r y / a e r o s p a c e a p p l i c a t i o n s o r e n v i r o n m e n t s u n l e s s t h e T I p r o d u c t s a r e s p e c i f i c a l l y d e s i g n a t e d b y T I a s m i l i t a r y - g r a d e o r " e n h a n c e d p l a s t i c . " O n l y p r o d u c t s d e s i g n a t e d b y T I a s m i l i t a r y - g r a d e m e e t m i l i t a r y s p e c i f i c a t i o n s . B u y e r s a c k n o w l e d g e a n d a g r e e t h a t a n y s u c h u s e o f T I p r o d u c t s w h i c h T I h a s n o t d e s i g n a t e d a s m i l i t a r y - g r a d e i s s o l e l y a t t h e B u y e r ' s r i s k , a n d t h a t t h e y a r e s o l e l y r e s p o n s i b l e f o r c o m p l i a n c e w i t h a l l l e g a l a n d r e g u l a t o r y r e q u i r e m e n t s i n c o n n e c t i o n w i t h s u c h u s e .

T I p r o d u c t s a r e n e i t h e r d e s i g n e d n o r i n t e n d e d f o r u s e i n a u t o m o t i v e a p p l i c a t i o n s o r e n v i r o n m e n t s u n l e s s t h e s p e c i f i c T I p r o d u c t s a r e d e s i g n a t e d b y T I a s c o m p l i a n t w i t h I S O / T S 1 6 9 4 9 r e q u i r e m e n t s . B u y e r s a c k n o w l e d g e a n d a g r e e t h a t , i f t h e y u s e a n y n o n - d e s i g n a t e d p r o d u c t s i n a u t o m o t i v e a p p l i c a t i o n s , T I w i l l n o t b e r e s p o n s i b l e f o r a n y f a i l u r e t o m e e t s u c h r e q u i r e m e n t s .

F o l l o w i n g a r e U R L s w h e r e y o u c a n o b t a i n i n f o r m a t i o n o n o t h e r T e x a s I n s t r u m e n t s p r o d u c t s a n d a p p l i c a t i o n s o l u t i o n s :

P r o d u c t s A p p l i c a t i o n s A m p l i f i e r s a m p l i f i e r . t i . c o m A u d i o w w w . t i . c o m / a u d i o D a t a C o n v e r t e r s d a t a c o n v e r t e r . t i . c o m A u t o m o t i v e w w w . t i . c o m / a u t o m o t i v e D L P P r o d u c t s w w w . d l p . c o m B r o a d b a n d w w w . t i . c o m / b r o a d b a n d D S P d s p . t i . c o m D i g i t a l C o n t r o l w w w . t i . c o m / d i g i t a l c o n t r o l C l o c k s a n d T i m e r s w w w . t i . c o m / c l o c k s M e d i c a l w w w . t i . c o m / m e d i c a l I n t e r f a c e i n t e r f a c e . t i . c o m M i l i t a r y w w w . t i . c o m / m i l i t a r y L o g i c l o g i c . t i . c o m O p t i c a l N e t w o r k i n g w w w . t i . c o m / o p t i c a l n e t w o r k P o w e r M g m t p o w e r . t i . c o m S e c u r i t y w w w . t i . c o m / s e c u r i t y M i c r o c o n t r o l l e r s m i c r o c o n t r o l l e r . t i . c o m T e l e p h o n y w w w . t i . c o m / t e l e p h o n y R F I D w w w . t i - r f i d . c o m V i d e o & I m a g i n g w w w . t i . c o m / v i d e o R F / I F a n d Z i g B e e S o l u t i o n s w w w . t i . c o m / l p r f W i r e l e s s w w w . t i . c o m / w i r e l e s s

M a i l i n g A d d r e s s : T e x a s I n s t r u m e n t s , P o s t O f f i c e B o x 6 5 5 3 0 3 , D a l l a s , T e x a s 7 5 2 6 5 C o p y r i g h t 2 0 0 9 , T e x a s I n s t r u m e n t s I n c o r p o r a t e d
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