Efficient VLSI Architectures for Image Compression Algorithms

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  • Efficient VLSI Architectures for Image Compression Algorithms

    Vijay Kumar Sharma

    Department of Electronics & Communication Engineering National Institute of Technology Rourkela

    Rourkela-769008, Odisha, India

  • Efficient VLSI Architectures for Image Compression Algorithms

    Thesis submitted in partial fulfillment of the requirements for the degree of

    Master of Technology (Research) In

    Electronics and Communication Engineering

    By

    Vijay Kumar Sharma (Roll No. 609EC101)

    January 2012

    Under the guidance of

    Dr. U. C. Pati Dr. K. K. Mahapatra

    Department of Electronics & Communication Engineering National Institute of Technology Rourkela

    Rourkela-769008,Odisha, India

  • To all who have shown Love and Support

  • Department of Electronics & Communication Engineering

    National Institute of Technology Rourkela Rourkela-769008, Odisha, India

    Certificate

    This is to certify that the thesis entitled Efficient VLSI Architectures for Image Compression Algorithms by Mr. Vijay Kumar Sharma, submitted to the National Institute of Technology, Rourkela for the degree of Master of Technology (Research), is a record of an original research work carried out by him under our supervision in the department of Electronics and Communication Engineering during session 2009-2011. We believe that the thesis fulfills the part of the requirements for the award of degree of Master of Technology (Research). Neither this thesis nor any part of it has been submitted elsewhere for the degree or academic award.

    Prof. U. C. Pati Department of Electronics and Communication Engineering

    National Institute of Technology, Rourkela

    Prof. K. K. Mahapatra Department of Electronics and Communication Engineering

    National Institute of Technology, Rourkela

  • Acknowledgement

    I am grateful to my research advisors Prof. U. C. Pati and Prof. K. K. Mahapatra for providing me the opportunity to realize this work. They inspired, motivated, encouraged and gave me full freedom to do my work with proper suggestions throughout my research work. I am indebted to Prof. K.K. Mahapatra for his kind and moral support throughout my academics at NIT Rourkela.

    I am also grateful to NIT Rourkela for providing adequate facilities in my research work.

    I acknowledge MHRD and DIT (Ministry of Information & Communication Technology), Govt. of India, for giving financial support.

    My special thanks to Prof. S. K. Patra, Prof. D. P. Acharya and Prof. A. K. Swain for their help and valuable suggestions. I would like to thank Sushant sir, my senior, for helping me in VLSI.

    I am thankful to Prof. S. Meher and Prof. S. K. Behera for his inspiration and support. I am also thankful to Prof. G. S. Rath, Prof. B. D. Sahoo, Prof. K. B. Mohanty and Prof. N.V. L. N. Murty for their valuable support in my research work.

    I would like to give special thank to Prakash sir, Preeti madam and Ranjan sir who helped and supported me throughout my research work.

    I must thank Karupannan sir, Kanhu sir, Jagannath and Tom sir for their support and help. I also thank Srinivas sir and Venkatratnam sir for their good attitude and behavior.

    I sincerely thank to all my friends, Research scholars of ECE Department, M.Tech (VLSI) students and all academic and non-teaching staffs in NIT Rourkela who helped me.

    Vijay Kumar Sharma

  • v

    Contents Certificate III Acknowledgement IV Contents V List of Figures VII List of Tables XIII Abstract 1 Chapter 1 Introduction 3

    1.1 Motivation 4 1.2 Background 6 1.3 Objective of the Thesis 9 1.4 Chapter Wise Contribution of the Thesis 10 1.5 Summary 11

    Chapter 2 Image Compression 13

    2.1 Introduction 13 2.2 Image representation and classification 14 2.3 Image Quality Measurement Metric 15 2.4 Image Compression Model 17 2.5 Transform based Image Coding 19 2.6 JPEG baseline Image Coding 21 2.7 Discrete Cosine Transform (DCT) 23

    2.7.1 2-D DCT Equation 24

    2.7.2 Energy Compaction Property of 2-D DCT 25

    2.7.3 Image Reconstruction by Selective DCT Coefficients 27

    2.8 Separable Discrete Hartley Transform (SDHT) 31 2.9 Conclusions 35

    Chapter 3 Distributed Arithmetic and Its VLSI Architecture 36

    3.1 Introduction 36 3.2 Systolic Architecture 37 3.3 ROM based Distributed Arithmetic (DA) 39

  • vi

    3.3.1 FPGA Implementation of 8-points 1-D DHT using ROM 45 based DA

    3.3.2 FPGA Implementation of SDHT using ROM based DA 46

    3.4 ROM Free DA 48

    3.4.1 FPGA Implementation of DCT using ROM free DA 51

    3.4.2 Area and Power Efficient VLSI Architecture of 8x1 1-D DCT 58

    3.5 SDHT Implementation using ROM free DA 64

    3.6 Conclusions 67

    Chapter 4 Efficient JPEG Image Compression Architecture 68

    4.1 Introduction 68 4.2 Normalization matrix for hardware simplification in JPEG 68 4.3 Efficient Architecture from DCT to Quantization and Re-ordering 72 4.4 Huffman Coding Architecture Implementation in FPGA for JPEG 78 4.5 Conclusions 93

    Chapter 5 Direct Computation of 8x8 2-D DCT Coefficients Equation 94 and Its Hardware Architecture

    5.1 Introduction 94 5.2 Equation for Direct computation of 2-D DCT 95 5.3 Non-recursive VLSI architecture of 2-D DCT 102 5.4 JPEG Image Compression Architecture using Proposed 114

    Non-recursive 2-D DCT

    5.5 Conclusions 117

    Chapter 6 Summary and Conclusions 118

    6.1 Summary 118 6.2 General Conclusions 119 6.3 Future Scope 120

    Appendix A 121

    Appendix B 122

  • vii

    List of Figures

    Fig.1.1 Energy efficiency on different implementations [23] 5 Fig.1.2 Trends in power consumption and battery capacity [37] 6 Fig.2.1 Representation of digital image in two dimensional 14